1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // RTC driver for Maxim MAX77686 and MAX77802
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright (C) 2012 Samsung Electronics Co.Ltd
6*4882a593Smuzhiyun //
7*4882a593Smuzhiyun // based on rtc-max8997.c
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/i2c.h>
10*4882a593Smuzhiyun #include <linux/slab.h>
11*4882a593Smuzhiyun #include <linux/rtc.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/mutex.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/mfd/max77686-private.h>
17*4882a593Smuzhiyun #include <linux/irqdomain.h>
18*4882a593Smuzhiyun #include <linux/regmap.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define MAX77686_I2C_ADDR_RTC (0x0C >> 1)
21*4882a593Smuzhiyun #define MAX77620_I2C_ADDR_RTC 0x68
22*4882a593Smuzhiyun #define MAX77686_INVALID_I2C_ADDR (-1)
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* Define non existing register */
25*4882a593Smuzhiyun #define MAX77686_INVALID_REG (-1)
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* RTC Control Register */
28*4882a593Smuzhiyun #define BCD_EN_SHIFT 0
29*4882a593Smuzhiyun #define BCD_EN_MASK BIT(BCD_EN_SHIFT)
30*4882a593Smuzhiyun #define MODEL24_SHIFT 1
31*4882a593Smuzhiyun #define MODEL24_MASK BIT(MODEL24_SHIFT)
32*4882a593Smuzhiyun /* RTC Update Register1 */
33*4882a593Smuzhiyun #define RTC_UDR_SHIFT 0
34*4882a593Smuzhiyun #define RTC_UDR_MASK BIT(RTC_UDR_SHIFT)
35*4882a593Smuzhiyun #define RTC_RBUDR_SHIFT 4
36*4882a593Smuzhiyun #define RTC_RBUDR_MASK BIT(RTC_RBUDR_SHIFT)
37*4882a593Smuzhiyun /* RTC Hour register */
38*4882a593Smuzhiyun #define HOUR_PM_SHIFT 6
39*4882a593Smuzhiyun #define HOUR_PM_MASK BIT(HOUR_PM_SHIFT)
40*4882a593Smuzhiyun /* RTC Alarm Enable */
41*4882a593Smuzhiyun #define ALARM_ENABLE_SHIFT 7
42*4882a593Smuzhiyun #define ALARM_ENABLE_MASK BIT(ALARM_ENABLE_SHIFT)
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define REG_RTC_NONE 0xdeadbeef
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /*
47*4882a593Smuzhiyun * MAX77802 has separate register (RTCAE1) for alarm enable instead
48*4882a593Smuzhiyun * using 1 bit from registers RTC{SEC,MIN,HOUR,DAY,MONTH,YEAR,DATE}
49*4882a593Smuzhiyun * as in done in MAX77686.
50*4882a593Smuzhiyun */
51*4882a593Smuzhiyun #define MAX77802_ALARM_ENABLE_VALUE 0x77
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun enum {
54*4882a593Smuzhiyun RTC_SEC = 0,
55*4882a593Smuzhiyun RTC_MIN,
56*4882a593Smuzhiyun RTC_HOUR,
57*4882a593Smuzhiyun RTC_WEEKDAY,
58*4882a593Smuzhiyun RTC_MONTH,
59*4882a593Smuzhiyun RTC_YEAR,
60*4882a593Smuzhiyun RTC_DATE,
61*4882a593Smuzhiyun RTC_NR_TIME
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun struct max77686_rtc_driver_data {
65*4882a593Smuzhiyun /* Minimum usecs needed for a RTC update */
66*4882a593Smuzhiyun unsigned long delay;
67*4882a593Smuzhiyun /* Mask used to read RTC registers value */
68*4882a593Smuzhiyun u8 mask;
69*4882a593Smuzhiyun /* Registers offset to I2C addresses map */
70*4882a593Smuzhiyun const unsigned int *map;
71*4882a593Smuzhiyun /* Has a separate alarm enable register? */
72*4882a593Smuzhiyun bool alarm_enable_reg;
73*4882a593Smuzhiyun /* I2C address for RTC block */
74*4882a593Smuzhiyun int rtc_i2c_addr;
75*4882a593Smuzhiyun /* RTC interrupt via platform resource */
76*4882a593Smuzhiyun bool rtc_irq_from_platform;
77*4882a593Smuzhiyun /* Pending alarm status register */
78*4882a593Smuzhiyun int alarm_pending_status_reg;
79*4882a593Smuzhiyun /* RTC IRQ CHIP for regmap */
80*4882a593Smuzhiyun const struct regmap_irq_chip *rtc_irq_chip;
81*4882a593Smuzhiyun /* regmap configuration for the chip */
82*4882a593Smuzhiyun const struct regmap_config *regmap_config;
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun struct max77686_rtc_info {
86*4882a593Smuzhiyun struct device *dev;
87*4882a593Smuzhiyun struct i2c_client *rtc;
88*4882a593Smuzhiyun struct rtc_device *rtc_dev;
89*4882a593Smuzhiyun struct mutex lock;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun struct regmap *regmap;
92*4882a593Smuzhiyun struct regmap *rtc_regmap;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun const struct max77686_rtc_driver_data *drv_data;
95*4882a593Smuzhiyun struct regmap_irq_chip_data *rtc_irq_data;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun int rtc_irq;
98*4882a593Smuzhiyun int virq;
99*4882a593Smuzhiyun int rtc_24hr_mode;
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun enum MAX77686_RTC_OP {
103*4882a593Smuzhiyun MAX77686_RTC_WRITE,
104*4882a593Smuzhiyun MAX77686_RTC_READ,
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* These are not registers but just offsets that are mapped to addresses */
108*4882a593Smuzhiyun enum max77686_rtc_reg_offset {
109*4882a593Smuzhiyun REG_RTC_CONTROLM = 0,
110*4882a593Smuzhiyun REG_RTC_CONTROL,
111*4882a593Smuzhiyun REG_RTC_UPDATE0,
112*4882a593Smuzhiyun REG_WTSR_SMPL_CNTL,
113*4882a593Smuzhiyun REG_RTC_SEC,
114*4882a593Smuzhiyun REG_RTC_MIN,
115*4882a593Smuzhiyun REG_RTC_HOUR,
116*4882a593Smuzhiyun REG_RTC_WEEKDAY,
117*4882a593Smuzhiyun REG_RTC_MONTH,
118*4882a593Smuzhiyun REG_RTC_YEAR,
119*4882a593Smuzhiyun REG_RTC_DATE,
120*4882a593Smuzhiyun REG_ALARM1_SEC,
121*4882a593Smuzhiyun REG_ALARM1_MIN,
122*4882a593Smuzhiyun REG_ALARM1_HOUR,
123*4882a593Smuzhiyun REG_ALARM1_WEEKDAY,
124*4882a593Smuzhiyun REG_ALARM1_MONTH,
125*4882a593Smuzhiyun REG_ALARM1_YEAR,
126*4882a593Smuzhiyun REG_ALARM1_DATE,
127*4882a593Smuzhiyun REG_ALARM2_SEC,
128*4882a593Smuzhiyun REG_ALARM2_MIN,
129*4882a593Smuzhiyun REG_ALARM2_HOUR,
130*4882a593Smuzhiyun REG_ALARM2_WEEKDAY,
131*4882a593Smuzhiyun REG_ALARM2_MONTH,
132*4882a593Smuzhiyun REG_ALARM2_YEAR,
133*4882a593Smuzhiyun REG_ALARM2_DATE,
134*4882a593Smuzhiyun REG_RTC_AE1,
135*4882a593Smuzhiyun REG_RTC_END,
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun /* Maps RTC registers offset to the MAX77686 register addresses */
139*4882a593Smuzhiyun static const unsigned int max77686_map[REG_RTC_END] = {
140*4882a593Smuzhiyun [REG_RTC_CONTROLM] = MAX77686_RTC_CONTROLM,
141*4882a593Smuzhiyun [REG_RTC_CONTROL] = MAX77686_RTC_CONTROL,
142*4882a593Smuzhiyun [REG_RTC_UPDATE0] = MAX77686_RTC_UPDATE0,
143*4882a593Smuzhiyun [REG_WTSR_SMPL_CNTL] = MAX77686_WTSR_SMPL_CNTL,
144*4882a593Smuzhiyun [REG_RTC_SEC] = MAX77686_RTC_SEC,
145*4882a593Smuzhiyun [REG_RTC_MIN] = MAX77686_RTC_MIN,
146*4882a593Smuzhiyun [REG_RTC_HOUR] = MAX77686_RTC_HOUR,
147*4882a593Smuzhiyun [REG_RTC_WEEKDAY] = MAX77686_RTC_WEEKDAY,
148*4882a593Smuzhiyun [REG_RTC_MONTH] = MAX77686_RTC_MONTH,
149*4882a593Smuzhiyun [REG_RTC_YEAR] = MAX77686_RTC_YEAR,
150*4882a593Smuzhiyun [REG_RTC_DATE] = MAX77686_RTC_DATE,
151*4882a593Smuzhiyun [REG_ALARM1_SEC] = MAX77686_ALARM1_SEC,
152*4882a593Smuzhiyun [REG_ALARM1_MIN] = MAX77686_ALARM1_MIN,
153*4882a593Smuzhiyun [REG_ALARM1_HOUR] = MAX77686_ALARM1_HOUR,
154*4882a593Smuzhiyun [REG_ALARM1_WEEKDAY] = MAX77686_ALARM1_WEEKDAY,
155*4882a593Smuzhiyun [REG_ALARM1_MONTH] = MAX77686_ALARM1_MONTH,
156*4882a593Smuzhiyun [REG_ALARM1_YEAR] = MAX77686_ALARM1_YEAR,
157*4882a593Smuzhiyun [REG_ALARM1_DATE] = MAX77686_ALARM1_DATE,
158*4882a593Smuzhiyun [REG_ALARM2_SEC] = MAX77686_ALARM2_SEC,
159*4882a593Smuzhiyun [REG_ALARM2_MIN] = MAX77686_ALARM2_MIN,
160*4882a593Smuzhiyun [REG_ALARM2_HOUR] = MAX77686_ALARM2_HOUR,
161*4882a593Smuzhiyun [REG_ALARM2_WEEKDAY] = MAX77686_ALARM2_WEEKDAY,
162*4882a593Smuzhiyun [REG_ALARM2_MONTH] = MAX77686_ALARM2_MONTH,
163*4882a593Smuzhiyun [REG_ALARM2_YEAR] = MAX77686_ALARM2_YEAR,
164*4882a593Smuzhiyun [REG_ALARM2_DATE] = MAX77686_ALARM2_DATE,
165*4882a593Smuzhiyun [REG_RTC_AE1] = REG_RTC_NONE,
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun static const struct regmap_irq max77686_rtc_irqs[] = {
169*4882a593Smuzhiyun /* RTC interrupts */
170*4882a593Smuzhiyun REGMAP_IRQ_REG(0, 0, MAX77686_RTCINT_RTC60S_MSK),
171*4882a593Smuzhiyun REGMAP_IRQ_REG(1, 0, MAX77686_RTCINT_RTCA1_MSK),
172*4882a593Smuzhiyun REGMAP_IRQ_REG(2, 0, MAX77686_RTCINT_RTCA2_MSK),
173*4882a593Smuzhiyun REGMAP_IRQ_REG(3, 0, MAX77686_RTCINT_SMPL_MSK),
174*4882a593Smuzhiyun REGMAP_IRQ_REG(4, 0, MAX77686_RTCINT_RTC1S_MSK),
175*4882a593Smuzhiyun REGMAP_IRQ_REG(5, 0, MAX77686_RTCINT_WTSR_MSK),
176*4882a593Smuzhiyun };
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun static const struct regmap_irq_chip max77686_rtc_irq_chip = {
179*4882a593Smuzhiyun .name = "max77686-rtc",
180*4882a593Smuzhiyun .status_base = MAX77686_RTC_INT,
181*4882a593Smuzhiyun .mask_base = MAX77686_RTC_INTM,
182*4882a593Smuzhiyun .num_regs = 1,
183*4882a593Smuzhiyun .irqs = max77686_rtc_irqs,
184*4882a593Smuzhiyun .num_irqs = ARRAY_SIZE(max77686_rtc_irqs),
185*4882a593Smuzhiyun };
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun static const struct regmap_config max77686_rtc_regmap_config = {
188*4882a593Smuzhiyun .reg_bits = 8,
189*4882a593Smuzhiyun .val_bits = 8,
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun static const struct max77686_rtc_driver_data max77686_drv_data = {
193*4882a593Smuzhiyun .delay = 16000,
194*4882a593Smuzhiyun .mask = 0x7f,
195*4882a593Smuzhiyun .map = max77686_map,
196*4882a593Smuzhiyun .alarm_enable_reg = false,
197*4882a593Smuzhiyun .rtc_irq_from_platform = false,
198*4882a593Smuzhiyun .alarm_pending_status_reg = MAX77686_REG_STATUS2,
199*4882a593Smuzhiyun .rtc_i2c_addr = MAX77686_I2C_ADDR_RTC,
200*4882a593Smuzhiyun .rtc_irq_chip = &max77686_rtc_irq_chip,
201*4882a593Smuzhiyun .regmap_config = &max77686_rtc_regmap_config,
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun static const struct regmap_config max77620_rtc_regmap_config = {
205*4882a593Smuzhiyun .reg_bits = 8,
206*4882a593Smuzhiyun .val_bits = 8,
207*4882a593Smuzhiyun .use_single_write = true,
208*4882a593Smuzhiyun };
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun static const struct max77686_rtc_driver_data max77620_drv_data = {
211*4882a593Smuzhiyun .delay = 16000,
212*4882a593Smuzhiyun .mask = 0x7f,
213*4882a593Smuzhiyun .map = max77686_map,
214*4882a593Smuzhiyun .alarm_enable_reg = false,
215*4882a593Smuzhiyun .rtc_irq_from_platform = true,
216*4882a593Smuzhiyun .alarm_pending_status_reg = MAX77686_INVALID_REG,
217*4882a593Smuzhiyun .rtc_i2c_addr = MAX77620_I2C_ADDR_RTC,
218*4882a593Smuzhiyun .rtc_irq_chip = &max77686_rtc_irq_chip,
219*4882a593Smuzhiyun .regmap_config = &max77620_rtc_regmap_config,
220*4882a593Smuzhiyun };
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun static const unsigned int max77802_map[REG_RTC_END] = {
223*4882a593Smuzhiyun [REG_RTC_CONTROLM] = MAX77802_RTC_CONTROLM,
224*4882a593Smuzhiyun [REG_RTC_CONTROL] = MAX77802_RTC_CONTROL,
225*4882a593Smuzhiyun [REG_RTC_UPDATE0] = MAX77802_RTC_UPDATE0,
226*4882a593Smuzhiyun [REG_WTSR_SMPL_CNTL] = MAX77802_WTSR_SMPL_CNTL,
227*4882a593Smuzhiyun [REG_RTC_SEC] = MAX77802_RTC_SEC,
228*4882a593Smuzhiyun [REG_RTC_MIN] = MAX77802_RTC_MIN,
229*4882a593Smuzhiyun [REG_RTC_HOUR] = MAX77802_RTC_HOUR,
230*4882a593Smuzhiyun [REG_RTC_WEEKDAY] = MAX77802_RTC_WEEKDAY,
231*4882a593Smuzhiyun [REG_RTC_MONTH] = MAX77802_RTC_MONTH,
232*4882a593Smuzhiyun [REG_RTC_YEAR] = MAX77802_RTC_YEAR,
233*4882a593Smuzhiyun [REG_RTC_DATE] = MAX77802_RTC_DATE,
234*4882a593Smuzhiyun [REG_ALARM1_SEC] = MAX77802_ALARM1_SEC,
235*4882a593Smuzhiyun [REG_ALARM1_MIN] = MAX77802_ALARM1_MIN,
236*4882a593Smuzhiyun [REG_ALARM1_HOUR] = MAX77802_ALARM1_HOUR,
237*4882a593Smuzhiyun [REG_ALARM1_WEEKDAY] = MAX77802_ALARM1_WEEKDAY,
238*4882a593Smuzhiyun [REG_ALARM1_MONTH] = MAX77802_ALARM1_MONTH,
239*4882a593Smuzhiyun [REG_ALARM1_YEAR] = MAX77802_ALARM1_YEAR,
240*4882a593Smuzhiyun [REG_ALARM1_DATE] = MAX77802_ALARM1_DATE,
241*4882a593Smuzhiyun [REG_ALARM2_SEC] = MAX77802_ALARM2_SEC,
242*4882a593Smuzhiyun [REG_ALARM2_MIN] = MAX77802_ALARM2_MIN,
243*4882a593Smuzhiyun [REG_ALARM2_HOUR] = MAX77802_ALARM2_HOUR,
244*4882a593Smuzhiyun [REG_ALARM2_WEEKDAY] = MAX77802_ALARM2_WEEKDAY,
245*4882a593Smuzhiyun [REG_ALARM2_MONTH] = MAX77802_ALARM2_MONTH,
246*4882a593Smuzhiyun [REG_ALARM2_YEAR] = MAX77802_ALARM2_YEAR,
247*4882a593Smuzhiyun [REG_ALARM2_DATE] = MAX77802_ALARM2_DATE,
248*4882a593Smuzhiyun [REG_RTC_AE1] = MAX77802_RTC_AE1,
249*4882a593Smuzhiyun };
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun static const struct regmap_irq_chip max77802_rtc_irq_chip = {
252*4882a593Smuzhiyun .name = "max77802-rtc",
253*4882a593Smuzhiyun .status_base = MAX77802_RTC_INT,
254*4882a593Smuzhiyun .mask_base = MAX77802_RTC_INTM,
255*4882a593Smuzhiyun .num_regs = 1,
256*4882a593Smuzhiyun .irqs = max77686_rtc_irqs, /* same masks as 77686 */
257*4882a593Smuzhiyun .num_irqs = ARRAY_SIZE(max77686_rtc_irqs),
258*4882a593Smuzhiyun };
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun static const struct max77686_rtc_driver_data max77802_drv_data = {
261*4882a593Smuzhiyun .delay = 200,
262*4882a593Smuzhiyun .mask = 0xff,
263*4882a593Smuzhiyun .map = max77802_map,
264*4882a593Smuzhiyun .alarm_enable_reg = true,
265*4882a593Smuzhiyun .rtc_irq_from_platform = false,
266*4882a593Smuzhiyun .alarm_pending_status_reg = MAX77686_REG_STATUS2,
267*4882a593Smuzhiyun .rtc_i2c_addr = MAX77686_INVALID_I2C_ADDR,
268*4882a593Smuzhiyun .rtc_irq_chip = &max77802_rtc_irq_chip,
269*4882a593Smuzhiyun };
270*4882a593Smuzhiyun
max77686_rtc_data_to_tm(u8 * data,struct rtc_time * tm,struct max77686_rtc_info * info)271*4882a593Smuzhiyun static void max77686_rtc_data_to_tm(u8 *data, struct rtc_time *tm,
272*4882a593Smuzhiyun struct max77686_rtc_info *info)
273*4882a593Smuzhiyun {
274*4882a593Smuzhiyun u8 mask = info->drv_data->mask;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun tm->tm_sec = data[RTC_SEC] & mask;
277*4882a593Smuzhiyun tm->tm_min = data[RTC_MIN] & mask;
278*4882a593Smuzhiyun if (info->rtc_24hr_mode) {
279*4882a593Smuzhiyun tm->tm_hour = data[RTC_HOUR] & 0x1f;
280*4882a593Smuzhiyun } else {
281*4882a593Smuzhiyun tm->tm_hour = data[RTC_HOUR] & 0x0f;
282*4882a593Smuzhiyun if (data[RTC_HOUR] & HOUR_PM_MASK)
283*4882a593Smuzhiyun tm->tm_hour += 12;
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun /* Only a single bit is set in data[], so fls() would be equivalent */
287*4882a593Smuzhiyun tm->tm_wday = ffs(data[RTC_WEEKDAY] & mask) - 1;
288*4882a593Smuzhiyun tm->tm_mday = data[RTC_DATE] & 0x1f;
289*4882a593Smuzhiyun tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1;
290*4882a593Smuzhiyun tm->tm_year = data[RTC_YEAR] & mask;
291*4882a593Smuzhiyun tm->tm_yday = 0;
292*4882a593Smuzhiyun tm->tm_isdst = 0;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun /*
295*4882a593Smuzhiyun * MAX77686 uses 1 bit from sec/min/hour/etc RTC registers and the
296*4882a593Smuzhiyun * year values are just 0..99 so add 100 to support up to 2099.
297*4882a593Smuzhiyun */
298*4882a593Smuzhiyun if (!info->drv_data->alarm_enable_reg)
299*4882a593Smuzhiyun tm->tm_year += 100;
300*4882a593Smuzhiyun }
301*4882a593Smuzhiyun
max77686_rtc_tm_to_data(struct rtc_time * tm,u8 * data,struct max77686_rtc_info * info)302*4882a593Smuzhiyun static int max77686_rtc_tm_to_data(struct rtc_time *tm, u8 *data,
303*4882a593Smuzhiyun struct max77686_rtc_info *info)
304*4882a593Smuzhiyun {
305*4882a593Smuzhiyun data[RTC_SEC] = tm->tm_sec;
306*4882a593Smuzhiyun data[RTC_MIN] = tm->tm_min;
307*4882a593Smuzhiyun data[RTC_HOUR] = tm->tm_hour;
308*4882a593Smuzhiyun data[RTC_WEEKDAY] = 1 << tm->tm_wday;
309*4882a593Smuzhiyun data[RTC_DATE] = tm->tm_mday;
310*4882a593Smuzhiyun data[RTC_MONTH] = tm->tm_mon + 1;
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun if (info->drv_data->alarm_enable_reg) {
313*4882a593Smuzhiyun data[RTC_YEAR] = tm->tm_year;
314*4882a593Smuzhiyun return 0;
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun data[RTC_YEAR] = tm->tm_year > 100 ? (tm->tm_year - 100) : 0;
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun if (tm->tm_year < 100) {
320*4882a593Smuzhiyun dev_err(info->dev, "RTC cannot handle the year %d.\n",
321*4882a593Smuzhiyun 1900 + tm->tm_year);
322*4882a593Smuzhiyun return -EINVAL;
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun return 0;
326*4882a593Smuzhiyun }
327*4882a593Smuzhiyun
max77686_rtc_update(struct max77686_rtc_info * info,enum MAX77686_RTC_OP op)328*4882a593Smuzhiyun static int max77686_rtc_update(struct max77686_rtc_info *info,
329*4882a593Smuzhiyun enum MAX77686_RTC_OP op)
330*4882a593Smuzhiyun {
331*4882a593Smuzhiyun int ret;
332*4882a593Smuzhiyun unsigned int data;
333*4882a593Smuzhiyun unsigned long delay = info->drv_data->delay;
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun if (op == MAX77686_RTC_WRITE)
336*4882a593Smuzhiyun data = 1 << RTC_UDR_SHIFT;
337*4882a593Smuzhiyun else
338*4882a593Smuzhiyun data = 1 << RTC_RBUDR_SHIFT;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun ret = regmap_update_bits(info->rtc_regmap,
341*4882a593Smuzhiyun info->drv_data->map[REG_RTC_UPDATE0],
342*4882a593Smuzhiyun data, data);
343*4882a593Smuzhiyun if (ret < 0)
344*4882a593Smuzhiyun dev_err(info->dev, "Fail to write update reg(ret=%d, data=0x%x)\n",
345*4882a593Smuzhiyun ret, data);
346*4882a593Smuzhiyun else {
347*4882a593Smuzhiyun /* Minimum delay required before RTC update. */
348*4882a593Smuzhiyun usleep_range(delay, delay * 2);
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun return ret;
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun
max77686_rtc_read_time(struct device * dev,struct rtc_time * tm)354*4882a593Smuzhiyun static int max77686_rtc_read_time(struct device *dev, struct rtc_time *tm)
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun struct max77686_rtc_info *info = dev_get_drvdata(dev);
357*4882a593Smuzhiyun u8 data[RTC_NR_TIME];
358*4882a593Smuzhiyun int ret;
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun mutex_lock(&info->lock);
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun ret = max77686_rtc_update(info, MAX77686_RTC_READ);
363*4882a593Smuzhiyun if (ret < 0)
364*4882a593Smuzhiyun goto out;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun ret = regmap_bulk_read(info->rtc_regmap,
367*4882a593Smuzhiyun info->drv_data->map[REG_RTC_SEC],
368*4882a593Smuzhiyun data, ARRAY_SIZE(data));
369*4882a593Smuzhiyun if (ret < 0) {
370*4882a593Smuzhiyun dev_err(info->dev, "Fail to read time reg(%d)\n", ret);
371*4882a593Smuzhiyun goto out;
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun max77686_rtc_data_to_tm(data, tm, info);
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun out:
377*4882a593Smuzhiyun mutex_unlock(&info->lock);
378*4882a593Smuzhiyun return ret;
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun
max77686_rtc_set_time(struct device * dev,struct rtc_time * tm)381*4882a593Smuzhiyun static int max77686_rtc_set_time(struct device *dev, struct rtc_time *tm)
382*4882a593Smuzhiyun {
383*4882a593Smuzhiyun struct max77686_rtc_info *info = dev_get_drvdata(dev);
384*4882a593Smuzhiyun u8 data[RTC_NR_TIME];
385*4882a593Smuzhiyun int ret;
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun ret = max77686_rtc_tm_to_data(tm, data, info);
388*4882a593Smuzhiyun if (ret < 0)
389*4882a593Smuzhiyun return ret;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun mutex_lock(&info->lock);
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun ret = regmap_bulk_write(info->rtc_regmap,
394*4882a593Smuzhiyun info->drv_data->map[REG_RTC_SEC],
395*4882a593Smuzhiyun data, ARRAY_SIZE(data));
396*4882a593Smuzhiyun if (ret < 0) {
397*4882a593Smuzhiyun dev_err(info->dev, "Fail to write time reg(%d)\n", ret);
398*4882a593Smuzhiyun goto out;
399*4882a593Smuzhiyun }
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun out:
404*4882a593Smuzhiyun mutex_unlock(&info->lock);
405*4882a593Smuzhiyun return ret;
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun
max77686_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)408*4882a593Smuzhiyun static int max77686_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
409*4882a593Smuzhiyun {
410*4882a593Smuzhiyun struct max77686_rtc_info *info = dev_get_drvdata(dev);
411*4882a593Smuzhiyun u8 data[RTC_NR_TIME];
412*4882a593Smuzhiyun unsigned int val;
413*4882a593Smuzhiyun const unsigned int *map = info->drv_data->map;
414*4882a593Smuzhiyun int i, ret;
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun mutex_lock(&info->lock);
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun ret = max77686_rtc_update(info, MAX77686_RTC_READ);
419*4882a593Smuzhiyun if (ret < 0)
420*4882a593Smuzhiyun goto out;
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
423*4882a593Smuzhiyun data, ARRAY_SIZE(data));
424*4882a593Smuzhiyun if (ret < 0) {
425*4882a593Smuzhiyun dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
426*4882a593Smuzhiyun goto out;
427*4882a593Smuzhiyun }
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun max77686_rtc_data_to_tm(data, &alrm->time, info);
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun alrm->enabled = 0;
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun if (info->drv_data->alarm_enable_reg) {
434*4882a593Smuzhiyun if (map[REG_RTC_AE1] == REG_RTC_NONE) {
435*4882a593Smuzhiyun ret = -EINVAL;
436*4882a593Smuzhiyun dev_err(info->dev,
437*4882a593Smuzhiyun "alarm enable register not set(%d)\n", ret);
438*4882a593Smuzhiyun goto out;
439*4882a593Smuzhiyun }
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun ret = regmap_read(info->rtc_regmap, map[REG_RTC_AE1], &val);
442*4882a593Smuzhiyun if (ret < 0) {
443*4882a593Smuzhiyun dev_err(info->dev,
444*4882a593Smuzhiyun "fail to read alarm enable(%d)\n", ret);
445*4882a593Smuzhiyun goto out;
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun if (val)
449*4882a593Smuzhiyun alrm->enabled = 1;
450*4882a593Smuzhiyun } else {
451*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(data); i++) {
452*4882a593Smuzhiyun if (data[i] & ALARM_ENABLE_MASK) {
453*4882a593Smuzhiyun alrm->enabled = 1;
454*4882a593Smuzhiyun break;
455*4882a593Smuzhiyun }
456*4882a593Smuzhiyun }
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun alrm->pending = 0;
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun if (info->drv_data->alarm_pending_status_reg == MAX77686_INVALID_REG)
462*4882a593Smuzhiyun goto out;
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun ret = regmap_read(info->regmap,
465*4882a593Smuzhiyun info->drv_data->alarm_pending_status_reg, &val);
466*4882a593Smuzhiyun if (ret < 0) {
467*4882a593Smuzhiyun dev_err(info->dev,
468*4882a593Smuzhiyun "Fail to read alarm pending status reg(%d)\n", ret);
469*4882a593Smuzhiyun goto out;
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun if (val & (1 << 4)) /* RTCA1 */
473*4882a593Smuzhiyun alrm->pending = 1;
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun out:
476*4882a593Smuzhiyun mutex_unlock(&info->lock);
477*4882a593Smuzhiyun return ret;
478*4882a593Smuzhiyun }
479*4882a593Smuzhiyun
max77686_rtc_stop_alarm(struct max77686_rtc_info * info)480*4882a593Smuzhiyun static int max77686_rtc_stop_alarm(struct max77686_rtc_info *info)
481*4882a593Smuzhiyun {
482*4882a593Smuzhiyun u8 data[RTC_NR_TIME];
483*4882a593Smuzhiyun int ret, i;
484*4882a593Smuzhiyun struct rtc_time tm;
485*4882a593Smuzhiyun const unsigned int *map = info->drv_data->map;
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun if (!mutex_is_locked(&info->lock))
488*4882a593Smuzhiyun dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun ret = max77686_rtc_update(info, MAX77686_RTC_READ);
491*4882a593Smuzhiyun if (ret < 0)
492*4882a593Smuzhiyun goto out;
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun if (info->drv_data->alarm_enable_reg) {
495*4882a593Smuzhiyun if (map[REG_RTC_AE1] == REG_RTC_NONE) {
496*4882a593Smuzhiyun ret = -EINVAL;
497*4882a593Smuzhiyun dev_err(info->dev,
498*4882a593Smuzhiyun "alarm enable register not set(%d)\n", ret);
499*4882a593Smuzhiyun goto out;
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun ret = regmap_write(info->rtc_regmap, map[REG_RTC_AE1], 0);
503*4882a593Smuzhiyun } else {
504*4882a593Smuzhiyun ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
505*4882a593Smuzhiyun data, ARRAY_SIZE(data));
506*4882a593Smuzhiyun if (ret < 0) {
507*4882a593Smuzhiyun dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
508*4882a593Smuzhiyun goto out;
509*4882a593Smuzhiyun }
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun max77686_rtc_data_to_tm(data, &tm, info);
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(data); i++)
514*4882a593Smuzhiyun data[i] &= ~ALARM_ENABLE_MASK;
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun ret = regmap_bulk_write(info->rtc_regmap, map[REG_ALARM1_SEC],
517*4882a593Smuzhiyun data, ARRAY_SIZE(data));
518*4882a593Smuzhiyun }
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun if (ret < 0) {
521*4882a593Smuzhiyun dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
522*4882a593Smuzhiyun goto out;
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
526*4882a593Smuzhiyun out:
527*4882a593Smuzhiyun return ret;
528*4882a593Smuzhiyun }
529*4882a593Smuzhiyun
max77686_rtc_start_alarm(struct max77686_rtc_info * info)530*4882a593Smuzhiyun static int max77686_rtc_start_alarm(struct max77686_rtc_info *info)
531*4882a593Smuzhiyun {
532*4882a593Smuzhiyun u8 data[RTC_NR_TIME];
533*4882a593Smuzhiyun int ret;
534*4882a593Smuzhiyun struct rtc_time tm;
535*4882a593Smuzhiyun const unsigned int *map = info->drv_data->map;
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun if (!mutex_is_locked(&info->lock))
538*4882a593Smuzhiyun dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun ret = max77686_rtc_update(info, MAX77686_RTC_READ);
541*4882a593Smuzhiyun if (ret < 0)
542*4882a593Smuzhiyun goto out;
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun if (info->drv_data->alarm_enable_reg) {
545*4882a593Smuzhiyun ret = regmap_write(info->rtc_regmap, map[REG_RTC_AE1],
546*4882a593Smuzhiyun MAX77802_ALARM_ENABLE_VALUE);
547*4882a593Smuzhiyun } else {
548*4882a593Smuzhiyun ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
549*4882a593Smuzhiyun data, ARRAY_SIZE(data));
550*4882a593Smuzhiyun if (ret < 0) {
551*4882a593Smuzhiyun dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
552*4882a593Smuzhiyun goto out;
553*4882a593Smuzhiyun }
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun max77686_rtc_data_to_tm(data, &tm, info);
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun data[RTC_SEC] |= (1 << ALARM_ENABLE_SHIFT);
558*4882a593Smuzhiyun data[RTC_MIN] |= (1 << ALARM_ENABLE_SHIFT);
559*4882a593Smuzhiyun data[RTC_HOUR] |= (1 << ALARM_ENABLE_SHIFT);
560*4882a593Smuzhiyun data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK;
561*4882a593Smuzhiyun if (data[RTC_MONTH] & 0xf)
562*4882a593Smuzhiyun data[RTC_MONTH] |= (1 << ALARM_ENABLE_SHIFT);
563*4882a593Smuzhiyun if (data[RTC_YEAR] & info->drv_data->mask)
564*4882a593Smuzhiyun data[RTC_YEAR] |= (1 << ALARM_ENABLE_SHIFT);
565*4882a593Smuzhiyun if (data[RTC_DATE] & 0x1f)
566*4882a593Smuzhiyun data[RTC_DATE] |= (1 << ALARM_ENABLE_SHIFT);
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun ret = regmap_bulk_write(info->rtc_regmap, map[REG_ALARM1_SEC],
569*4882a593Smuzhiyun data, ARRAY_SIZE(data));
570*4882a593Smuzhiyun }
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun if (ret < 0) {
573*4882a593Smuzhiyun dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
574*4882a593Smuzhiyun goto out;
575*4882a593Smuzhiyun }
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
578*4882a593Smuzhiyun out:
579*4882a593Smuzhiyun return ret;
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun
max77686_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)582*4882a593Smuzhiyun static int max77686_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
583*4882a593Smuzhiyun {
584*4882a593Smuzhiyun struct max77686_rtc_info *info = dev_get_drvdata(dev);
585*4882a593Smuzhiyun u8 data[RTC_NR_TIME];
586*4882a593Smuzhiyun int ret;
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun ret = max77686_rtc_tm_to_data(&alrm->time, data, info);
589*4882a593Smuzhiyun if (ret < 0)
590*4882a593Smuzhiyun return ret;
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun mutex_lock(&info->lock);
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun ret = max77686_rtc_stop_alarm(info);
595*4882a593Smuzhiyun if (ret < 0)
596*4882a593Smuzhiyun goto out;
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun ret = regmap_bulk_write(info->rtc_regmap,
599*4882a593Smuzhiyun info->drv_data->map[REG_ALARM1_SEC],
600*4882a593Smuzhiyun data, ARRAY_SIZE(data));
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun if (ret < 0) {
603*4882a593Smuzhiyun dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
604*4882a593Smuzhiyun goto out;
605*4882a593Smuzhiyun }
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
608*4882a593Smuzhiyun if (ret < 0)
609*4882a593Smuzhiyun goto out;
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun if (alrm->enabled)
612*4882a593Smuzhiyun ret = max77686_rtc_start_alarm(info);
613*4882a593Smuzhiyun out:
614*4882a593Smuzhiyun mutex_unlock(&info->lock);
615*4882a593Smuzhiyun return ret;
616*4882a593Smuzhiyun }
617*4882a593Smuzhiyun
max77686_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)618*4882a593Smuzhiyun static int max77686_rtc_alarm_irq_enable(struct device *dev,
619*4882a593Smuzhiyun unsigned int enabled)
620*4882a593Smuzhiyun {
621*4882a593Smuzhiyun struct max77686_rtc_info *info = dev_get_drvdata(dev);
622*4882a593Smuzhiyun int ret;
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun mutex_lock(&info->lock);
625*4882a593Smuzhiyun if (enabled)
626*4882a593Smuzhiyun ret = max77686_rtc_start_alarm(info);
627*4882a593Smuzhiyun else
628*4882a593Smuzhiyun ret = max77686_rtc_stop_alarm(info);
629*4882a593Smuzhiyun mutex_unlock(&info->lock);
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun return ret;
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun
max77686_rtc_alarm_irq(int irq,void * data)634*4882a593Smuzhiyun static irqreturn_t max77686_rtc_alarm_irq(int irq, void *data)
635*4882a593Smuzhiyun {
636*4882a593Smuzhiyun struct max77686_rtc_info *info = data;
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun dev_dbg(info->dev, "RTC alarm IRQ: %d\n", irq);
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF);
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun return IRQ_HANDLED;
643*4882a593Smuzhiyun }
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun static const struct rtc_class_ops max77686_rtc_ops = {
646*4882a593Smuzhiyun .read_time = max77686_rtc_read_time,
647*4882a593Smuzhiyun .set_time = max77686_rtc_set_time,
648*4882a593Smuzhiyun .read_alarm = max77686_rtc_read_alarm,
649*4882a593Smuzhiyun .set_alarm = max77686_rtc_set_alarm,
650*4882a593Smuzhiyun .alarm_irq_enable = max77686_rtc_alarm_irq_enable,
651*4882a593Smuzhiyun };
652*4882a593Smuzhiyun
max77686_rtc_init_reg(struct max77686_rtc_info * info)653*4882a593Smuzhiyun static int max77686_rtc_init_reg(struct max77686_rtc_info *info)
654*4882a593Smuzhiyun {
655*4882a593Smuzhiyun u8 data[2];
656*4882a593Smuzhiyun int ret;
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun /* Set RTC control register : Binary mode, 24hour mdoe */
659*4882a593Smuzhiyun data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
660*4882a593Smuzhiyun data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun info->rtc_24hr_mode = 1;
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun ret = regmap_bulk_write(info->rtc_regmap,
665*4882a593Smuzhiyun info->drv_data->map[REG_RTC_CONTROLM],
666*4882a593Smuzhiyun data, ARRAY_SIZE(data));
667*4882a593Smuzhiyun if (ret < 0) {
668*4882a593Smuzhiyun dev_err(info->dev, "Fail to write controlm reg(%d)\n", ret);
669*4882a593Smuzhiyun return ret;
670*4882a593Smuzhiyun }
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
673*4882a593Smuzhiyun return ret;
674*4882a593Smuzhiyun }
675*4882a593Smuzhiyun
max77686_init_rtc_regmap(struct max77686_rtc_info * info)676*4882a593Smuzhiyun static int max77686_init_rtc_regmap(struct max77686_rtc_info *info)
677*4882a593Smuzhiyun {
678*4882a593Smuzhiyun struct device *parent = info->dev->parent;
679*4882a593Smuzhiyun struct i2c_client *parent_i2c = to_i2c_client(parent);
680*4882a593Smuzhiyun int ret;
681*4882a593Smuzhiyun
682*4882a593Smuzhiyun if (info->drv_data->rtc_irq_from_platform) {
683*4882a593Smuzhiyun struct platform_device *pdev = to_platform_device(info->dev);
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun info->rtc_irq = platform_get_irq(pdev, 0);
686*4882a593Smuzhiyun if (info->rtc_irq < 0)
687*4882a593Smuzhiyun return info->rtc_irq;
688*4882a593Smuzhiyun } else {
689*4882a593Smuzhiyun info->rtc_irq = parent_i2c->irq;
690*4882a593Smuzhiyun }
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun info->regmap = dev_get_regmap(parent, NULL);
693*4882a593Smuzhiyun if (!info->regmap) {
694*4882a593Smuzhiyun dev_err(info->dev, "Failed to get rtc regmap\n");
695*4882a593Smuzhiyun return -ENODEV;
696*4882a593Smuzhiyun }
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun if (info->drv_data->rtc_i2c_addr == MAX77686_INVALID_I2C_ADDR) {
699*4882a593Smuzhiyun info->rtc_regmap = info->regmap;
700*4882a593Smuzhiyun goto add_rtc_irq;
701*4882a593Smuzhiyun }
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun info->rtc = devm_i2c_new_dummy_device(info->dev, parent_i2c->adapter,
704*4882a593Smuzhiyun info->drv_data->rtc_i2c_addr);
705*4882a593Smuzhiyun if (IS_ERR(info->rtc)) {
706*4882a593Smuzhiyun dev_err(info->dev, "Failed to allocate I2C device for RTC\n");
707*4882a593Smuzhiyun return PTR_ERR(info->rtc);
708*4882a593Smuzhiyun }
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun info->rtc_regmap = devm_regmap_init_i2c(info->rtc,
711*4882a593Smuzhiyun info->drv_data->regmap_config);
712*4882a593Smuzhiyun if (IS_ERR(info->rtc_regmap)) {
713*4882a593Smuzhiyun ret = PTR_ERR(info->rtc_regmap);
714*4882a593Smuzhiyun dev_err(info->dev, "Failed to allocate RTC regmap: %d\n", ret);
715*4882a593Smuzhiyun return ret;
716*4882a593Smuzhiyun }
717*4882a593Smuzhiyun
718*4882a593Smuzhiyun add_rtc_irq:
719*4882a593Smuzhiyun ret = regmap_add_irq_chip(info->rtc_regmap, info->rtc_irq,
720*4882a593Smuzhiyun IRQF_ONESHOT | IRQF_SHARED,
721*4882a593Smuzhiyun 0, info->drv_data->rtc_irq_chip,
722*4882a593Smuzhiyun &info->rtc_irq_data);
723*4882a593Smuzhiyun if (ret < 0) {
724*4882a593Smuzhiyun dev_err(info->dev, "Failed to add RTC irq chip: %d\n", ret);
725*4882a593Smuzhiyun return ret;
726*4882a593Smuzhiyun }
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun return 0;
729*4882a593Smuzhiyun }
730*4882a593Smuzhiyun
max77686_rtc_probe(struct platform_device * pdev)731*4882a593Smuzhiyun static int max77686_rtc_probe(struct platform_device *pdev)
732*4882a593Smuzhiyun {
733*4882a593Smuzhiyun struct max77686_rtc_info *info;
734*4882a593Smuzhiyun const struct platform_device_id *id = platform_get_device_id(pdev);
735*4882a593Smuzhiyun int ret;
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun info = devm_kzalloc(&pdev->dev, sizeof(struct max77686_rtc_info),
738*4882a593Smuzhiyun GFP_KERNEL);
739*4882a593Smuzhiyun if (!info)
740*4882a593Smuzhiyun return -ENOMEM;
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun mutex_init(&info->lock);
743*4882a593Smuzhiyun info->dev = &pdev->dev;
744*4882a593Smuzhiyun info->drv_data = (const struct max77686_rtc_driver_data *)
745*4882a593Smuzhiyun id->driver_data;
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun ret = max77686_init_rtc_regmap(info);
748*4882a593Smuzhiyun if (ret < 0)
749*4882a593Smuzhiyun return ret;
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun platform_set_drvdata(pdev, info);
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun ret = max77686_rtc_init_reg(info);
754*4882a593Smuzhiyun if (ret < 0) {
755*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to initialize RTC reg:%d\n", ret);
756*4882a593Smuzhiyun goto err_rtc;
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun device_init_wakeup(&pdev->dev, 1);
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun info->rtc_dev = devm_rtc_device_register(&pdev->dev, id->name,
762*4882a593Smuzhiyun &max77686_rtc_ops, THIS_MODULE);
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun if (IS_ERR(info->rtc_dev)) {
765*4882a593Smuzhiyun ret = PTR_ERR(info->rtc_dev);
766*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
767*4882a593Smuzhiyun if (ret == 0)
768*4882a593Smuzhiyun ret = -EINVAL;
769*4882a593Smuzhiyun goto err_rtc;
770*4882a593Smuzhiyun }
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun info->virq = regmap_irq_get_virq(info->rtc_irq_data,
773*4882a593Smuzhiyun MAX77686_RTCIRQ_RTCA1);
774*4882a593Smuzhiyun if (info->virq <= 0) {
775*4882a593Smuzhiyun ret = -ENXIO;
776*4882a593Smuzhiyun goto err_rtc;
777*4882a593Smuzhiyun }
778*4882a593Smuzhiyun
779*4882a593Smuzhiyun ret = request_threaded_irq(info->virq, NULL, max77686_rtc_alarm_irq, 0,
780*4882a593Smuzhiyun "rtc-alarm1", info);
781*4882a593Smuzhiyun if (ret < 0) {
782*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
783*4882a593Smuzhiyun info->virq, ret);
784*4882a593Smuzhiyun goto err_rtc;
785*4882a593Smuzhiyun }
786*4882a593Smuzhiyun
787*4882a593Smuzhiyun return 0;
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun err_rtc:
790*4882a593Smuzhiyun regmap_del_irq_chip(info->rtc_irq, info->rtc_irq_data);
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun return ret;
793*4882a593Smuzhiyun }
794*4882a593Smuzhiyun
max77686_rtc_remove(struct platform_device * pdev)795*4882a593Smuzhiyun static int max77686_rtc_remove(struct platform_device *pdev)
796*4882a593Smuzhiyun {
797*4882a593Smuzhiyun struct max77686_rtc_info *info = platform_get_drvdata(pdev);
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun free_irq(info->virq, info);
800*4882a593Smuzhiyun regmap_del_irq_chip(info->rtc_irq, info->rtc_irq_data);
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun return 0;
803*4882a593Smuzhiyun }
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
max77686_rtc_suspend(struct device * dev)806*4882a593Smuzhiyun static int max77686_rtc_suspend(struct device *dev)
807*4882a593Smuzhiyun {
808*4882a593Smuzhiyun struct max77686_rtc_info *info = dev_get_drvdata(dev);
809*4882a593Smuzhiyun int ret = 0;
810*4882a593Smuzhiyun
811*4882a593Smuzhiyun if (device_may_wakeup(dev)) {
812*4882a593Smuzhiyun struct max77686_rtc_info *info = dev_get_drvdata(dev);
813*4882a593Smuzhiyun
814*4882a593Smuzhiyun ret = enable_irq_wake(info->virq);
815*4882a593Smuzhiyun }
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun /*
818*4882a593Smuzhiyun * If the main IRQ (not virtual) is the parent IRQ, then it must be
819*4882a593Smuzhiyun * disabled during suspend because if it happens while suspended it
820*4882a593Smuzhiyun * will be handled before resuming I2C.
821*4882a593Smuzhiyun *
822*4882a593Smuzhiyun * Since Main IRQ is shared, all its users should disable it to be sure
823*4882a593Smuzhiyun * it won't fire while one of them is still suspended.
824*4882a593Smuzhiyun */
825*4882a593Smuzhiyun if (!info->drv_data->rtc_irq_from_platform)
826*4882a593Smuzhiyun disable_irq(info->rtc_irq);
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun return ret;
829*4882a593Smuzhiyun }
830*4882a593Smuzhiyun
max77686_rtc_resume(struct device * dev)831*4882a593Smuzhiyun static int max77686_rtc_resume(struct device *dev)
832*4882a593Smuzhiyun {
833*4882a593Smuzhiyun struct max77686_rtc_info *info = dev_get_drvdata(dev);
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun if (!info->drv_data->rtc_irq_from_platform)
836*4882a593Smuzhiyun enable_irq(info->rtc_irq);
837*4882a593Smuzhiyun
838*4882a593Smuzhiyun if (device_may_wakeup(dev)) {
839*4882a593Smuzhiyun struct max77686_rtc_info *info = dev_get_drvdata(dev);
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun return disable_irq_wake(info->virq);
842*4882a593Smuzhiyun }
843*4882a593Smuzhiyun
844*4882a593Smuzhiyun return 0;
845*4882a593Smuzhiyun }
846*4882a593Smuzhiyun #endif
847*4882a593Smuzhiyun
848*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(max77686_rtc_pm_ops,
849*4882a593Smuzhiyun max77686_rtc_suspend, max77686_rtc_resume);
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun static const struct platform_device_id rtc_id[] = {
852*4882a593Smuzhiyun { "max77686-rtc", .driver_data = (kernel_ulong_t)&max77686_drv_data, },
853*4882a593Smuzhiyun { "max77802-rtc", .driver_data = (kernel_ulong_t)&max77802_drv_data, },
854*4882a593Smuzhiyun { "max77620-rtc", .driver_data = (kernel_ulong_t)&max77620_drv_data, },
855*4882a593Smuzhiyun {},
856*4882a593Smuzhiyun };
857*4882a593Smuzhiyun MODULE_DEVICE_TABLE(platform, rtc_id);
858*4882a593Smuzhiyun
859*4882a593Smuzhiyun static struct platform_driver max77686_rtc_driver = {
860*4882a593Smuzhiyun .driver = {
861*4882a593Smuzhiyun .name = "max77686-rtc",
862*4882a593Smuzhiyun .pm = &max77686_rtc_pm_ops,
863*4882a593Smuzhiyun },
864*4882a593Smuzhiyun .probe = max77686_rtc_probe,
865*4882a593Smuzhiyun .remove = max77686_rtc_remove,
866*4882a593Smuzhiyun .id_table = rtc_id,
867*4882a593Smuzhiyun };
868*4882a593Smuzhiyun
869*4882a593Smuzhiyun module_platform_driver(max77686_rtc_driver);
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun MODULE_DESCRIPTION("Maxim MAX77686 RTC driver");
872*4882a593Smuzhiyun MODULE_AUTHOR("Chiwoong Byun <woong.byun@samsung.com>");
873*4882a593Smuzhiyun MODULE_LICENSE("GPL");
874