1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * ST M48T86 / Dallas DS12887 RTC driver
4*4882a593Smuzhiyun * Copyright (c) 2006 Tower Technologies
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Author: Alessandro Zummo <a.zummo@towertech.it>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This drivers only supports the clock running in BCD and 24H mode.
9*4882a593Smuzhiyun * If it will be ever adapted to binary and 12H mode, care must be taken
10*4882a593Smuzhiyun * to not introduce bugs.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/rtc.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/bcd.h>
17*4882a593Smuzhiyun #include <linux/io.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define M48T86_SEC 0x00
20*4882a593Smuzhiyun #define M48T86_SECALRM 0x01
21*4882a593Smuzhiyun #define M48T86_MIN 0x02
22*4882a593Smuzhiyun #define M48T86_MINALRM 0x03
23*4882a593Smuzhiyun #define M48T86_HOUR 0x04
24*4882a593Smuzhiyun #define M48T86_HOURALRM 0x05
25*4882a593Smuzhiyun #define M48T86_DOW 0x06 /* 1 = sunday */
26*4882a593Smuzhiyun #define M48T86_DOM 0x07
27*4882a593Smuzhiyun #define M48T86_MONTH 0x08 /* 1 - 12 */
28*4882a593Smuzhiyun #define M48T86_YEAR 0x09 /* 0 - 99 */
29*4882a593Smuzhiyun #define M48T86_A 0x0a
30*4882a593Smuzhiyun #define M48T86_B 0x0b
31*4882a593Smuzhiyun #define M48T86_B_SET BIT(7)
32*4882a593Smuzhiyun #define M48T86_B_DM BIT(2)
33*4882a593Smuzhiyun #define M48T86_B_H24 BIT(1)
34*4882a593Smuzhiyun #define M48T86_C 0x0c
35*4882a593Smuzhiyun #define M48T86_D 0x0d
36*4882a593Smuzhiyun #define M48T86_D_VRT BIT(7)
37*4882a593Smuzhiyun #define M48T86_NVRAM(x) (0x0e + (x))
38*4882a593Smuzhiyun #define M48T86_NVRAM_LEN 114
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun struct m48t86_rtc_info {
41*4882a593Smuzhiyun void __iomem *index_reg;
42*4882a593Smuzhiyun void __iomem *data_reg;
43*4882a593Smuzhiyun struct rtc_device *rtc;
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
m48t86_readb(struct device * dev,unsigned long addr)46*4882a593Smuzhiyun static unsigned char m48t86_readb(struct device *dev, unsigned long addr)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun struct m48t86_rtc_info *info = dev_get_drvdata(dev);
49*4882a593Smuzhiyun unsigned char value;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun writeb(addr, info->index_reg);
52*4882a593Smuzhiyun value = readb(info->data_reg);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun return value;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
m48t86_writeb(struct device * dev,unsigned char value,unsigned long addr)57*4882a593Smuzhiyun static void m48t86_writeb(struct device *dev,
58*4882a593Smuzhiyun unsigned char value, unsigned long addr)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun struct m48t86_rtc_info *info = dev_get_drvdata(dev);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun writeb(addr, info->index_reg);
63*4882a593Smuzhiyun writeb(value, info->data_reg);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
m48t86_rtc_read_time(struct device * dev,struct rtc_time * tm)66*4882a593Smuzhiyun static int m48t86_rtc_read_time(struct device *dev, struct rtc_time *tm)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun unsigned char reg;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun reg = m48t86_readb(dev, M48T86_B);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun if (reg & M48T86_B_DM) {
73*4882a593Smuzhiyun /* data (binary) mode */
74*4882a593Smuzhiyun tm->tm_sec = m48t86_readb(dev, M48T86_SEC);
75*4882a593Smuzhiyun tm->tm_min = m48t86_readb(dev, M48T86_MIN);
76*4882a593Smuzhiyun tm->tm_hour = m48t86_readb(dev, M48T86_HOUR) & 0x3f;
77*4882a593Smuzhiyun tm->tm_mday = m48t86_readb(dev, M48T86_DOM);
78*4882a593Smuzhiyun /* tm_mon is 0-11 */
79*4882a593Smuzhiyun tm->tm_mon = m48t86_readb(dev, M48T86_MONTH) - 1;
80*4882a593Smuzhiyun tm->tm_year = m48t86_readb(dev, M48T86_YEAR) + 100;
81*4882a593Smuzhiyun tm->tm_wday = m48t86_readb(dev, M48T86_DOW);
82*4882a593Smuzhiyun } else {
83*4882a593Smuzhiyun /* bcd mode */
84*4882a593Smuzhiyun tm->tm_sec = bcd2bin(m48t86_readb(dev, M48T86_SEC));
85*4882a593Smuzhiyun tm->tm_min = bcd2bin(m48t86_readb(dev, M48T86_MIN));
86*4882a593Smuzhiyun tm->tm_hour = bcd2bin(m48t86_readb(dev, M48T86_HOUR) &
87*4882a593Smuzhiyun 0x3f);
88*4882a593Smuzhiyun tm->tm_mday = bcd2bin(m48t86_readb(dev, M48T86_DOM));
89*4882a593Smuzhiyun /* tm_mon is 0-11 */
90*4882a593Smuzhiyun tm->tm_mon = bcd2bin(m48t86_readb(dev, M48T86_MONTH)) - 1;
91*4882a593Smuzhiyun tm->tm_year = bcd2bin(m48t86_readb(dev, M48T86_YEAR)) + 100;
92*4882a593Smuzhiyun tm->tm_wday = bcd2bin(m48t86_readb(dev, M48T86_DOW));
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* correct the hour if the clock is in 12h mode */
96*4882a593Smuzhiyun if (!(reg & M48T86_B_H24))
97*4882a593Smuzhiyun if (m48t86_readb(dev, M48T86_HOUR) & 0x80)
98*4882a593Smuzhiyun tm->tm_hour += 12;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun return 0;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
m48t86_rtc_set_time(struct device * dev,struct rtc_time * tm)103*4882a593Smuzhiyun static int m48t86_rtc_set_time(struct device *dev, struct rtc_time *tm)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun unsigned char reg;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun reg = m48t86_readb(dev, M48T86_B);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* update flag and 24h mode */
110*4882a593Smuzhiyun reg |= M48T86_B_SET | M48T86_B_H24;
111*4882a593Smuzhiyun m48t86_writeb(dev, reg, M48T86_B);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun if (reg & M48T86_B_DM) {
114*4882a593Smuzhiyun /* data (binary) mode */
115*4882a593Smuzhiyun m48t86_writeb(dev, tm->tm_sec, M48T86_SEC);
116*4882a593Smuzhiyun m48t86_writeb(dev, tm->tm_min, M48T86_MIN);
117*4882a593Smuzhiyun m48t86_writeb(dev, tm->tm_hour, M48T86_HOUR);
118*4882a593Smuzhiyun m48t86_writeb(dev, tm->tm_mday, M48T86_DOM);
119*4882a593Smuzhiyun m48t86_writeb(dev, tm->tm_mon + 1, M48T86_MONTH);
120*4882a593Smuzhiyun m48t86_writeb(dev, tm->tm_year % 100, M48T86_YEAR);
121*4882a593Smuzhiyun m48t86_writeb(dev, tm->tm_wday, M48T86_DOW);
122*4882a593Smuzhiyun } else {
123*4882a593Smuzhiyun /* bcd mode */
124*4882a593Smuzhiyun m48t86_writeb(dev, bin2bcd(tm->tm_sec), M48T86_SEC);
125*4882a593Smuzhiyun m48t86_writeb(dev, bin2bcd(tm->tm_min), M48T86_MIN);
126*4882a593Smuzhiyun m48t86_writeb(dev, bin2bcd(tm->tm_hour), M48T86_HOUR);
127*4882a593Smuzhiyun m48t86_writeb(dev, bin2bcd(tm->tm_mday), M48T86_DOM);
128*4882a593Smuzhiyun m48t86_writeb(dev, bin2bcd(tm->tm_mon + 1), M48T86_MONTH);
129*4882a593Smuzhiyun m48t86_writeb(dev, bin2bcd(tm->tm_year % 100), M48T86_YEAR);
130*4882a593Smuzhiyun m48t86_writeb(dev, bin2bcd(tm->tm_wday), M48T86_DOW);
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /* update ended */
134*4882a593Smuzhiyun reg &= ~M48T86_B_SET;
135*4882a593Smuzhiyun m48t86_writeb(dev, reg, M48T86_B);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun return 0;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
m48t86_rtc_proc(struct device * dev,struct seq_file * seq)140*4882a593Smuzhiyun static int m48t86_rtc_proc(struct device *dev, struct seq_file *seq)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun unsigned char reg;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun reg = m48t86_readb(dev, M48T86_B);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun seq_printf(seq, "mode\t\t: %s\n",
147*4882a593Smuzhiyun (reg & M48T86_B_DM) ? "binary" : "bcd");
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun reg = m48t86_readb(dev, M48T86_D);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun seq_printf(seq, "battery\t\t: %s\n",
152*4882a593Smuzhiyun (reg & M48T86_D_VRT) ? "ok" : "exhausted");
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun return 0;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun static const struct rtc_class_ops m48t86_rtc_ops = {
158*4882a593Smuzhiyun .read_time = m48t86_rtc_read_time,
159*4882a593Smuzhiyun .set_time = m48t86_rtc_set_time,
160*4882a593Smuzhiyun .proc = m48t86_rtc_proc,
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun
m48t86_nvram_read(void * priv,unsigned int off,void * buf,size_t count)163*4882a593Smuzhiyun static int m48t86_nvram_read(void *priv, unsigned int off, void *buf,
164*4882a593Smuzhiyun size_t count)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun struct device *dev = priv;
167*4882a593Smuzhiyun unsigned int i;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun for (i = 0; i < count; i++)
170*4882a593Smuzhiyun ((u8 *)buf)[i] = m48t86_readb(dev, M48T86_NVRAM(off + i));
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun return 0;
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
m48t86_nvram_write(void * priv,unsigned int off,void * buf,size_t count)175*4882a593Smuzhiyun static int m48t86_nvram_write(void *priv, unsigned int off, void *buf,
176*4882a593Smuzhiyun size_t count)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun struct device *dev = priv;
179*4882a593Smuzhiyun unsigned int i;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun for (i = 0; i < count; i++)
182*4882a593Smuzhiyun m48t86_writeb(dev, ((u8 *)buf)[i], M48T86_NVRAM(off + i));
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun return 0;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun /*
188*4882a593Smuzhiyun * The RTC is an optional feature at purchase time on some Technologic Systems
189*4882a593Smuzhiyun * boards. Verify that it actually exists by checking if the last two bytes
190*4882a593Smuzhiyun * of the NVRAM can be changed.
191*4882a593Smuzhiyun *
192*4882a593Smuzhiyun * This is based on the method used in their rtc7800.c example.
193*4882a593Smuzhiyun */
m48t86_verify_chip(struct platform_device * pdev)194*4882a593Smuzhiyun static bool m48t86_verify_chip(struct platform_device *pdev)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun unsigned int offset0 = M48T86_NVRAM(M48T86_NVRAM_LEN - 2);
197*4882a593Smuzhiyun unsigned int offset1 = M48T86_NVRAM(M48T86_NVRAM_LEN - 1);
198*4882a593Smuzhiyun unsigned char tmp0, tmp1;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun tmp0 = m48t86_readb(&pdev->dev, offset0);
201*4882a593Smuzhiyun tmp1 = m48t86_readb(&pdev->dev, offset1);
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun m48t86_writeb(&pdev->dev, 0x00, offset0);
204*4882a593Smuzhiyun m48t86_writeb(&pdev->dev, 0x55, offset1);
205*4882a593Smuzhiyun if (m48t86_readb(&pdev->dev, offset1) == 0x55) {
206*4882a593Smuzhiyun m48t86_writeb(&pdev->dev, 0xaa, offset1);
207*4882a593Smuzhiyun if (m48t86_readb(&pdev->dev, offset1) == 0xaa &&
208*4882a593Smuzhiyun m48t86_readb(&pdev->dev, offset0) == 0x00) {
209*4882a593Smuzhiyun m48t86_writeb(&pdev->dev, tmp0, offset0);
210*4882a593Smuzhiyun m48t86_writeb(&pdev->dev, tmp1, offset1);
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun return true;
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun return false;
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun
m48t86_rtc_probe(struct platform_device * pdev)218*4882a593Smuzhiyun static int m48t86_rtc_probe(struct platform_device *pdev)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun struct m48t86_rtc_info *info;
221*4882a593Smuzhiyun unsigned char reg;
222*4882a593Smuzhiyun int err;
223*4882a593Smuzhiyun struct nvmem_config m48t86_nvmem_cfg = {
224*4882a593Smuzhiyun .name = "m48t86_nvram",
225*4882a593Smuzhiyun .word_size = 1,
226*4882a593Smuzhiyun .stride = 1,
227*4882a593Smuzhiyun .size = M48T86_NVRAM_LEN,
228*4882a593Smuzhiyun .reg_read = m48t86_nvram_read,
229*4882a593Smuzhiyun .reg_write = m48t86_nvram_write,
230*4882a593Smuzhiyun .priv = &pdev->dev,
231*4882a593Smuzhiyun };
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
234*4882a593Smuzhiyun if (!info)
235*4882a593Smuzhiyun return -ENOMEM;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun info->index_reg = devm_platform_ioremap_resource(pdev, 0);
238*4882a593Smuzhiyun if (IS_ERR(info->index_reg))
239*4882a593Smuzhiyun return PTR_ERR(info->index_reg);
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun info->data_reg = devm_platform_ioremap_resource(pdev, 1);
242*4882a593Smuzhiyun if (IS_ERR(info->data_reg))
243*4882a593Smuzhiyun return PTR_ERR(info->data_reg);
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun dev_set_drvdata(&pdev->dev, info);
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun if (!m48t86_verify_chip(pdev)) {
248*4882a593Smuzhiyun dev_info(&pdev->dev, "RTC not present\n");
249*4882a593Smuzhiyun return -ENODEV;
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun info->rtc = devm_rtc_allocate_device(&pdev->dev);
253*4882a593Smuzhiyun if (IS_ERR(info->rtc))
254*4882a593Smuzhiyun return PTR_ERR(info->rtc);
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun info->rtc->ops = &m48t86_rtc_ops;
257*4882a593Smuzhiyun info->rtc->nvram_old_abi = true;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun err = rtc_register_device(info->rtc);
260*4882a593Smuzhiyun if (err)
261*4882a593Smuzhiyun return err;
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun rtc_nvmem_register(info->rtc, &m48t86_nvmem_cfg);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun /* read battery status */
266*4882a593Smuzhiyun reg = m48t86_readb(&pdev->dev, M48T86_D);
267*4882a593Smuzhiyun dev_info(&pdev->dev, "battery %s\n",
268*4882a593Smuzhiyun (reg & M48T86_D_VRT) ? "ok" : "exhausted");
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun return 0;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun static struct platform_driver m48t86_rtc_platform_driver = {
274*4882a593Smuzhiyun .driver = {
275*4882a593Smuzhiyun .name = "rtc-m48t86",
276*4882a593Smuzhiyun },
277*4882a593Smuzhiyun .probe = m48t86_rtc_probe,
278*4882a593Smuzhiyun };
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun module_platform_driver(m48t86_rtc_platform_driver);
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun MODULE_AUTHOR("Alessandro Zummo <a.zummo@towertech.it>");
283*4882a593Smuzhiyun MODULE_DESCRIPTION("M48T86 RTC driver");
284*4882a593Smuzhiyun MODULE_LICENSE("GPL");
285*4882a593Smuzhiyun MODULE_ALIAS("platform:rtc-m48t86");
286