1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for the SGS-Thomson M48T35 Timekeeper RAM chip
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2000 Silicon Graphics, Inc.
6*4882a593Smuzhiyun * Written by Ulf Carlsson (ulfc@engr.sgi.com)
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Copyright (C) 2008 Thomas Bogendoerfer
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Based on code written by Paul Gortmaker.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/rtc.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/bcd.h>
18*4882a593Smuzhiyun #include <linux/io.h>
19*4882a593Smuzhiyun #include <linux/err.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun struct m48t35_rtc {
22*4882a593Smuzhiyun u8 pad[0x7ff8]; /* starts at 0x7ff8 */
23*4882a593Smuzhiyun #ifdef CONFIG_SGI_IP27
24*4882a593Smuzhiyun u8 hour;
25*4882a593Smuzhiyun u8 min;
26*4882a593Smuzhiyun u8 sec;
27*4882a593Smuzhiyun u8 control;
28*4882a593Smuzhiyun u8 year;
29*4882a593Smuzhiyun u8 month;
30*4882a593Smuzhiyun u8 date;
31*4882a593Smuzhiyun u8 day;
32*4882a593Smuzhiyun #else
33*4882a593Smuzhiyun u8 control;
34*4882a593Smuzhiyun u8 sec;
35*4882a593Smuzhiyun u8 min;
36*4882a593Smuzhiyun u8 hour;
37*4882a593Smuzhiyun u8 day;
38*4882a593Smuzhiyun u8 date;
39*4882a593Smuzhiyun u8 month;
40*4882a593Smuzhiyun u8 year;
41*4882a593Smuzhiyun #endif
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define M48T35_RTC_SET 0x80
45*4882a593Smuzhiyun #define M48T35_RTC_READ 0x40
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun struct m48t35_priv {
48*4882a593Smuzhiyun struct rtc_device *rtc;
49*4882a593Smuzhiyun struct m48t35_rtc __iomem *reg;
50*4882a593Smuzhiyun size_t size;
51*4882a593Smuzhiyun unsigned long baseaddr;
52*4882a593Smuzhiyun spinlock_t lock;
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
m48t35_read_time(struct device * dev,struct rtc_time * tm)55*4882a593Smuzhiyun static int m48t35_read_time(struct device *dev, struct rtc_time *tm)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun struct m48t35_priv *priv = dev_get_drvdata(dev);
58*4882a593Smuzhiyun u8 control;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /*
61*4882a593Smuzhiyun * Only the values that we read from the RTC are set. We leave
62*4882a593Smuzhiyun * tm_wday, tm_yday and tm_isdst untouched. Even though the
63*4882a593Smuzhiyun * RTC has RTC_DAY_OF_WEEK, we ignore it, as it is only updated
64*4882a593Smuzhiyun * by the RTC when initially set to a non-zero value.
65*4882a593Smuzhiyun */
66*4882a593Smuzhiyun spin_lock_irq(&priv->lock);
67*4882a593Smuzhiyun control = readb(&priv->reg->control);
68*4882a593Smuzhiyun writeb(control | M48T35_RTC_READ, &priv->reg->control);
69*4882a593Smuzhiyun tm->tm_sec = readb(&priv->reg->sec);
70*4882a593Smuzhiyun tm->tm_min = readb(&priv->reg->min);
71*4882a593Smuzhiyun tm->tm_hour = readb(&priv->reg->hour);
72*4882a593Smuzhiyun tm->tm_mday = readb(&priv->reg->date);
73*4882a593Smuzhiyun tm->tm_mon = readb(&priv->reg->month);
74*4882a593Smuzhiyun tm->tm_year = readb(&priv->reg->year);
75*4882a593Smuzhiyun writeb(control, &priv->reg->control);
76*4882a593Smuzhiyun spin_unlock_irq(&priv->lock);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun tm->tm_sec = bcd2bin(tm->tm_sec);
79*4882a593Smuzhiyun tm->tm_min = bcd2bin(tm->tm_min);
80*4882a593Smuzhiyun tm->tm_hour = bcd2bin(tm->tm_hour);
81*4882a593Smuzhiyun tm->tm_mday = bcd2bin(tm->tm_mday);
82*4882a593Smuzhiyun tm->tm_mon = bcd2bin(tm->tm_mon);
83*4882a593Smuzhiyun tm->tm_year = bcd2bin(tm->tm_year);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /*
86*4882a593Smuzhiyun * Account for differences between how the RTC uses the values
87*4882a593Smuzhiyun * and how they are defined in a struct rtc_time;
88*4882a593Smuzhiyun */
89*4882a593Smuzhiyun tm->tm_year += 70;
90*4882a593Smuzhiyun if (tm->tm_year <= 69)
91*4882a593Smuzhiyun tm->tm_year += 100;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun tm->tm_mon--;
94*4882a593Smuzhiyun return 0;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
m48t35_set_time(struct device * dev,struct rtc_time * tm)97*4882a593Smuzhiyun static int m48t35_set_time(struct device *dev, struct rtc_time *tm)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun struct m48t35_priv *priv = dev_get_drvdata(dev);
100*4882a593Smuzhiyun unsigned char mon, day, hrs, min, sec;
101*4882a593Smuzhiyun unsigned int yrs;
102*4882a593Smuzhiyun u8 control;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun yrs = tm->tm_year + 1900;
105*4882a593Smuzhiyun mon = tm->tm_mon + 1; /* tm_mon starts at zero */
106*4882a593Smuzhiyun day = tm->tm_mday;
107*4882a593Smuzhiyun hrs = tm->tm_hour;
108*4882a593Smuzhiyun min = tm->tm_min;
109*4882a593Smuzhiyun sec = tm->tm_sec;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun if (yrs < 1970)
112*4882a593Smuzhiyun return -EINVAL;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun yrs -= 1970;
115*4882a593Smuzhiyun if (yrs > 255) /* They are unsigned */
116*4882a593Smuzhiyun return -EINVAL;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun if (yrs > 169)
119*4882a593Smuzhiyun return -EINVAL;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun if (yrs >= 100)
122*4882a593Smuzhiyun yrs -= 100;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun sec = bin2bcd(sec);
125*4882a593Smuzhiyun min = bin2bcd(min);
126*4882a593Smuzhiyun hrs = bin2bcd(hrs);
127*4882a593Smuzhiyun day = bin2bcd(day);
128*4882a593Smuzhiyun mon = bin2bcd(mon);
129*4882a593Smuzhiyun yrs = bin2bcd(yrs);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun spin_lock_irq(&priv->lock);
132*4882a593Smuzhiyun control = readb(&priv->reg->control);
133*4882a593Smuzhiyun writeb(control | M48T35_RTC_SET, &priv->reg->control);
134*4882a593Smuzhiyun writeb(yrs, &priv->reg->year);
135*4882a593Smuzhiyun writeb(mon, &priv->reg->month);
136*4882a593Smuzhiyun writeb(day, &priv->reg->date);
137*4882a593Smuzhiyun writeb(hrs, &priv->reg->hour);
138*4882a593Smuzhiyun writeb(min, &priv->reg->min);
139*4882a593Smuzhiyun writeb(sec, &priv->reg->sec);
140*4882a593Smuzhiyun writeb(control, &priv->reg->control);
141*4882a593Smuzhiyun spin_unlock_irq(&priv->lock);
142*4882a593Smuzhiyun return 0;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun static const struct rtc_class_ops m48t35_ops = {
146*4882a593Smuzhiyun .read_time = m48t35_read_time,
147*4882a593Smuzhiyun .set_time = m48t35_set_time,
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun
m48t35_probe(struct platform_device * pdev)150*4882a593Smuzhiyun static int m48t35_probe(struct platform_device *pdev)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun struct resource *res;
153*4882a593Smuzhiyun struct m48t35_priv *priv;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
156*4882a593Smuzhiyun if (!res)
157*4882a593Smuzhiyun return -ENODEV;
158*4882a593Smuzhiyun priv = devm_kzalloc(&pdev->dev, sizeof(struct m48t35_priv), GFP_KERNEL);
159*4882a593Smuzhiyun if (!priv)
160*4882a593Smuzhiyun return -ENOMEM;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun priv->size = resource_size(res);
163*4882a593Smuzhiyun if (!devm_request_mem_region(&pdev->dev, res->start, priv->size,
164*4882a593Smuzhiyun pdev->name))
165*4882a593Smuzhiyun return -EBUSY;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun priv->baseaddr = res->start;
168*4882a593Smuzhiyun priv->reg = devm_ioremap(&pdev->dev, priv->baseaddr, priv->size);
169*4882a593Smuzhiyun if (!priv->reg)
170*4882a593Smuzhiyun return -ENOMEM;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun spin_lock_init(&priv->lock);
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun platform_set_drvdata(pdev, priv);
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun priv->rtc = devm_rtc_device_register(&pdev->dev, "m48t35",
177*4882a593Smuzhiyun &m48t35_ops, THIS_MODULE);
178*4882a593Smuzhiyun return PTR_ERR_OR_ZERO(priv->rtc);
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun static struct platform_driver m48t35_platform_driver = {
182*4882a593Smuzhiyun .driver = {
183*4882a593Smuzhiyun .name = "rtc-m48t35",
184*4882a593Smuzhiyun },
185*4882a593Smuzhiyun .probe = m48t35_probe,
186*4882a593Smuzhiyun };
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun module_platform_driver(m48t35_platform_driver);
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun MODULE_AUTHOR("Thomas Bogendoerfer <tsbogend@alpha.franken.de>");
191*4882a593Smuzhiyun MODULE_DESCRIPTION("M48T35 RTC driver");
192*4882a593Smuzhiyun MODULE_LICENSE("GPL");
193*4882a593Smuzhiyun MODULE_ALIAS("platform:rtc-m48t35");
194