xref: /OK3568_Linux_fs/kernel/drivers/rtc/rtc-ls1x.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2011 Zhao Zhang <zhzhl555@gmail.com>
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Derived from driver/rtc/rtc-au1xxx.c
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/rtc.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/types.h>
15*4882a593Smuzhiyun #include <linux/io.h>
16*4882a593Smuzhiyun #include <loongson1.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define LS1X_RTC_REG_OFFSET	(LS1X_RTC_BASE + 0x20)
19*4882a593Smuzhiyun #define LS1X_RTC_REGS(x) \
20*4882a593Smuzhiyun 		((void __iomem *)KSEG1ADDR(LS1X_RTC_REG_OFFSET + (x)))
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /*RTC programmable counters 0 and 1*/
23*4882a593Smuzhiyun #define SYS_COUNTER_CNTRL		(LS1X_RTC_REGS(0x20))
24*4882a593Smuzhiyun #define SYS_CNTRL_ERS			(1 << 23)
25*4882a593Smuzhiyun #define SYS_CNTRL_RTS			(1 << 20)
26*4882a593Smuzhiyun #define SYS_CNTRL_RM2			(1 << 19)
27*4882a593Smuzhiyun #define SYS_CNTRL_RM1			(1 << 18)
28*4882a593Smuzhiyun #define SYS_CNTRL_RM0			(1 << 17)
29*4882a593Smuzhiyun #define SYS_CNTRL_RS			(1 << 16)
30*4882a593Smuzhiyun #define SYS_CNTRL_BP			(1 << 14)
31*4882a593Smuzhiyun #define SYS_CNTRL_REN			(1 << 13)
32*4882a593Smuzhiyun #define SYS_CNTRL_BRT			(1 << 12)
33*4882a593Smuzhiyun #define SYS_CNTRL_TEN			(1 << 11)
34*4882a593Smuzhiyun #define SYS_CNTRL_BTT			(1 << 10)
35*4882a593Smuzhiyun #define SYS_CNTRL_E0			(1 << 8)
36*4882a593Smuzhiyun #define SYS_CNTRL_ETS			(1 << 7)
37*4882a593Smuzhiyun #define SYS_CNTRL_32S			(1 << 5)
38*4882a593Smuzhiyun #define SYS_CNTRL_TTS			(1 << 4)
39*4882a593Smuzhiyun #define SYS_CNTRL_TM2			(1 << 3)
40*4882a593Smuzhiyun #define SYS_CNTRL_TM1			(1 << 2)
41*4882a593Smuzhiyun #define SYS_CNTRL_TM0			(1 << 1)
42*4882a593Smuzhiyun #define SYS_CNTRL_TS			(1 << 0)
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun /* Programmable Counter 0 Registers */
45*4882a593Smuzhiyun #define SYS_TOYTRIM		(LS1X_RTC_REGS(0))
46*4882a593Smuzhiyun #define SYS_TOYWRITE0		(LS1X_RTC_REGS(4))
47*4882a593Smuzhiyun #define SYS_TOYWRITE1		(LS1X_RTC_REGS(8))
48*4882a593Smuzhiyun #define SYS_TOYREAD0		(LS1X_RTC_REGS(0xC))
49*4882a593Smuzhiyun #define SYS_TOYREAD1		(LS1X_RTC_REGS(0x10))
50*4882a593Smuzhiyun #define SYS_TOYMATCH0		(LS1X_RTC_REGS(0x14))
51*4882a593Smuzhiyun #define SYS_TOYMATCH1		(LS1X_RTC_REGS(0x18))
52*4882a593Smuzhiyun #define SYS_TOYMATCH2		(LS1X_RTC_REGS(0x1C))
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun /* Programmable Counter 1 Registers */
55*4882a593Smuzhiyun #define SYS_RTCTRIM		(LS1X_RTC_REGS(0x40))
56*4882a593Smuzhiyun #define SYS_RTCWRITE0		(LS1X_RTC_REGS(0x44))
57*4882a593Smuzhiyun #define SYS_RTCREAD0		(LS1X_RTC_REGS(0x48))
58*4882a593Smuzhiyun #define SYS_RTCMATCH0		(LS1X_RTC_REGS(0x4C))
59*4882a593Smuzhiyun #define SYS_RTCMATCH1		(LS1X_RTC_REGS(0x50))
60*4882a593Smuzhiyun #define SYS_RTCMATCH2		(LS1X_RTC_REGS(0x54))
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun #define LS1X_SEC_OFFSET		(4)
63*4882a593Smuzhiyun #define LS1X_MIN_OFFSET		(10)
64*4882a593Smuzhiyun #define LS1X_HOUR_OFFSET	(16)
65*4882a593Smuzhiyun #define LS1X_DAY_OFFSET		(21)
66*4882a593Smuzhiyun #define LS1X_MONTH_OFFSET	(26)
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define LS1X_SEC_MASK		(0x3f)
70*4882a593Smuzhiyun #define LS1X_MIN_MASK		(0x3f)
71*4882a593Smuzhiyun #define LS1X_HOUR_MASK		(0x1f)
72*4882a593Smuzhiyun #define LS1X_DAY_MASK		(0x1f)
73*4882a593Smuzhiyun #define LS1X_MONTH_MASK		(0x3f)
74*4882a593Smuzhiyun #define LS1X_YEAR_MASK		(0xffffffff)
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun #define ls1x_get_sec(t)		(((t) >> LS1X_SEC_OFFSET) & LS1X_SEC_MASK)
77*4882a593Smuzhiyun #define ls1x_get_min(t)		(((t) >> LS1X_MIN_OFFSET) & LS1X_MIN_MASK)
78*4882a593Smuzhiyun #define ls1x_get_hour(t)	(((t) >> LS1X_HOUR_OFFSET) & LS1X_HOUR_MASK)
79*4882a593Smuzhiyun #define ls1x_get_day(t)		(((t) >> LS1X_DAY_OFFSET) & LS1X_DAY_MASK)
80*4882a593Smuzhiyun #define ls1x_get_month(t)	(((t) >> LS1X_MONTH_OFFSET) & LS1X_MONTH_MASK)
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun #define RTC_CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
83*4882a593Smuzhiyun 
ls1x_rtc_read_time(struct device * dev,struct rtc_time * rtm)84*4882a593Smuzhiyun static int ls1x_rtc_read_time(struct device *dev, struct rtc_time *rtm)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun 	unsigned long v;
87*4882a593Smuzhiyun 	time64_t t;
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	v = readl(SYS_TOYREAD0);
90*4882a593Smuzhiyun 	t = readl(SYS_TOYREAD1);
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	memset(rtm, 0, sizeof(struct rtc_time));
93*4882a593Smuzhiyun 	t  = mktime64((t & LS1X_YEAR_MASK), ls1x_get_month(v),
94*4882a593Smuzhiyun 			ls1x_get_day(v), ls1x_get_hour(v),
95*4882a593Smuzhiyun 			ls1x_get_min(v), ls1x_get_sec(v));
96*4882a593Smuzhiyun 	rtc_time64_to_tm(t, rtm);
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	return 0;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun 
ls1x_rtc_set_time(struct device * dev,struct rtc_time * rtm)101*4882a593Smuzhiyun static int ls1x_rtc_set_time(struct device *dev, struct  rtc_time *rtm)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun 	unsigned long v, t, c;
104*4882a593Smuzhiyun 	int ret = -ETIMEDOUT;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	v = ((rtm->tm_mon + 1)  << LS1X_MONTH_OFFSET)
107*4882a593Smuzhiyun 		| (rtm->tm_mday << LS1X_DAY_OFFSET)
108*4882a593Smuzhiyun 		| (rtm->tm_hour << LS1X_HOUR_OFFSET)
109*4882a593Smuzhiyun 		| (rtm->tm_min  << LS1X_MIN_OFFSET)
110*4882a593Smuzhiyun 		| (rtm->tm_sec  << LS1X_SEC_OFFSET);
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	writel(v, SYS_TOYWRITE0);
113*4882a593Smuzhiyun 	c = 0x10000;
114*4882a593Smuzhiyun 	/* add timeout check counter, for more safe */
115*4882a593Smuzhiyun 	while ((readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TS) && --c)
116*4882a593Smuzhiyun 		usleep_range(1000, 3000);
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	if (!c) {
119*4882a593Smuzhiyun 		dev_err(dev, "set time timeout!\n");
120*4882a593Smuzhiyun 		goto err;
121*4882a593Smuzhiyun 	}
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	t = rtm->tm_year + 1900;
124*4882a593Smuzhiyun 	writel(t, SYS_TOYWRITE1);
125*4882a593Smuzhiyun 	c = 0x10000;
126*4882a593Smuzhiyun 	while ((readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TS) && --c)
127*4882a593Smuzhiyun 		usleep_range(1000, 3000);
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	if (!c) {
130*4882a593Smuzhiyun 		dev_err(dev, "set time timeout!\n");
131*4882a593Smuzhiyun 		goto err;
132*4882a593Smuzhiyun 	}
133*4882a593Smuzhiyun 	return 0;
134*4882a593Smuzhiyun err:
135*4882a593Smuzhiyun 	return ret;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun static const struct rtc_class_ops  ls1x_rtc_ops = {
139*4882a593Smuzhiyun 	.read_time	= ls1x_rtc_read_time,
140*4882a593Smuzhiyun 	.set_time	= ls1x_rtc_set_time,
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun 
ls1x_rtc_probe(struct platform_device * pdev)143*4882a593Smuzhiyun static int ls1x_rtc_probe(struct platform_device *pdev)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun 	struct rtc_device *rtcdev;
146*4882a593Smuzhiyun 	unsigned long v;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	v = readl(SYS_COUNTER_CNTRL);
149*4882a593Smuzhiyun 	if (!(v & RTC_CNTR_OK)) {
150*4882a593Smuzhiyun 		dev_err(&pdev->dev, "rtc counters not working\n");
151*4882a593Smuzhiyun 		return -ENODEV;
152*4882a593Smuzhiyun 	}
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	/* set to 1 HZ if needed */
155*4882a593Smuzhiyun 	if (readl(SYS_TOYTRIM) != 32767) {
156*4882a593Smuzhiyun 		v = 0x100000;
157*4882a593Smuzhiyun 		while ((readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TTS) && --v)
158*4882a593Smuzhiyun 			usleep_range(1000, 3000);
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 		if (!v) {
161*4882a593Smuzhiyun 			dev_err(&pdev->dev, "time out\n");
162*4882a593Smuzhiyun 			return -ETIMEDOUT;
163*4882a593Smuzhiyun 		}
164*4882a593Smuzhiyun 		writel(32767, SYS_TOYTRIM);
165*4882a593Smuzhiyun 	}
166*4882a593Smuzhiyun 	/* this loop coundn't be endless */
167*4882a593Smuzhiyun 	while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TTS)
168*4882a593Smuzhiyun 		usleep_range(1000, 3000);
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	rtcdev = devm_rtc_allocate_device(&pdev->dev);
171*4882a593Smuzhiyun 	if (IS_ERR(rtcdev))
172*4882a593Smuzhiyun 		return PTR_ERR(rtcdev);
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	platform_set_drvdata(pdev, rtcdev);
175*4882a593Smuzhiyun 	rtcdev->ops = &ls1x_rtc_ops;
176*4882a593Smuzhiyun 	rtcdev->range_min = RTC_TIMESTAMP_BEGIN_1900;
177*4882a593Smuzhiyun 	rtcdev->range_max = RTC_TIMESTAMP_END_2099;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	return rtc_register_device(rtcdev);
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun static struct platform_driver  ls1x_rtc_driver = {
183*4882a593Smuzhiyun 	.driver		= {
184*4882a593Smuzhiyun 		.name	= "ls1x-rtc",
185*4882a593Smuzhiyun 	},
186*4882a593Smuzhiyun 	.probe		= ls1x_rtc_probe,
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun module_platform_driver(ls1x_rtc_driver);
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun MODULE_AUTHOR("zhao zhang <zhzhl555@gmail.com>");
192*4882a593Smuzhiyun MODULE_LICENSE("GPL");
193