xref: /OK3568_Linux_fs/kernel/drivers/rtc/rtc-lpc24xx.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * RTC driver for NXP LPC178x/18xx/43xx Real-Time Clock (RTC)
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2011 NXP Semiconductors
6*4882a593Smuzhiyun  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/clk.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/of.h>
14*4882a593Smuzhiyun #include <linux/of_device.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/rtc.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun /* LPC24xx RTC register offsets and bits */
19*4882a593Smuzhiyun #define LPC24XX_ILR		0x00
20*4882a593Smuzhiyun #define  LPC24XX_RTCCIF		BIT(0)
21*4882a593Smuzhiyun #define  LPC24XX_RTCALF		BIT(1)
22*4882a593Smuzhiyun #define LPC24XX_CTC		0x04
23*4882a593Smuzhiyun #define LPC24XX_CCR		0x08
24*4882a593Smuzhiyun #define  LPC24XX_CLKEN		BIT(0)
25*4882a593Smuzhiyun #define  LPC178X_CCALEN		BIT(4)
26*4882a593Smuzhiyun #define LPC24XX_CIIR		0x0c
27*4882a593Smuzhiyun #define LPC24XX_AMR		0x10
28*4882a593Smuzhiyun #define  LPC24XX_ALARM_DISABLE	0xff
29*4882a593Smuzhiyun #define LPC24XX_CTIME0		0x14
30*4882a593Smuzhiyun #define LPC24XX_CTIME1		0x18
31*4882a593Smuzhiyun #define LPC24XX_CTIME2		0x1c
32*4882a593Smuzhiyun #define LPC24XX_SEC		0x20
33*4882a593Smuzhiyun #define LPC24XX_MIN		0x24
34*4882a593Smuzhiyun #define LPC24XX_HOUR		0x28
35*4882a593Smuzhiyun #define LPC24XX_DOM		0x2c
36*4882a593Smuzhiyun #define LPC24XX_DOW		0x30
37*4882a593Smuzhiyun #define LPC24XX_DOY		0x34
38*4882a593Smuzhiyun #define LPC24XX_MONTH		0x38
39*4882a593Smuzhiyun #define LPC24XX_YEAR		0x3c
40*4882a593Smuzhiyun #define LPC24XX_ALSEC		0x60
41*4882a593Smuzhiyun #define LPC24XX_ALMIN		0x64
42*4882a593Smuzhiyun #define LPC24XX_ALHOUR		0x68
43*4882a593Smuzhiyun #define LPC24XX_ALDOM		0x6c
44*4882a593Smuzhiyun #define LPC24XX_ALDOW		0x70
45*4882a593Smuzhiyun #define LPC24XX_ALDOY		0x74
46*4882a593Smuzhiyun #define LPC24XX_ALMON		0x78
47*4882a593Smuzhiyun #define LPC24XX_ALYEAR		0x7c
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun /* Macros to read fields in consolidated time (CT) registers */
50*4882a593Smuzhiyun #define CT0_SECS(x)		(((x) >> 0)  & 0x3f)
51*4882a593Smuzhiyun #define CT0_MINS(x)		(((x) >> 8)  & 0x3f)
52*4882a593Smuzhiyun #define CT0_HOURS(x)		(((x) >> 16) & 0x1f)
53*4882a593Smuzhiyun #define CT0_DOW(x)		(((x) >> 24) & 0x07)
54*4882a593Smuzhiyun #define CT1_DOM(x)		(((x) >> 0)  & 0x1f)
55*4882a593Smuzhiyun #define CT1_MONTH(x)		(((x) >> 8)  & 0x0f)
56*4882a593Smuzhiyun #define CT1_YEAR(x)		(((x) >> 16) & 0xfff)
57*4882a593Smuzhiyun #define CT2_DOY(x)		(((x) >> 0)  & 0xfff)
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun #define rtc_readl(dev, reg)		readl((dev)->rtc_base + (reg))
60*4882a593Smuzhiyun #define rtc_writel(dev, reg, val)	writel((val), (dev)->rtc_base + (reg))
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun struct lpc24xx_rtc {
63*4882a593Smuzhiyun 	void __iomem *rtc_base;
64*4882a593Smuzhiyun 	struct rtc_device *rtc;
65*4882a593Smuzhiyun 	struct clk *clk_rtc;
66*4882a593Smuzhiyun 	struct clk *clk_reg;
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun 
lpc24xx_rtc_set_time(struct device * dev,struct rtc_time * tm)69*4882a593Smuzhiyun static int lpc24xx_rtc_set_time(struct device *dev, struct rtc_time *tm)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun 	struct lpc24xx_rtc *rtc = dev_get_drvdata(dev);
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	/* Disable RTC during update */
74*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_CCR, LPC178X_CCALEN);
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_SEC,	tm->tm_sec);
77*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_MIN,	tm->tm_min);
78*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_HOUR,	tm->tm_hour);
79*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_DOW,	tm->tm_wday);
80*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_DOM,	tm->tm_mday);
81*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_DOY,	tm->tm_yday);
82*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_MONTH,	tm->tm_mon);
83*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_YEAR,	tm->tm_year);
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_CCR, LPC24XX_CLKEN | LPC178X_CCALEN);
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	return 0;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun 
lpc24xx_rtc_read_time(struct device * dev,struct rtc_time * tm)90*4882a593Smuzhiyun static int lpc24xx_rtc_read_time(struct device *dev, struct rtc_time *tm)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun 	struct lpc24xx_rtc *rtc = dev_get_drvdata(dev);
93*4882a593Smuzhiyun 	u32 ct0, ct1, ct2;
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	ct0 = rtc_readl(rtc, LPC24XX_CTIME0);
96*4882a593Smuzhiyun 	ct1 = rtc_readl(rtc, LPC24XX_CTIME1);
97*4882a593Smuzhiyun 	ct2 = rtc_readl(rtc, LPC24XX_CTIME2);
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	tm->tm_sec  = CT0_SECS(ct0);
100*4882a593Smuzhiyun 	tm->tm_min  = CT0_MINS(ct0);
101*4882a593Smuzhiyun 	tm->tm_hour = CT0_HOURS(ct0);
102*4882a593Smuzhiyun 	tm->tm_wday = CT0_DOW(ct0);
103*4882a593Smuzhiyun 	tm->tm_mon  = CT1_MONTH(ct1);
104*4882a593Smuzhiyun 	tm->tm_mday = CT1_DOM(ct1);
105*4882a593Smuzhiyun 	tm->tm_year = CT1_YEAR(ct1);
106*4882a593Smuzhiyun 	tm->tm_yday = CT2_DOY(ct2);
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	return 0;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun 
lpc24xx_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * wkalrm)111*4882a593Smuzhiyun static int lpc24xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun 	struct lpc24xx_rtc *rtc = dev_get_drvdata(dev);
114*4882a593Smuzhiyun 	struct rtc_time *tm = &wkalrm->time;
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	tm->tm_sec  = rtc_readl(rtc, LPC24XX_ALSEC);
117*4882a593Smuzhiyun 	tm->tm_min  = rtc_readl(rtc, LPC24XX_ALMIN);
118*4882a593Smuzhiyun 	tm->tm_hour = rtc_readl(rtc, LPC24XX_ALHOUR);
119*4882a593Smuzhiyun 	tm->tm_mday = rtc_readl(rtc, LPC24XX_ALDOM);
120*4882a593Smuzhiyun 	tm->tm_wday = rtc_readl(rtc, LPC24XX_ALDOW);
121*4882a593Smuzhiyun 	tm->tm_yday = rtc_readl(rtc, LPC24XX_ALDOY);
122*4882a593Smuzhiyun 	tm->tm_mon  = rtc_readl(rtc, LPC24XX_ALMON);
123*4882a593Smuzhiyun 	tm->tm_year = rtc_readl(rtc, LPC24XX_ALYEAR);
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	wkalrm->enabled = rtc_readl(rtc, LPC24XX_AMR) == 0;
126*4882a593Smuzhiyun 	wkalrm->pending = !!(rtc_readl(rtc, LPC24XX_ILR) & LPC24XX_RTCCIF);
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	return rtc_valid_tm(&wkalrm->time);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun 
lpc24xx_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * wkalrm)131*4882a593Smuzhiyun static int lpc24xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun 	struct lpc24xx_rtc *rtc = dev_get_drvdata(dev);
134*4882a593Smuzhiyun 	struct rtc_time *tm = &wkalrm->time;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	/* Disable alarm irq during update */
137*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_AMR, LPC24XX_ALARM_DISABLE);
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_ALSEC,  tm->tm_sec);
140*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_ALMIN,  tm->tm_min);
141*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_ALHOUR, tm->tm_hour);
142*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_ALDOM,  tm->tm_mday);
143*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_ALDOW,  tm->tm_wday);
144*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_ALDOY,  tm->tm_yday);
145*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_ALMON,  tm->tm_mon);
146*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_ALYEAR, tm->tm_year);
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	if (wkalrm->enabled)
149*4882a593Smuzhiyun 		rtc_writel(rtc, LPC24XX_AMR, 0);
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	return 0;
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun 
lpc24xx_rtc_alarm_irq_enable(struct device * dev,unsigned int enable)154*4882a593Smuzhiyun static int lpc24xx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun 	struct lpc24xx_rtc *rtc = dev_get_drvdata(dev);
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	if (enable)
159*4882a593Smuzhiyun 		rtc_writel(rtc, LPC24XX_AMR, 0);
160*4882a593Smuzhiyun 	else
161*4882a593Smuzhiyun 		rtc_writel(rtc, LPC24XX_AMR, LPC24XX_ALARM_DISABLE);
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	return 0;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun 
lpc24xx_rtc_interrupt(int irq,void * data)166*4882a593Smuzhiyun static irqreturn_t lpc24xx_rtc_interrupt(int irq, void *data)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun 	unsigned long events = RTC_IRQF;
169*4882a593Smuzhiyun 	struct lpc24xx_rtc *rtc = data;
170*4882a593Smuzhiyun 	u32 rtc_iir;
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	/* Check interrupt cause */
173*4882a593Smuzhiyun 	rtc_iir = rtc_readl(rtc, LPC24XX_ILR);
174*4882a593Smuzhiyun 	if (rtc_iir & LPC24XX_RTCALF) {
175*4882a593Smuzhiyun 		events |= RTC_AF;
176*4882a593Smuzhiyun 		rtc_writel(rtc, LPC24XX_AMR, LPC24XX_ALARM_DISABLE);
177*4882a593Smuzhiyun 	}
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	/* Clear interrupt status and report event */
180*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_ILR, rtc_iir);
181*4882a593Smuzhiyun 	rtc_update_irq(rtc->rtc, 1, events);
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	return IRQ_HANDLED;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun static const struct rtc_class_ops lpc24xx_rtc_ops = {
187*4882a593Smuzhiyun 	.read_time		= lpc24xx_rtc_read_time,
188*4882a593Smuzhiyun 	.set_time		= lpc24xx_rtc_set_time,
189*4882a593Smuzhiyun 	.read_alarm		= lpc24xx_rtc_read_alarm,
190*4882a593Smuzhiyun 	.set_alarm		= lpc24xx_rtc_set_alarm,
191*4882a593Smuzhiyun 	.alarm_irq_enable	= lpc24xx_rtc_alarm_irq_enable,
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun 
lpc24xx_rtc_probe(struct platform_device * pdev)194*4882a593Smuzhiyun static int lpc24xx_rtc_probe(struct platform_device *pdev)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun 	struct lpc24xx_rtc *rtc;
197*4882a593Smuzhiyun 	int irq, ret;
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
200*4882a593Smuzhiyun 	if (!rtc)
201*4882a593Smuzhiyun 		return -ENOMEM;
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	rtc->rtc_base = devm_platform_ioremap_resource(pdev, 0);
204*4882a593Smuzhiyun 	if (IS_ERR(rtc->rtc_base))
205*4882a593Smuzhiyun 		return PTR_ERR(rtc->rtc_base);
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	irq = platform_get_irq(pdev, 0);
208*4882a593Smuzhiyun 	if (irq < 0)
209*4882a593Smuzhiyun 		return irq;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	rtc->clk_rtc = devm_clk_get(&pdev->dev, "rtc");
212*4882a593Smuzhiyun 	if (IS_ERR(rtc->clk_rtc)) {
213*4882a593Smuzhiyun 		dev_err(&pdev->dev, "error getting rtc clock\n");
214*4882a593Smuzhiyun 		return PTR_ERR(rtc->clk_rtc);
215*4882a593Smuzhiyun 	}
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	rtc->clk_reg = devm_clk_get(&pdev->dev, "reg");
218*4882a593Smuzhiyun 	if (IS_ERR(rtc->clk_reg)) {
219*4882a593Smuzhiyun 		dev_err(&pdev->dev, "error getting reg clock\n");
220*4882a593Smuzhiyun 		return PTR_ERR(rtc->clk_reg);
221*4882a593Smuzhiyun 	}
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	ret = clk_prepare_enable(rtc->clk_rtc);
224*4882a593Smuzhiyun 	if (ret) {
225*4882a593Smuzhiyun 		dev_err(&pdev->dev, "unable to enable rtc clock\n");
226*4882a593Smuzhiyun 		return ret;
227*4882a593Smuzhiyun 	}
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	ret = clk_prepare_enable(rtc->clk_reg);
230*4882a593Smuzhiyun 	if (ret) {
231*4882a593Smuzhiyun 		dev_err(&pdev->dev, "unable to enable reg clock\n");
232*4882a593Smuzhiyun 		goto disable_rtc_clk;
233*4882a593Smuzhiyun 	}
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	platform_set_drvdata(pdev, rtc);
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	/* Clear any pending interrupts */
238*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_ILR, LPC24XX_RTCCIF | LPC24XX_RTCALF);
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	/* Enable RTC count */
241*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_CCR, LPC24XX_CLKEN | LPC178X_CCALEN);
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	ret = devm_request_irq(&pdev->dev, irq, lpc24xx_rtc_interrupt, 0,
244*4882a593Smuzhiyun 			       pdev->name, rtc);
245*4882a593Smuzhiyun 	if (ret < 0) {
246*4882a593Smuzhiyun 		dev_warn(&pdev->dev, "can't request interrupt\n");
247*4882a593Smuzhiyun 		goto disable_clks;
248*4882a593Smuzhiyun 	}
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	rtc->rtc = devm_rtc_device_register(&pdev->dev, "lpc24xx-rtc",
251*4882a593Smuzhiyun 					    &lpc24xx_rtc_ops, THIS_MODULE);
252*4882a593Smuzhiyun 	if (IS_ERR(rtc->rtc)) {
253*4882a593Smuzhiyun 		dev_err(&pdev->dev, "can't register rtc device\n");
254*4882a593Smuzhiyun 		ret = PTR_ERR(rtc->rtc);
255*4882a593Smuzhiyun 		goto disable_clks;
256*4882a593Smuzhiyun 	}
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 	return 0;
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun disable_clks:
261*4882a593Smuzhiyun 	clk_disable_unprepare(rtc->clk_reg);
262*4882a593Smuzhiyun disable_rtc_clk:
263*4882a593Smuzhiyun 	clk_disable_unprepare(rtc->clk_rtc);
264*4882a593Smuzhiyun 	return ret;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun 
lpc24xx_rtc_remove(struct platform_device * pdev)267*4882a593Smuzhiyun static int lpc24xx_rtc_remove(struct platform_device *pdev)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun 	struct lpc24xx_rtc *rtc = platform_get_drvdata(pdev);
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	/* Ensure all interrupt sources are masked */
272*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_AMR, LPC24XX_ALARM_DISABLE);
273*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_CIIR, 0);
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun 	rtc_writel(rtc, LPC24XX_CCR, LPC178X_CCALEN);
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	clk_disable_unprepare(rtc->clk_rtc);
278*4882a593Smuzhiyun 	clk_disable_unprepare(rtc->clk_reg);
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	return 0;
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun static const struct of_device_id lpc24xx_rtc_match[] = {
284*4882a593Smuzhiyun 	{ .compatible = "nxp,lpc1788-rtc" },
285*4882a593Smuzhiyun 	{ }
286*4882a593Smuzhiyun };
287*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, lpc24xx_rtc_match);
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun static struct platform_driver lpc24xx_rtc_driver = {
290*4882a593Smuzhiyun 	.probe	= lpc24xx_rtc_probe,
291*4882a593Smuzhiyun 	.remove	= lpc24xx_rtc_remove,
292*4882a593Smuzhiyun 	.driver	= {
293*4882a593Smuzhiyun 		.name = "lpc24xx-rtc",
294*4882a593Smuzhiyun 		.of_match_table	= lpc24xx_rtc_match,
295*4882a593Smuzhiyun 	},
296*4882a593Smuzhiyun };
297*4882a593Smuzhiyun module_platform_driver(lpc24xx_rtc_driver);
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun MODULE_AUTHOR("Kevin Wells <wellsk40@gmail.com>");
300*4882a593Smuzhiyun MODULE_DESCRIPTION("RTC driver for the LPC178x/18xx/408x/43xx SoCs");
301*4882a593Smuzhiyun MODULE_LICENSE("GPL");
302