1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * An I2C driver for the Intersil ISL 12026
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2018 Cavium, Inc.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/bcd.h>
8*4882a593Smuzhiyun #include <linux/delay.h>
9*4882a593Smuzhiyun #include <linux/i2c.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/mutex.h>
12*4882a593Smuzhiyun #include <linux/nvmem-provider.h>
13*4882a593Smuzhiyun #include <linux/of.h>
14*4882a593Smuzhiyun #include <linux/of_device.h>
15*4882a593Smuzhiyun #include <linux/rtc.h>
16*4882a593Smuzhiyun #include <linux/slab.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* register offsets */
19*4882a593Smuzhiyun #define ISL12026_REG_PWR 0x14
20*4882a593Smuzhiyun # define ISL12026_REG_PWR_BSW BIT(6)
21*4882a593Smuzhiyun # define ISL12026_REG_PWR_SBIB BIT(7)
22*4882a593Smuzhiyun #define ISL12026_REG_SC 0x30
23*4882a593Smuzhiyun #define ISL12026_REG_HR 0x32
24*4882a593Smuzhiyun # define ISL12026_REG_HR_MIL BIT(7) /* military or 24 hour time */
25*4882a593Smuzhiyun #define ISL12026_REG_SR 0x3f
26*4882a593Smuzhiyun # define ISL12026_REG_SR_RTCF BIT(0)
27*4882a593Smuzhiyun # define ISL12026_REG_SR_WEL BIT(1)
28*4882a593Smuzhiyun # define ISL12026_REG_SR_RWEL BIT(2)
29*4882a593Smuzhiyun # define ISL12026_REG_SR_MBZ BIT(3)
30*4882a593Smuzhiyun # define ISL12026_REG_SR_OSCF BIT(4)
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* The EEPROM array responds at i2c address 0x57 */
33*4882a593Smuzhiyun #define ISL12026_EEPROM_ADDR 0x57
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define ISL12026_PAGESIZE 16
36*4882a593Smuzhiyun #define ISL12026_NVMEM_WRITE_TIME 20
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun struct isl12026 {
39*4882a593Smuzhiyun struct rtc_device *rtc;
40*4882a593Smuzhiyun struct i2c_client *nvm_client;
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
isl12026_read_reg(struct i2c_client * client,int reg)43*4882a593Smuzhiyun static int isl12026_read_reg(struct i2c_client *client, int reg)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun u8 addr[] = {0, reg};
46*4882a593Smuzhiyun u8 val;
47*4882a593Smuzhiyun int ret;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun struct i2c_msg msgs[] = {
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun .addr = client->addr,
52*4882a593Smuzhiyun .flags = 0,
53*4882a593Smuzhiyun .len = sizeof(addr),
54*4882a593Smuzhiyun .buf = addr
55*4882a593Smuzhiyun }, {
56*4882a593Smuzhiyun .addr = client->addr,
57*4882a593Smuzhiyun .flags = I2C_M_RD,
58*4882a593Smuzhiyun .len = 1,
59*4882a593Smuzhiyun .buf = &val
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
64*4882a593Smuzhiyun if (ret != ARRAY_SIZE(msgs)) {
65*4882a593Smuzhiyun dev_err(&client->dev, "read reg error, ret=%d\n", ret);
66*4882a593Smuzhiyun ret = ret < 0 ? ret : -EIO;
67*4882a593Smuzhiyun } else {
68*4882a593Smuzhiyun ret = val;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun return ret;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
isl12026_arm_write(struct i2c_client * client)74*4882a593Smuzhiyun static int isl12026_arm_write(struct i2c_client *client)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun int ret;
77*4882a593Smuzhiyun u8 op[3];
78*4882a593Smuzhiyun struct i2c_msg msg = {
79*4882a593Smuzhiyun .addr = client->addr,
80*4882a593Smuzhiyun .flags = 0,
81*4882a593Smuzhiyun .len = 1,
82*4882a593Smuzhiyun .buf = op
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* Set SR.WEL */
86*4882a593Smuzhiyun op[0] = 0;
87*4882a593Smuzhiyun op[1] = ISL12026_REG_SR;
88*4882a593Smuzhiyun op[2] = ISL12026_REG_SR_WEL;
89*4882a593Smuzhiyun msg.len = 3;
90*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, &msg, 1);
91*4882a593Smuzhiyun if (ret != 1) {
92*4882a593Smuzhiyun dev_err(&client->dev, "write error SR.WEL, ret=%d\n", ret);
93*4882a593Smuzhiyun ret = ret < 0 ? ret : -EIO;
94*4882a593Smuzhiyun goto out;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /* Set SR.WEL and SR.RWEL */
98*4882a593Smuzhiyun op[2] = ISL12026_REG_SR_WEL | ISL12026_REG_SR_RWEL;
99*4882a593Smuzhiyun msg.len = 3;
100*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, &msg, 1);
101*4882a593Smuzhiyun if (ret != 1) {
102*4882a593Smuzhiyun dev_err(&client->dev,
103*4882a593Smuzhiyun "write error SR.WEL|SR.RWEL, ret=%d\n", ret);
104*4882a593Smuzhiyun ret = ret < 0 ? ret : -EIO;
105*4882a593Smuzhiyun goto out;
106*4882a593Smuzhiyun } else {
107*4882a593Smuzhiyun ret = 0;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun out:
110*4882a593Smuzhiyun return ret;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
isl12026_disarm_write(struct i2c_client * client)113*4882a593Smuzhiyun static int isl12026_disarm_write(struct i2c_client *client)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun int ret;
116*4882a593Smuzhiyun u8 op[3] = {0, ISL12026_REG_SR, 0};
117*4882a593Smuzhiyun struct i2c_msg msg = {
118*4882a593Smuzhiyun .addr = client->addr,
119*4882a593Smuzhiyun .flags = 0,
120*4882a593Smuzhiyun .len = sizeof(op),
121*4882a593Smuzhiyun .buf = op
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, &msg, 1);
125*4882a593Smuzhiyun if (ret != 1) {
126*4882a593Smuzhiyun dev_err(&client->dev,
127*4882a593Smuzhiyun "write error SR, ret=%d\n", ret);
128*4882a593Smuzhiyun ret = ret < 0 ? ret : -EIO;
129*4882a593Smuzhiyun } else {
130*4882a593Smuzhiyun ret = 0;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun return ret;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
isl12026_write_reg(struct i2c_client * client,int reg,u8 val)136*4882a593Smuzhiyun static int isl12026_write_reg(struct i2c_client *client, int reg, u8 val)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun int ret;
139*4882a593Smuzhiyun u8 op[3] = {0, reg, val};
140*4882a593Smuzhiyun struct i2c_msg msg = {
141*4882a593Smuzhiyun .addr = client->addr,
142*4882a593Smuzhiyun .flags = 0,
143*4882a593Smuzhiyun .len = sizeof(op),
144*4882a593Smuzhiyun .buf = op
145*4882a593Smuzhiyun };
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun ret = isl12026_arm_write(client);
148*4882a593Smuzhiyun if (ret)
149*4882a593Smuzhiyun return ret;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, &msg, 1);
152*4882a593Smuzhiyun if (ret != 1) {
153*4882a593Smuzhiyun dev_err(&client->dev, "write error CCR, ret=%d\n", ret);
154*4882a593Smuzhiyun ret = ret < 0 ? ret : -EIO;
155*4882a593Smuzhiyun goto out;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun msleep(ISL12026_NVMEM_WRITE_TIME);
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun ret = isl12026_disarm_write(client);
161*4882a593Smuzhiyun out:
162*4882a593Smuzhiyun return ret;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
isl12026_rtc_set_time(struct device * dev,struct rtc_time * tm)165*4882a593Smuzhiyun static int isl12026_rtc_set_time(struct device *dev, struct rtc_time *tm)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
168*4882a593Smuzhiyun int ret;
169*4882a593Smuzhiyun u8 op[10];
170*4882a593Smuzhiyun struct i2c_msg msg = {
171*4882a593Smuzhiyun .addr = client->addr,
172*4882a593Smuzhiyun .flags = 0,
173*4882a593Smuzhiyun .len = sizeof(op),
174*4882a593Smuzhiyun .buf = op
175*4882a593Smuzhiyun };
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun ret = isl12026_arm_write(client);
178*4882a593Smuzhiyun if (ret)
179*4882a593Smuzhiyun return ret;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun /* Set the CCR registers */
182*4882a593Smuzhiyun op[0] = 0;
183*4882a593Smuzhiyun op[1] = ISL12026_REG_SC;
184*4882a593Smuzhiyun op[2] = bin2bcd(tm->tm_sec); /* SC */
185*4882a593Smuzhiyun op[3] = bin2bcd(tm->tm_min); /* MN */
186*4882a593Smuzhiyun op[4] = bin2bcd(tm->tm_hour) | ISL12026_REG_HR_MIL; /* HR */
187*4882a593Smuzhiyun op[5] = bin2bcd(tm->tm_mday); /* DT */
188*4882a593Smuzhiyun op[6] = bin2bcd(tm->tm_mon + 1); /* MO */
189*4882a593Smuzhiyun op[7] = bin2bcd(tm->tm_year % 100); /* YR */
190*4882a593Smuzhiyun op[8] = bin2bcd(tm->tm_wday & 7); /* DW */
191*4882a593Smuzhiyun op[9] = bin2bcd(tm->tm_year >= 100 ? 20 : 19); /* Y2K */
192*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, &msg, 1);
193*4882a593Smuzhiyun if (ret != 1) {
194*4882a593Smuzhiyun dev_err(&client->dev, "write error CCR, ret=%d\n", ret);
195*4882a593Smuzhiyun ret = ret < 0 ? ret : -EIO;
196*4882a593Smuzhiyun goto out;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun ret = isl12026_disarm_write(client);
200*4882a593Smuzhiyun out:
201*4882a593Smuzhiyun return ret;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
isl12026_rtc_read_time(struct device * dev,struct rtc_time * tm)204*4882a593Smuzhiyun static int isl12026_rtc_read_time(struct device *dev, struct rtc_time *tm)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
207*4882a593Smuzhiyun u8 ccr[8];
208*4882a593Smuzhiyun u8 addr[2];
209*4882a593Smuzhiyun u8 sr;
210*4882a593Smuzhiyun int ret;
211*4882a593Smuzhiyun struct i2c_msg msgs[] = {
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun .addr = client->addr,
214*4882a593Smuzhiyun .flags = 0,
215*4882a593Smuzhiyun .len = sizeof(addr),
216*4882a593Smuzhiyun .buf = addr
217*4882a593Smuzhiyun }, {
218*4882a593Smuzhiyun .addr = client->addr,
219*4882a593Smuzhiyun .flags = I2C_M_RD,
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun };
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun /* First, read SR */
224*4882a593Smuzhiyun addr[0] = 0;
225*4882a593Smuzhiyun addr[1] = ISL12026_REG_SR;
226*4882a593Smuzhiyun msgs[1].len = 1;
227*4882a593Smuzhiyun msgs[1].buf = &sr;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
230*4882a593Smuzhiyun if (ret != ARRAY_SIZE(msgs)) {
231*4882a593Smuzhiyun dev_err(&client->dev, "read error, ret=%d\n", ret);
232*4882a593Smuzhiyun ret = ret < 0 ? ret : -EIO;
233*4882a593Smuzhiyun goto out;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun if (sr & ISL12026_REG_SR_RTCF)
237*4882a593Smuzhiyun dev_warn(&client->dev, "Real-Time Clock Failure on read\n");
238*4882a593Smuzhiyun if (sr & ISL12026_REG_SR_OSCF)
239*4882a593Smuzhiyun dev_warn(&client->dev, "Oscillator Failure on read\n");
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun /* Second, CCR regs */
242*4882a593Smuzhiyun addr[0] = 0;
243*4882a593Smuzhiyun addr[1] = ISL12026_REG_SC;
244*4882a593Smuzhiyun msgs[1].len = sizeof(ccr);
245*4882a593Smuzhiyun msgs[1].buf = ccr;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
248*4882a593Smuzhiyun if (ret != ARRAY_SIZE(msgs)) {
249*4882a593Smuzhiyun dev_err(&client->dev, "read error, ret=%d\n", ret);
250*4882a593Smuzhiyun ret = ret < 0 ? ret : -EIO;
251*4882a593Smuzhiyun goto out;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun tm->tm_sec = bcd2bin(ccr[0] & 0x7F);
255*4882a593Smuzhiyun tm->tm_min = bcd2bin(ccr[1] & 0x7F);
256*4882a593Smuzhiyun if (ccr[2] & ISL12026_REG_HR_MIL)
257*4882a593Smuzhiyun tm->tm_hour = bcd2bin(ccr[2] & 0x3F);
258*4882a593Smuzhiyun else
259*4882a593Smuzhiyun tm->tm_hour = bcd2bin(ccr[2] & 0x1F) +
260*4882a593Smuzhiyun ((ccr[2] & 0x20) ? 12 : 0);
261*4882a593Smuzhiyun tm->tm_mday = bcd2bin(ccr[3] & 0x3F);
262*4882a593Smuzhiyun tm->tm_mon = bcd2bin(ccr[4] & 0x1F) - 1;
263*4882a593Smuzhiyun tm->tm_year = bcd2bin(ccr[5]);
264*4882a593Smuzhiyun if (bcd2bin(ccr[7]) == 20)
265*4882a593Smuzhiyun tm->tm_year += 100;
266*4882a593Smuzhiyun tm->tm_wday = ccr[6] & 0x07;
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun ret = 0;
269*4882a593Smuzhiyun out:
270*4882a593Smuzhiyun return ret;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun static const struct rtc_class_ops isl12026_rtc_ops = {
274*4882a593Smuzhiyun .read_time = isl12026_rtc_read_time,
275*4882a593Smuzhiyun .set_time = isl12026_rtc_set_time,
276*4882a593Smuzhiyun };
277*4882a593Smuzhiyun
isl12026_nvm_read(void * p,unsigned int offset,void * val,size_t bytes)278*4882a593Smuzhiyun static int isl12026_nvm_read(void *p, unsigned int offset,
279*4882a593Smuzhiyun void *val, size_t bytes)
280*4882a593Smuzhiyun {
281*4882a593Smuzhiyun struct isl12026 *priv = p;
282*4882a593Smuzhiyun int ret;
283*4882a593Smuzhiyun u8 addr[2];
284*4882a593Smuzhiyun struct i2c_msg msgs[] = {
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun .addr = priv->nvm_client->addr,
287*4882a593Smuzhiyun .flags = 0,
288*4882a593Smuzhiyun .len = sizeof(addr),
289*4882a593Smuzhiyun .buf = addr
290*4882a593Smuzhiyun }, {
291*4882a593Smuzhiyun .addr = priv->nvm_client->addr,
292*4882a593Smuzhiyun .flags = I2C_M_RD,
293*4882a593Smuzhiyun .buf = val
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun };
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun /*
298*4882a593Smuzhiyun * offset and bytes checked and limited by nvmem core, so
299*4882a593Smuzhiyun * proceed without further checks.
300*4882a593Smuzhiyun */
301*4882a593Smuzhiyun ret = mutex_lock_interruptible(&priv->rtc->ops_lock);
302*4882a593Smuzhiyun if (ret)
303*4882a593Smuzhiyun return ret;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun /* 2 bytes of address, most significant first */
306*4882a593Smuzhiyun addr[0] = offset >> 8;
307*4882a593Smuzhiyun addr[1] = offset;
308*4882a593Smuzhiyun msgs[1].len = bytes;
309*4882a593Smuzhiyun ret = i2c_transfer(priv->nvm_client->adapter, msgs, ARRAY_SIZE(msgs));
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun mutex_unlock(&priv->rtc->ops_lock);
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun if (ret != ARRAY_SIZE(msgs)) {
314*4882a593Smuzhiyun dev_err(&priv->nvm_client->dev,
315*4882a593Smuzhiyun "nvmem read error, ret=%d\n", ret);
316*4882a593Smuzhiyun return ret < 0 ? ret : -EIO;
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun return 0;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
isl12026_nvm_write(void * p,unsigned int offset,void * val,size_t bytes)322*4882a593Smuzhiyun static int isl12026_nvm_write(void *p, unsigned int offset,
323*4882a593Smuzhiyun void *val, size_t bytes)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun struct isl12026 *priv = p;
326*4882a593Smuzhiyun int ret;
327*4882a593Smuzhiyun u8 *v = val;
328*4882a593Smuzhiyun size_t chunk_size, num_written;
329*4882a593Smuzhiyun u8 payload[ISL12026_PAGESIZE + 2]; /* page + 2 address bytes */
330*4882a593Smuzhiyun struct i2c_msg msgs[] = {
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun .addr = priv->nvm_client->addr,
333*4882a593Smuzhiyun .flags = 0,
334*4882a593Smuzhiyun .buf = payload
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun };
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun /*
339*4882a593Smuzhiyun * offset and bytes checked and limited by nvmem core, so
340*4882a593Smuzhiyun * proceed without further checks.
341*4882a593Smuzhiyun */
342*4882a593Smuzhiyun ret = mutex_lock_interruptible(&priv->rtc->ops_lock);
343*4882a593Smuzhiyun if (ret)
344*4882a593Smuzhiyun return ret;
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun num_written = 0;
347*4882a593Smuzhiyun while (bytes) {
348*4882a593Smuzhiyun chunk_size = round_down(offset, ISL12026_PAGESIZE) +
349*4882a593Smuzhiyun ISL12026_PAGESIZE - offset;
350*4882a593Smuzhiyun chunk_size = min(bytes, chunk_size);
351*4882a593Smuzhiyun /*
352*4882a593Smuzhiyun * 2 bytes of address, most significant first, followed
353*4882a593Smuzhiyun * by page data bytes
354*4882a593Smuzhiyun */
355*4882a593Smuzhiyun memcpy(payload + 2, v + num_written, chunk_size);
356*4882a593Smuzhiyun payload[0] = offset >> 8;
357*4882a593Smuzhiyun payload[1] = offset;
358*4882a593Smuzhiyun msgs[0].len = chunk_size + 2;
359*4882a593Smuzhiyun ret = i2c_transfer(priv->nvm_client->adapter,
360*4882a593Smuzhiyun msgs, ARRAY_SIZE(msgs));
361*4882a593Smuzhiyun if (ret != ARRAY_SIZE(msgs)) {
362*4882a593Smuzhiyun dev_err(&priv->nvm_client->dev,
363*4882a593Smuzhiyun "nvmem write error, ret=%d\n", ret);
364*4882a593Smuzhiyun ret = ret < 0 ? ret : -EIO;
365*4882a593Smuzhiyun break;
366*4882a593Smuzhiyun }
367*4882a593Smuzhiyun ret = 0;
368*4882a593Smuzhiyun bytes -= chunk_size;
369*4882a593Smuzhiyun offset += chunk_size;
370*4882a593Smuzhiyun num_written += chunk_size;
371*4882a593Smuzhiyun msleep(ISL12026_NVMEM_WRITE_TIME);
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun mutex_unlock(&priv->rtc->ops_lock);
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun return ret;
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun
isl12026_force_power_modes(struct i2c_client * client)379*4882a593Smuzhiyun static void isl12026_force_power_modes(struct i2c_client *client)
380*4882a593Smuzhiyun {
381*4882a593Smuzhiyun int ret;
382*4882a593Smuzhiyun int pwr, requested_pwr;
383*4882a593Smuzhiyun u32 bsw_val, sbib_val;
384*4882a593Smuzhiyun bool set_bsw, set_sbib;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun /*
387*4882a593Smuzhiyun * If we can read the of_property, set the specified value.
388*4882a593Smuzhiyun * If there is an error reading the of_property (likely
389*4882a593Smuzhiyun * because it does not exist), keep the current value.
390*4882a593Smuzhiyun */
391*4882a593Smuzhiyun ret = of_property_read_u32(client->dev.of_node,
392*4882a593Smuzhiyun "isil,pwr-bsw", &bsw_val);
393*4882a593Smuzhiyun set_bsw = (ret == 0);
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun ret = of_property_read_u32(client->dev.of_node,
396*4882a593Smuzhiyun "isil,pwr-sbib", &sbib_val);
397*4882a593Smuzhiyun set_sbib = (ret == 0);
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun /* Check if PWR.BSW and/or PWR.SBIB need specified values */
400*4882a593Smuzhiyun if (!set_bsw && !set_sbib)
401*4882a593Smuzhiyun return;
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun pwr = isl12026_read_reg(client, ISL12026_REG_PWR);
404*4882a593Smuzhiyun if (pwr < 0) {
405*4882a593Smuzhiyun dev_warn(&client->dev, "Error: Failed to read PWR %d\n", pwr);
406*4882a593Smuzhiyun return;
407*4882a593Smuzhiyun }
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun requested_pwr = pwr;
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun if (set_bsw) {
412*4882a593Smuzhiyun if (bsw_val)
413*4882a593Smuzhiyun requested_pwr |= ISL12026_REG_PWR_BSW;
414*4882a593Smuzhiyun else
415*4882a593Smuzhiyun requested_pwr &= ~ISL12026_REG_PWR_BSW;
416*4882a593Smuzhiyun } /* else keep current BSW */
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun if (set_sbib) {
419*4882a593Smuzhiyun if (sbib_val)
420*4882a593Smuzhiyun requested_pwr |= ISL12026_REG_PWR_SBIB;
421*4882a593Smuzhiyun else
422*4882a593Smuzhiyun requested_pwr &= ~ISL12026_REG_PWR_SBIB;
423*4882a593Smuzhiyun } /* else keep current SBIB */
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun if (pwr >= 0 && pwr != requested_pwr) {
426*4882a593Smuzhiyun dev_dbg(&client->dev, "PWR: %02x\n", pwr);
427*4882a593Smuzhiyun dev_dbg(&client->dev, "Updating PWR to: %02x\n", requested_pwr);
428*4882a593Smuzhiyun isl12026_write_reg(client, ISL12026_REG_PWR, requested_pwr);
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun }
431*4882a593Smuzhiyun
isl12026_probe_new(struct i2c_client * client)432*4882a593Smuzhiyun static int isl12026_probe_new(struct i2c_client *client)
433*4882a593Smuzhiyun {
434*4882a593Smuzhiyun struct isl12026 *priv;
435*4882a593Smuzhiyun int ret;
436*4882a593Smuzhiyun struct nvmem_config nvm_cfg = {
437*4882a593Smuzhiyun .name = "isl12026-",
438*4882a593Smuzhiyun .base_dev = &client->dev,
439*4882a593Smuzhiyun .stride = 1,
440*4882a593Smuzhiyun .word_size = 1,
441*4882a593Smuzhiyun .size = 512,
442*4882a593Smuzhiyun .reg_read = isl12026_nvm_read,
443*4882a593Smuzhiyun .reg_write = isl12026_nvm_write,
444*4882a593Smuzhiyun };
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
447*4882a593Smuzhiyun return -ENODEV;
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
450*4882a593Smuzhiyun if (!priv)
451*4882a593Smuzhiyun return -ENOMEM;
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun i2c_set_clientdata(client, priv);
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun isl12026_force_power_modes(client);
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun priv->nvm_client = i2c_new_dummy_device(client->adapter, ISL12026_EEPROM_ADDR);
458*4882a593Smuzhiyun if (IS_ERR(priv->nvm_client))
459*4882a593Smuzhiyun return PTR_ERR(priv->nvm_client);
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun priv->rtc = devm_rtc_allocate_device(&client->dev);
462*4882a593Smuzhiyun ret = PTR_ERR_OR_ZERO(priv->rtc);
463*4882a593Smuzhiyun if (ret)
464*4882a593Smuzhiyun return ret;
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun priv->rtc->ops = &isl12026_rtc_ops;
467*4882a593Smuzhiyun nvm_cfg.priv = priv;
468*4882a593Smuzhiyun ret = rtc_nvmem_register(priv->rtc, &nvm_cfg);
469*4882a593Smuzhiyun if (ret)
470*4882a593Smuzhiyun return ret;
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun return rtc_register_device(priv->rtc);
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun
isl12026_remove(struct i2c_client * client)475*4882a593Smuzhiyun static int isl12026_remove(struct i2c_client *client)
476*4882a593Smuzhiyun {
477*4882a593Smuzhiyun struct isl12026 *priv = i2c_get_clientdata(client);
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun i2c_unregister_device(priv->nvm_client);
480*4882a593Smuzhiyun return 0;
481*4882a593Smuzhiyun }
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun static const struct of_device_id isl12026_dt_match[] = {
484*4882a593Smuzhiyun { .compatible = "isil,isl12026" },
485*4882a593Smuzhiyun { }
486*4882a593Smuzhiyun };
487*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, isl12026_dt_match);
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun static struct i2c_driver isl12026_driver = {
490*4882a593Smuzhiyun .driver = {
491*4882a593Smuzhiyun .name = "rtc-isl12026",
492*4882a593Smuzhiyun .of_match_table = isl12026_dt_match,
493*4882a593Smuzhiyun },
494*4882a593Smuzhiyun .probe_new = isl12026_probe_new,
495*4882a593Smuzhiyun .remove = isl12026_remove,
496*4882a593Smuzhiyun };
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun module_i2c_driver(isl12026_driver);
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun MODULE_DESCRIPTION("ISL 12026 RTC driver");
501*4882a593Smuzhiyun MODULE_LICENSE("GPL");
502