1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Freescale FlexTimer Module (FTM) alarm device driver.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor, Inc.
6*4882a593Smuzhiyun * Copyright 2019-2020 NXP
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/err.h>
12*4882a593Smuzhiyun #include <linux/interrupt.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/of_address.h>
15*4882a593Smuzhiyun #include <linux/of_irq.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/of.h>
18*4882a593Smuzhiyun #include <linux/of_device.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <linux/fsl/ftm.h>
21*4882a593Smuzhiyun #include <linux/rtc.h>
22*4882a593Smuzhiyun #include <linux/time.h>
23*4882a593Smuzhiyun #include <linux/acpi.h>
24*4882a593Smuzhiyun #include <linux/pm_wakeirq.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define FTM_SC_CLK(c) ((c) << FTM_SC_CLK_MASK_SHIFT)
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun * Select Fixed frequency clock (32KHz) as clock source
30*4882a593Smuzhiyun * of FlexTimer Module
31*4882a593Smuzhiyun */
32*4882a593Smuzhiyun #define FTM_SC_CLKS_FIXED_FREQ 0x02
33*4882a593Smuzhiyun #define FIXED_FREQ_CLK 32000
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Select 128 (2^7) as divider factor */
36*4882a593Smuzhiyun #define MAX_FREQ_DIV (1 << FTM_SC_PS_MASK)
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* Maximum counter value in FlexTimer's CNT registers */
39*4882a593Smuzhiyun #define MAX_COUNT_VAL 0xffff
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun struct ftm_rtc {
42*4882a593Smuzhiyun struct rtc_device *rtc_dev;
43*4882a593Smuzhiyun void __iomem *base;
44*4882a593Smuzhiyun bool big_endian;
45*4882a593Smuzhiyun u32 alarm_freq;
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
rtc_readl(struct ftm_rtc * dev,u32 reg)48*4882a593Smuzhiyun static inline u32 rtc_readl(struct ftm_rtc *dev, u32 reg)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun if (dev->big_endian)
51*4882a593Smuzhiyun return ioread32be(dev->base + reg);
52*4882a593Smuzhiyun else
53*4882a593Smuzhiyun return ioread32(dev->base + reg);
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
rtc_writel(struct ftm_rtc * dev,u32 reg,u32 val)56*4882a593Smuzhiyun static inline void rtc_writel(struct ftm_rtc *dev, u32 reg, u32 val)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun if (dev->big_endian)
59*4882a593Smuzhiyun iowrite32be(val, dev->base + reg);
60*4882a593Smuzhiyun else
61*4882a593Smuzhiyun iowrite32(val, dev->base + reg);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
ftm_counter_enable(struct ftm_rtc * rtc)64*4882a593Smuzhiyun static inline void ftm_counter_enable(struct ftm_rtc *rtc)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun u32 val;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* select and enable counter clock source */
69*4882a593Smuzhiyun val = rtc_readl(rtc, FTM_SC);
70*4882a593Smuzhiyun val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);
71*4882a593Smuzhiyun val |= (FTM_SC_PS_MASK | FTM_SC_CLK(FTM_SC_CLKS_FIXED_FREQ));
72*4882a593Smuzhiyun rtc_writel(rtc, FTM_SC, val);
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
ftm_counter_disable(struct ftm_rtc * rtc)75*4882a593Smuzhiyun static inline void ftm_counter_disable(struct ftm_rtc *rtc)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun u32 val;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /* disable counter clock source */
80*4882a593Smuzhiyun val = rtc_readl(rtc, FTM_SC);
81*4882a593Smuzhiyun val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);
82*4882a593Smuzhiyun rtc_writel(rtc, FTM_SC, val);
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
ftm_irq_acknowledge(struct ftm_rtc * rtc)85*4882a593Smuzhiyun static inline void ftm_irq_acknowledge(struct ftm_rtc *rtc)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun unsigned int timeout = 100;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /*
90*4882a593Smuzhiyun *Fix errata A-007728 for flextimer
91*4882a593Smuzhiyun * If the FTM counter reaches the FTM_MOD value between
92*4882a593Smuzhiyun * the reading of the TOF bit and the writing of 0 to
93*4882a593Smuzhiyun * the TOF bit, the process of clearing the TOF bit
94*4882a593Smuzhiyun * does not work as expected when FTMx_CONF[NUMTOF] != 0
95*4882a593Smuzhiyun * and the current TOF count is less than FTMx_CONF[NUMTOF].
96*4882a593Smuzhiyun * If the above condition is met, the TOF bit remains set.
97*4882a593Smuzhiyun * If the TOF interrupt is enabled (FTMx_SC[TOIE] = 1),the
98*4882a593Smuzhiyun * TOF interrupt also remains asserted.
99*4882a593Smuzhiyun *
100*4882a593Smuzhiyun * Above is the errata discription
101*4882a593Smuzhiyun *
102*4882a593Smuzhiyun * In one word: software clearing TOF bit not works when
103*4882a593Smuzhiyun * FTMx_CONF[NUMTOF] was seted as nonzero and FTM counter
104*4882a593Smuzhiyun * reaches the FTM_MOD value.
105*4882a593Smuzhiyun *
106*4882a593Smuzhiyun * The workaround is clearing TOF bit until it works
107*4882a593Smuzhiyun * (FTM counter doesn't always reache the FTM_MOD anyway),
108*4882a593Smuzhiyun * which may cost some cycles.
109*4882a593Smuzhiyun */
110*4882a593Smuzhiyun while ((FTM_SC_TOF & rtc_readl(rtc, FTM_SC)) && timeout--)
111*4882a593Smuzhiyun rtc_writel(rtc, FTM_SC, rtc_readl(rtc, FTM_SC) & (~FTM_SC_TOF));
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
ftm_irq_enable(struct ftm_rtc * rtc)114*4882a593Smuzhiyun static inline void ftm_irq_enable(struct ftm_rtc *rtc)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun u32 val;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun val = rtc_readl(rtc, FTM_SC);
119*4882a593Smuzhiyun val |= FTM_SC_TOIE;
120*4882a593Smuzhiyun rtc_writel(rtc, FTM_SC, val);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
ftm_irq_disable(struct ftm_rtc * rtc)123*4882a593Smuzhiyun static inline void ftm_irq_disable(struct ftm_rtc *rtc)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun u32 val;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun val = rtc_readl(rtc, FTM_SC);
128*4882a593Smuzhiyun val &= ~FTM_SC_TOIE;
129*4882a593Smuzhiyun rtc_writel(rtc, FTM_SC, val);
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
ftm_reset_counter(struct ftm_rtc * rtc)132*4882a593Smuzhiyun static inline void ftm_reset_counter(struct ftm_rtc *rtc)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun /*
135*4882a593Smuzhiyun * The CNT register contains the FTM counter value.
136*4882a593Smuzhiyun * Reset clears the CNT register. Writing any value to COUNT
137*4882a593Smuzhiyun * updates the counter with its initial value, CNTIN.
138*4882a593Smuzhiyun */
139*4882a593Smuzhiyun rtc_writel(rtc, FTM_CNT, 0x00);
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
ftm_clean_alarm(struct ftm_rtc * rtc)142*4882a593Smuzhiyun static void ftm_clean_alarm(struct ftm_rtc *rtc)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun ftm_counter_disable(rtc);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun rtc_writel(rtc, FTM_CNTIN, 0x00);
147*4882a593Smuzhiyun rtc_writel(rtc, FTM_MOD, ~0U);
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun ftm_reset_counter(rtc);
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
ftm_rtc_alarm_interrupt(int irq,void * dev)152*4882a593Smuzhiyun static irqreturn_t ftm_rtc_alarm_interrupt(int irq, void *dev)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun struct ftm_rtc *rtc = dev;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun ftm_irq_acknowledge(rtc);
159*4882a593Smuzhiyun ftm_irq_disable(rtc);
160*4882a593Smuzhiyun ftm_clean_alarm(rtc);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun return IRQ_HANDLED;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
ftm_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)165*4882a593Smuzhiyun static int ftm_rtc_alarm_irq_enable(struct device *dev,
166*4882a593Smuzhiyun unsigned int enabled)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun struct ftm_rtc *rtc = dev_get_drvdata(dev);
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun if (enabled)
171*4882a593Smuzhiyun ftm_irq_enable(rtc);
172*4882a593Smuzhiyun else
173*4882a593Smuzhiyun ftm_irq_disable(rtc);
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun return 0;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun /*
179*4882a593Smuzhiyun * Note:
180*4882a593Smuzhiyun * The function is not really getting time from the RTC
181*4882a593Smuzhiyun * since FlexTimer is not a RTC device, but we need to
182*4882a593Smuzhiyun * get time to setup alarm, so we are using system time
183*4882a593Smuzhiyun * for now.
184*4882a593Smuzhiyun */
ftm_rtc_read_time(struct device * dev,struct rtc_time * tm)185*4882a593Smuzhiyun static int ftm_rtc_read_time(struct device *dev, struct rtc_time *tm)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun rtc_time64_to_tm(ktime_get_real_seconds(), tm);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun return 0;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
ftm_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alm)192*4882a593Smuzhiyun static int ftm_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun return 0;
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun /*
198*4882a593Smuzhiyun * 1. Select fixed frequency clock (32KHz) as clock source;
199*4882a593Smuzhiyun * 2. Select 128 (2^7) as divider factor;
200*4882a593Smuzhiyun * So clock is 250 Hz (32KHz/128).
201*4882a593Smuzhiyun *
202*4882a593Smuzhiyun * 3. FlexTimer's CNT register is a 32bit register,
203*4882a593Smuzhiyun * but the register's 16 bit as counter value,it's other 16 bit
204*4882a593Smuzhiyun * is reserved.So minimum counter value is 0x0,maximum counter
205*4882a593Smuzhiyun * value is 0xffff.
206*4882a593Smuzhiyun * So max alarm value is 262 (65536 / 250) seconds
207*4882a593Smuzhiyun */
ftm_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alm)208*4882a593Smuzhiyun static int ftm_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun time64_t alm_time;
211*4882a593Smuzhiyun unsigned long long cycle;
212*4882a593Smuzhiyun struct ftm_rtc *rtc = dev_get_drvdata(dev);
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun alm_time = rtc_tm_to_time64(&alm->time);
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun ftm_clean_alarm(rtc);
217*4882a593Smuzhiyun cycle = (alm_time - ktime_get_real_seconds()) * rtc->alarm_freq;
218*4882a593Smuzhiyun if (cycle > MAX_COUNT_VAL) {
219*4882a593Smuzhiyun pr_err("Out of alarm range {0~262} seconds.\n");
220*4882a593Smuzhiyun return -ERANGE;
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun ftm_irq_disable(rtc);
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun /*
226*4882a593Smuzhiyun * The counter increments until the value of MOD is reached,
227*4882a593Smuzhiyun * at which point the counter is reloaded with the value of CNTIN.
228*4882a593Smuzhiyun * The TOF (the overflow flag) bit is set when the FTM counter
229*4882a593Smuzhiyun * changes from MOD to CNTIN. So we should using the cycle - 1.
230*4882a593Smuzhiyun */
231*4882a593Smuzhiyun rtc_writel(rtc, FTM_MOD, cycle - 1);
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun ftm_counter_enable(rtc);
234*4882a593Smuzhiyun ftm_irq_enable(rtc);
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun return 0;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun static const struct rtc_class_ops ftm_rtc_ops = {
241*4882a593Smuzhiyun .read_time = ftm_rtc_read_time,
242*4882a593Smuzhiyun .read_alarm = ftm_rtc_read_alarm,
243*4882a593Smuzhiyun .set_alarm = ftm_rtc_set_alarm,
244*4882a593Smuzhiyun .alarm_irq_enable = ftm_rtc_alarm_irq_enable,
245*4882a593Smuzhiyun };
246*4882a593Smuzhiyun
ftm_rtc_probe(struct platform_device * pdev)247*4882a593Smuzhiyun static int ftm_rtc_probe(struct platform_device *pdev)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun int irq;
250*4882a593Smuzhiyun int ret;
251*4882a593Smuzhiyun struct ftm_rtc *rtc;
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
254*4882a593Smuzhiyun if (unlikely(!rtc)) {
255*4882a593Smuzhiyun dev_err(&pdev->dev, "cannot alloc memory for rtc\n");
256*4882a593Smuzhiyun return -ENOMEM;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun platform_set_drvdata(pdev, rtc);
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
262*4882a593Smuzhiyun if (IS_ERR(rtc->rtc_dev))
263*4882a593Smuzhiyun return PTR_ERR(rtc->rtc_dev);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun rtc->base = devm_platform_ioremap_resource(pdev, 0);
266*4882a593Smuzhiyun if (IS_ERR(rtc->base)) {
267*4882a593Smuzhiyun dev_err(&pdev->dev, "cannot ioremap resource for rtc\n");
268*4882a593Smuzhiyun return PTR_ERR(rtc->base);
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun irq = platform_get_irq(pdev, 0);
272*4882a593Smuzhiyun if (irq < 0)
273*4882a593Smuzhiyun return irq;
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun ret = devm_request_irq(&pdev->dev, irq, ftm_rtc_alarm_interrupt,
276*4882a593Smuzhiyun 0, dev_name(&pdev->dev), rtc);
277*4882a593Smuzhiyun if (ret < 0) {
278*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to request irq\n");
279*4882a593Smuzhiyun return ret;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun rtc->big_endian =
283*4882a593Smuzhiyun device_property_read_bool(&pdev->dev, "big-endian");
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun rtc->alarm_freq = (u32)FIXED_FREQ_CLK / (u32)MAX_FREQ_DIV;
286*4882a593Smuzhiyun rtc->rtc_dev->ops = &ftm_rtc_ops;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun device_init_wakeup(&pdev->dev, true);
289*4882a593Smuzhiyun ret = dev_pm_set_wake_irq(&pdev->dev, irq);
290*4882a593Smuzhiyun if (ret)
291*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to enable irq wake\n");
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun ret = rtc_register_device(rtc->rtc_dev);
294*4882a593Smuzhiyun if (ret) {
295*4882a593Smuzhiyun dev_err(&pdev->dev, "can't register rtc device\n");
296*4882a593Smuzhiyun return ret;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun return 0;
300*4882a593Smuzhiyun }
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun static const struct of_device_id ftm_rtc_match[] = {
303*4882a593Smuzhiyun { .compatible = "fsl,ls1012a-ftm-alarm", },
304*4882a593Smuzhiyun { .compatible = "fsl,ls1021a-ftm-alarm", },
305*4882a593Smuzhiyun { .compatible = "fsl,ls1028a-ftm-alarm", },
306*4882a593Smuzhiyun { .compatible = "fsl,ls1043a-ftm-alarm", },
307*4882a593Smuzhiyun { .compatible = "fsl,ls1046a-ftm-alarm", },
308*4882a593Smuzhiyun { .compatible = "fsl,ls1088a-ftm-alarm", },
309*4882a593Smuzhiyun { .compatible = "fsl,ls208xa-ftm-alarm", },
310*4882a593Smuzhiyun { .compatible = "fsl,lx2160a-ftm-alarm", },
311*4882a593Smuzhiyun { },
312*4882a593Smuzhiyun };
313*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ftm_rtc_match);
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun static const struct acpi_device_id ftm_imx_acpi_ids[] = {
316*4882a593Smuzhiyun {"NXP0014",},
317*4882a593Smuzhiyun { }
318*4882a593Smuzhiyun };
319*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, ftm_imx_acpi_ids);
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun static struct platform_driver ftm_rtc_driver = {
322*4882a593Smuzhiyun .probe = ftm_rtc_probe,
323*4882a593Smuzhiyun .driver = {
324*4882a593Smuzhiyun .name = "ftm-alarm",
325*4882a593Smuzhiyun .of_match_table = ftm_rtc_match,
326*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(ftm_imx_acpi_ids),
327*4882a593Smuzhiyun },
328*4882a593Smuzhiyun };
329*4882a593Smuzhiyun
ftm_alarm_init(void)330*4882a593Smuzhiyun static int __init ftm_alarm_init(void)
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun return platform_driver_register(&ftm_rtc_driver);
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun device_initcall(ftm_alarm_init);
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun MODULE_DESCRIPTION("NXP/Freescale FlexTimer alarm driver");
338*4882a593Smuzhiyun MODULE_AUTHOR("Biwen Li <biwen.li@nxp.com>");
339*4882a593Smuzhiyun MODULE_LICENSE("GPL");
340