1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * rtc-fm3130.c - RTC driver for Ramtron FM3130 I2C chip.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2008 Sergey Lapin
6*4882a593Smuzhiyun * Based on ds1307 driver by James Chapman and David Brownell
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/i2c.h>
11*4882a593Smuzhiyun #include <linux/rtc.h>
12*4882a593Smuzhiyun #include <linux/bcd.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define FM3130_RTC_CONTROL (0x0)
16*4882a593Smuzhiyun #define FM3130_CAL_CONTROL (0x1)
17*4882a593Smuzhiyun #define FM3130_RTC_SECONDS (0x2)
18*4882a593Smuzhiyun #define FM3130_RTC_MINUTES (0x3)
19*4882a593Smuzhiyun #define FM3130_RTC_HOURS (0x4)
20*4882a593Smuzhiyun #define FM3130_RTC_DAY (0x5)
21*4882a593Smuzhiyun #define FM3130_RTC_DATE (0x6)
22*4882a593Smuzhiyun #define FM3130_RTC_MONTHS (0x7)
23*4882a593Smuzhiyun #define FM3130_RTC_YEARS (0x8)
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define FM3130_ALARM_SECONDS (0x9)
26*4882a593Smuzhiyun #define FM3130_ALARM_MINUTES (0xa)
27*4882a593Smuzhiyun #define FM3130_ALARM_HOURS (0xb)
28*4882a593Smuzhiyun #define FM3130_ALARM_DATE (0xc)
29*4882a593Smuzhiyun #define FM3130_ALARM_MONTHS (0xd)
30*4882a593Smuzhiyun #define FM3130_ALARM_WP_CONTROL (0xe)
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define FM3130_CAL_CONTROL_BIT_nOSCEN (1 << 7) /* Osciallator enabled */
33*4882a593Smuzhiyun #define FM3130_RTC_CONTROL_BIT_LB (1 << 7) /* Low battery */
34*4882a593Smuzhiyun #define FM3130_RTC_CONTROL_BIT_AF (1 << 6) /* Alarm flag */
35*4882a593Smuzhiyun #define FM3130_RTC_CONTROL_BIT_CF (1 << 5) /* Century overflow */
36*4882a593Smuzhiyun #define FM3130_RTC_CONTROL_BIT_POR (1 << 4) /* Power on reset */
37*4882a593Smuzhiyun #define FM3130_RTC_CONTROL_BIT_AEN (1 << 3) /* Alarm enable */
38*4882a593Smuzhiyun #define FM3130_RTC_CONTROL_BIT_CAL (1 << 2) /* Calibration mode */
39*4882a593Smuzhiyun #define FM3130_RTC_CONTROL_BIT_WRITE (1 << 1) /* W=1 -> write mode W=0 normal */
40*4882a593Smuzhiyun #define FM3130_RTC_CONTROL_BIT_READ (1 << 0) /* R=1 -> read mode R=0 normal */
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define FM3130_CLOCK_REGS 7
43*4882a593Smuzhiyun #define FM3130_ALARM_REGS 5
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun struct fm3130 {
46*4882a593Smuzhiyun u8 reg_addr_time;
47*4882a593Smuzhiyun u8 reg_addr_alarm;
48*4882a593Smuzhiyun u8 regs[15];
49*4882a593Smuzhiyun struct i2c_msg msg[4];
50*4882a593Smuzhiyun struct i2c_client *client;
51*4882a593Smuzhiyun struct rtc_device *rtc;
52*4882a593Smuzhiyun int alarm_valid;
53*4882a593Smuzhiyun int data_valid;
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun static const struct i2c_device_id fm3130_id[] = {
56*4882a593Smuzhiyun { "fm3130", 0 },
57*4882a593Smuzhiyun { }
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, fm3130_id);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #define FM3130_MODE_NORMAL 0
62*4882a593Smuzhiyun #define FM3130_MODE_WRITE 1
63*4882a593Smuzhiyun #define FM3130_MODE_READ 2
64*4882a593Smuzhiyun
fm3130_rtc_mode(struct device * dev,int mode)65*4882a593Smuzhiyun static void fm3130_rtc_mode(struct device *dev, int mode)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun struct fm3130 *fm3130 = dev_get_drvdata(dev);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun fm3130->regs[FM3130_RTC_CONTROL] =
70*4882a593Smuzhiyun i2c_smbus_read_byte_data(fm3130->client, FM3130_RTC_CONTROL);
71*4882a593Smuzhiyun switch (mode) {
72*4882a593Smuzhiyun case FM3130_MODE_NORMAL:
73*4882a593Smuzhiyun fm3130->regs[FM3130_RTC_CONTROL] &=
74*4882a593Smuzhiyun ~(FM3130_RTC_CONTROL_BIT_WRITE |
75*4882a593Smuzhiyun FM3130_RTC_CONTROL_BIT_READ);
76*4882a593Smuzhiyun break;
77*4882a593Smuzhiyun case FM3130_MODE_WRITE:
78*4882a593Smuzhiyun fm3130->regs[FM3130_RTC_CONTROL] |= FM3130_RTC_CONTROL_BIT_WRITE;
79*4882a593Smuzhiyun break;
80*4882a593Smuzhiyun case FM3130_MODE_READ:
81*4882a593Smuzhiyun fm3130->regs[FM3130_RTC_CONTROL] |= FM3130_RTC_CONTROL_BIT_READ;
82*4882a593Smuzhiyun break;
83*4882a593Smuzhiyun default:
84*4882a593Smuzhiyun dev_dbg(dev, "invalid mode %d\n", mode);
85*4882a593Smuzhiyun break;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun i2c_smbus_write_byte_data(fm3130->client,
89*4882a593Smuzhiyun FM3130_RTC_CONTROL, fm3130->regs[FM3130_RTC_CONTROL]);
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
fm3130_get_time(struct device * dev,struct rtc_time * t)92*4882a593Smuzhiyun static int fm3130_get_time(struct device *dev, struct rtc_time *t)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun struct fm3130 *fm3130 = dev_get_drvdata(dev);
95*4882a593Smuzhiyun int tmp;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun if (!fm3130->data_valid) {
98*4882a593Smuzhiyun /* We have invalid data in RTC, probably due
99*4882a593Smuzhiyun to battery faults or other problems. Return EIO
100*4882a593Smuzhiyun for now, it will allow us to set data later instead
101*4882a593Smuzhiyun of error during probing which disables device */
102*4882a593Smuzhiyun return -EIO;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun fm3130_rtc_mode(dev, FM3130_MODE_READ);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /* read the RTC date and time registers all at once */
107*4882a593Smuzhiyun tmp = i2c_transfer(fm3130->client->adapter, fm3130->msg, 2);
108*4882a593Smuzhiyun if (tmp != 2) {
109*4882a593Smuzhiyun dev_err(dev, "%s error %d\n", "read", tmp);
110*4882a593Smuzhiyun return -EIO;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun fm3130_rtc_mode(dev, FM3130_MODE_NORMAL);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun dev_dbg(dev, "%s: %15ph\n", "read", fm3130->regs);
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun t->tm_sec = bcd2bin(fm3130->regs[FM3130_RTC_SECONDS] & 0x7f);
118*4882a593Smuzhiyun t->tm_min = bcd2bin(fm3130->regs[FM3130_RTC_MINUTES] & 0x7f);
119*4882a593Smuzhiyun tmp = fm3130->regs[FM3130_RTC_HOURS] & 0x3f;
120*4882a593Smuzhiyun t->tm_hour = bcd2bin(tmp);
121*4882a593Smuzhiyun t->tm_wday = bcd2bin(fm3130->regs[FM3130_RTC_DAY] & 0x07) - 1;
122*4882a593Smuzhiyun t->tm_mday = bcd2bin(fm3130->regs[FM3130_RTC_DATE] & 0x3f);
123*4882a593Smuzhiyun tmp = fm3130->regs[FM3130_RTC_MONTHS] & 0x1f;
124*4882a593Smuzhiyun t->tm_mon = bcd2bin(tmp) - 1;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun /* assume 20YY not 19YY, and ignore CF bit */
127*4882a593Smuzhiyun t->tm_year = bcd2bin(fm3130->regs[FM3130_RTC_YEARS]) + 100;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun dev_dbg(dev, "%s secs=%d, mins=%d, "
130*4882a593Smuzhiyun "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
131*4882a593Smuzhiyun "read", t->tm_sec, t->tm_min,
132*4882a593Smuzhiyun t->tm_hour, t->tm_mday,
133*4882a593Smuzhiyun t->tm_mon, t->tm_year, t->tm_wday);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun return 0;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun
fm3130_set_time(struct device * dev,struct rtc_time * t)139*4882a593Smuzhiyun static int fm3130_set_time(struct device *dev, struct rtc_time *t)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun struct fm3130 *fm3130 = dev_get_drvdata(dev);
142*4882a593Smuzhiyun int tmp, i;
143*4882a593Smuzhiyun u8 *buf = fm3130->regs;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun dev_dbg(dev, "%s secs=%d, mins=%d, "
146*4882a593Smuzhiyun "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
147*4882a593Smuzhiyun "write", t->tm_sec, t->tm_min,
148*4882a593Smuzhiyun t->tm_hour, t->tm_mday,
149*4882a593Smuzhiyun t->tm_mon, t->tm_year, t->tm_wday);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun /* first register addr */
152*4882a593Smuzhiyun buf[FM3130_RTC_SECONDS] = bin2bcd(t->tm_sec);
153*4882a593Smuzhiyun buf[FM3130_RTC_MINUTES] = bin2bcd(t->tm_min);
154*4882a593Smuzhiyun buf[FM3130_RTC_HOURS] = bin2bcd(t->tm_hour);
155*4882a593Smuzhiyun buf[FM3130_RTC_DAY] = bin2bcd(t->tm_wday + 1);
156*4882a593Smuzhiyun buf[FM3130_RTC_DATE] = bin2bcd(t->tm_mday);
157*4882a593Smuzhiyun buf[FM3130_RTC_MONTHS] = bin2bcd(t->tm_mon + 1);
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun /* assume 20YY not 19YY */
160*4882a593Smuzhiyun tmp = t->tm_year - 100;
161*4882a593Smuzhiyun buf[FM3130_RTC_YEARS] = bin2bcd(tmp);
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun dev_dbg(dev, "%s: %15ph\n", "write", buf);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun fm3130_rtc_mode(dev, FM3130_MODE_WRITE);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun /* Writing time registers, we don't support multibyte transfers */
168*4882a593Smuzhiyun for (i = 0; i < FM3130_CLOCK_REGS; i++) {
169*4882a593Smuzhiyun i2c_smbus_write_byte_data(fm3130->client,
170*4882a593Smuzhiyun FM3130_RTC_SECONDS + i,
171*4882a593Smuzhiyun fm3130->regs[FM3130_RTC_SECONDS + i]);
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun fm3130_rtc_mode(dev, FM3130_MODE_NORMAL);
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun /* We assume here that data are valid once written */
177*4882a593Smuzhiyun if (!fm3130->data_valid)
178*4882a593Smuzhiyun fm3130->data_valid = 1;
179*4882a593Smuzhiyun return 0;
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun
fm3130_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)182*4882a593Smuzhiyun static int fm3130_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun struct fm3130 *fm3130 = dev_get_drvdata(dev);
185*4882a593Smuzhiyun int tmp;
186*4882a593Smuzhiyun struct rtc_time *tm = &alrm->time;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun if (!fm3130->alarm_valid) {
189*4882a593Smuzhiyun /*
190*4882a593Smuzhiyun * We have invalid alarm in RTC, probably due to battery faults
191*4882a593Smuzhiyun * or other problems. Return EIO for now, it will allow us to
192*4882a593Smuzhiyun * set alarm value later instead of error during probing which
193*4882a593Smuzhiyun * disables device
194*4882a593Smuzhiyun */
195*4882a593Smuzhiyun return -EIO;
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun /* read the RTC alarm registers all at once */
199*4882a593Smuzhiyun tmp = i2c_transfer(fm3130->client->adapter, &fm3130->msg[2], 2);
200*4882a593Smuzhiyun if (tmp != 2) {
201*4882a593Smuzhiyun dev_err(dev, "%s error %d\n", "read", tmp);
202*4882a593Smuzhiyun return -EIO;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun dev_dbg(dev, "alarm read %02x %02x %02x %02x %02x\n",
205*4882a593Smuzhiyun fm3130->regs[FM3130_ALARM_SECONDS],
206*4882a593Smuzhiyun fm3130->regs[FM3130_ALARM_MINUTES],
207*4882a593Smuzhiyun fm3130->regs[FM3130_ALARM_HOURS],
208*4882a593Smuzhiyun fm3130->regs[FM3130_ALARM_DATE],
209*4882a593Smuzhiyun fm3130->regs[FM3130_ALARM_MONTHS]);
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun tm->tm_sec = bcd2bin(fm3130->regs[FM3130_ALARM_SECONDS] & 0x7F);
212*4882a593Smuzhiyun tm->tm_min = bcd2bin(fm3130->regs[FM3130_ALARM_MINUTES] & 0x7F);
213*4882a593Smuzhiyun tm->tm_hour = bcd2bin(fm3130->regs[FM3130_ALARM_HOURS] & 0x3F);
214*4882a593Smuzhiyun tm->tm_mday = bcd2bin(fm3130->regs[FM3130_ALARM_DATE] & 0x3F);
215*4882a593Smuzhiyun tm->tm_mon = bcd2bin(fm3130->regs[FM3130_ALARM_MONTHS] & 0x1F);
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun if (tm->tm_mon > 0)
218*4882a593Smuzhiyun tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun dev_dbg(dev, "%s secs=%d, mins=%d, "
221*4882a593Smuzhiyun "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
222*4882a593Smuzhiyun "read alarm", tm->tm_sec, tm->tm_min,
223*4882a593Smuzhiyun tm->tm_hour, tm->tm_mday,
224*4882a593Smuzhiyun tm->tm_mon, tm->tm_year, tm->tm_wday);
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun /* check if alarm enabled */
227*4882a593Smuzhiyun fm3130->regs[FM3130_RTC_CONTROL] =
228*4882a593Smuzhiyun i2c_smbus_read_byte_data(fm3130->client, FM3130_RTC_CONTROL);
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun if ((fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_AEN) &&
231*4882a593Smuzhiyun (~fm3130->regs[FM3130_RTC_CONTROL] &
232*4882a593Smuzhiyun FM3130_RTC_CONTROL_BIT_CAL)) {
233*4882a593Smuzhiyun alrm->enabled = 1;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun return 0;
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun
fm3130_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)239*4882a593Smuzhiyun static int fm3130_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
240*4882a593Smuzhiyun {
241*4882a593Smuzhiyun struct fm3130 *fm3130 = dev_get_drvdata(dev);
242*4882a593Smuzhiyun struct rtc_time *tm = &alrm->time;
243*4882a593Smuzhiyun int i;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun dev_dbg(dev, "%s secs=%d, mins=%d, "
246*4882a593Smuzhiyun "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
247*4882a593Smuzhiyun "write alarm", tm->tm_sec, tm->tm_min,
248*4882a593Smuzhiyun tm->tm_hour, tm->tm_mday,
249*4882a593Smuzhiyun tm->tm_mon, tm->tm_year, tm->tm_wday);
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun fm3130->regs[FM3130_ALARM_SECONDS] =
252*4882a593Smuzhiyun (tm->tm_sec != -1) ? bin2bcd(tm->tm_sec) : 0x80;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun fm3130->regs[FM3130_ALARM_MINUTES] =
255*4882a593Smuzhiyun (tm->tm_min != -1) ? bin2bcd(tm->tm_min) : 0x80;
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun fm3130->regs[FM3130_ALARM_HOURS] =
258*4882a593Smuzhiyun (tm->tm_hour != -1) ? bin2bcd(tm->tm_hour) : 0x80;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun fm3130->regs[FM3130_ALARM_DATE] =
261*4882a593Smuzhiyun (tm->tm_mday != -1) ? bin2bcd(tm->tm_mday) : 0x80;
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun fm3130->regs[FM3130_ALARM_MONTHS] =
264*4882a593Smuzhiyun (tm->tm_mon != -1) ? bin2bcd(tm->tm_mon + 1) : 0x80;
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun dev_dbg(dev, "alarm write %02x %02x %02x %02x %02x\n",
267*4882a593Smuzhiyun fm3130->regs[FM3130_ALARM_SECONDS],
268*4882a593Smuzhiyun fm3130->regs[FM3130_ALARM_MINUTES],
269*4882a593Smuzhiyun fm3130->regs[FM3130_ALARM_HOURS],
270*4882a593Smuzhiyun fm3130->regs[FM3130_ALARM_DATE],
271*4882a593Smuzhiyun fm3130->regs[FM3130_ALARM_MONTHS]);
272*4882a593Smuzhiyun /* Writing time registers, we don't support multibyte transfers */
273*4882a593Smuzhiyun for (i = 0; i < FM3130_ALARM_REGS; i++) {
274*4882a593Smuzhiyun i2c_smbus_write_byte_data(fm3130->client,
275*4882a593Smuzhiyun FM3130_ALARM_SECONDS + i,
276*4882a593Smuzhiyun fm3130->regs[FM3130_ALARM_SECONDS + i]);
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun fm3130->regs[FM3130_RTC_CONTROL] =
279*4882a593Smuzhiyun i2c_smbus_read_byte_data(fm3130->client, FM3130_RTC_CONTROL);
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun /* enable or disable alarm */
282*4882a593Smuzhiyun if (alrm->enabled) {
283*4882a593Smuzhiyun i2c_smbus_write_byte_data(fm3130->client, FM3130_RTC_CONTROL,
284*4882a593Smuzhiyun (fm3130->regs[FM3130_RTC_CONTROL] &
285*4882a593Smuzhiyun ~(FM3130_RTC_CONTROL_BIT_CAL)) |
286*4882a593Smuzhiyun FM3130_RTC_CONTROL_BIT_AEN);
287*4882a593Smuzhiyun } else {
288*4882a593Smuzhiyun i2c_smbus_write_byte_data(fm3130->client, FM3130_RTC_CONTROL,
289*4882a593Smuzhiyun fm3130->regs[FM3130_RTC_CONTROL] &
290*4882a593Smuzhiyun ~(FM3130_RTC_CONTROL_BIT_CAL) &
291*4882a593Smuzhiyun ~(FM3130_RTC_CONTROL_BIT_AEN));
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun /* We assume here that data is valid once written */
295*4882a593Smuzhiyun if (!fm3130->alarm_valid)
296*4882a593Smuzhiyun fm3130->alarm_valid = 1;
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun return 0;
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun
fm3130_alarm_irq_enable(struct device * dev,unsigned int enabled)301*4882a593Smuzhiyun static int fm3130_alarm_irq_enable(struct device *dev, unsigned int enabled)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun struct fm3130 *fm3130 = dev_get_drvdata(dev);
304*4882a593Smuzhiyun int ret = 0;
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun fm3130->regs[FM3130_RTC_CONTROL] =
307*4882a593Smuzhiyun i2c_smbus_read_byte_data(fm3130->client, FM3130_RTC_CONTROL);
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun dev_dbg(dev, "alarm_irq_enable: enable=%d, FM3130_RTC_CONTROL=%02x\n",
310*4882a593Smuzhiyun enabled, fm3130->regs[FM3130_RTC_CONTROL]);
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun switch (enabled) {
313*4882a593Smuzhiyun case 0: /* alarm off */
314*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(fm3130->client,
315*4882a593Smuzhiyun FM3130_RTC_CONTROL, fm3130->regs[FM3130_RTC_CONTROL] &
316*4882a593Smuzhiyun ~(FM3130_RTC_CONTROL_BIT_CAL) &
317*4882a593Smuzhiyun ~(FM3130_RTC_CONTROL_BIT_AEN));
318*4882a593Smuzhiyun break;
319*4882a593Smuzhiyun case 1: /* alarm on */
320*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(fm3130->client,
321*4882a593Smuzhiyun FM3130_RTC_CONTROL, (fm3130->regs[FM3130_RTC_CONTROL] &
322*4882a593Smuzhiyun ~(FM3130_RTC_CONTROL_BIT_CAL)) |
323*4882a593Smuzhiyun FM3130_RTC_CONTROL_BIT_AEN);
324*4882a593Smuzhiyun break;
325*4882a593Smuzhiyun default:
326*4882a593Smuzhiyun ret = -EINVAL;
327*4882a593Smuzhiyun break;
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun return ret;
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun static const struct rtc_class_ops fm3130_rtc_ops = {
334*4882a593Smuzhiyun .read_time = fm3130_get_time,
335*4882a593Smuzhiyun .set_time = fm3130_set_time,
336*4882a593Smuzhiyun .read_alarm = fm3130_read_alarm,
337*4882a593Smuzhiyun .set_alarm = fm3130_set_alarm,
338*4882a593Smuzhiyun .alarm_irq_enable = fm3130_alarm_irq_enable,
339*4882a593Smuzhiyun };
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun static struct i2c_driver fm3130_driver;
342*4882a593Smuzhiyun
fm3130_probe(struct i2c_client * client,const struct i2c_device_id * id)343*4882a593Smuzhiyun static int fm3130_probe(struct i2c_client *client,
344*4882a593Smuzhiyun const struct i2c_device_id *id)
345*4882a593Smuzhiyun {
346*4882a593Smuzhiyun struct fm3130 *fm3130;
347*4882a593Smuzhiyun int err = -ENODEV;
348*4882a593Smuzhiyun int tmp;
349*4882a593Smuzhiyun struct i2c_adapter *adapter = client->adapter;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun if (!i2c_check_functionality(adapter,
352*4882a593Smuzhiyun I2C_FUNC_I2C | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
353*4882a593Smuzhiyun return -EIO;
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun fm3130 = devm_kzalloc(&client->dev, sizeof(struct fm3130), GFP_KERNEL);
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun if (!fm3130)
358*4882a593Smuzhiyun return -ENOMEM;
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun fm3130->client = client;
361*4882a593Smuzhiyun i2c_set_clientdata(client, fm3130);
362*4882a593Smuzhiyun fm3130->reg_addr_time = FM3130_RTC_SECONDS;
363*4882a593Smuzhiyun fm3130->reg_addr_alarm = FM3130_ALARM_SECONDS;
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun /* Messages to read time */
366*4882a593Smuzhiyun fm3130->msg[0].addr = client->addr;
367*4882a593Smuzhiyun fm3130->msg[0].flags = 0;
368*4882a593Smuzhiyun fm3130->msg[0].len = 1;
369*4882a593Smuzhiyun fm3130->msg[0].buf = &fm3130->reg_addr_time;
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun fm3130->msg[1].addr = client->addr;
372*4882a593Smuzhiyun fm3130->msg[1].flags = I2C_M_RD;
373*4882a593Smuzhiyun fm3130->msg[1].len = FM3130_CLOCK_REGS;
374*4882a593Smuzhiyun fm3130->msg[1].buf = &fm3130->regs[FM3130_RTC_SECONDS];
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun /* Messages to read alarm */
377*4882a593Smuzhiyun fm3130->msg[2].addr = client->addr;
378*4882a593Smuzhiyun fm3130->msg[2].flags = 0;
379*4882a593Smuzhiyun fm3130->msg[2].len = 1;
380*4882a593Smuzhiyun fm3130->msg[2].buf = &fm3130->reg_addr_alarm;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun fm3130->msg[3].addr = client->addr;
383*4882a593Smuzhiyun fm3130->msg[3].flags = I2C_M_RD;
384*4882a593Smuzhiyun fm3130->msg[3].len = FM3130_ALARM_REGS;
385*4882a593Smuzhiyun fm3130->msg[3].buf = &fm3130->regs[FM3130_ALARM_SECONDS];
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun fm3130->alarm_valid = 0;
388*4882a593Smuzhiyun fm3130->data_valid = 0;
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun tmp = i2c_transfer(adapter, fm3130->msg, 4);
391*4882a593Smuzhiyun if (tmp != 4) {
392*4882a593Smuzhiyun dev_dbg(&client->dev, "read error %d\n", tmp);
393*4882a593Smuzhiyun err = -EIO;
394*4882a593Smuzhiyun goto exit_free;
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun fm3130->regs[FM3130_RTC_CONTROL] =
398*4882a593Smuzhiyun i2c_smbus_read_byte_data(client, FM3130_RTC_CONTROL);
399*4882a593Smuzhiyun fm3130->regs[FM3130_CAL_CONTROL] =
400*4882a593Smuzhiyun i2c_smbus_read_byte_data(client, FM3130_CAL_CONTROL);
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun /* Disabling calibration mode */
403*4882a593Smuzhiyun if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_CAL) {
404*4882a593Smuzhiyun i2c_smbus_write_byte_data(client, FM3130_RTC_CONTROL,
405*4882a593Smuzhiyun fm3130->regs[FM3130_RTC_CONTROL] &
406*4882a593Smuzhiyun ~(FM3130_RTC_CONTROL_BIT_CAL));
407*4882a593Smuzhiyun dev_warn(&client->dev, "Disabling calibration mode!\n");
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun /* Disabling read and write modes */
411*4882a593Smuzhiyun if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_WRITE ||
412*4882a593Smuzhiyun fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_READ) {
413*4882a593Smuzhiyun i2c_smbus_write_byte_data(client, FM3130_RTC_CONTROL,
414*4882a593Smuzhiyun fm3130->regs[FM3130_RTC_CONTROL] &
415*4882a593Smuzhiyun ~(FM3130_RTC_CONTROL_BIT_READ |
416*4882a593Smuzhiyun FM3130_RTC_CONTROL_BIT_WRITE));
417*4882a593Smuzhiyun dev_warn(&client->dev, "Disabling READ or WRITE mode!\n");
418*4882a593Smuzhiyun }
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun /* oscillator off? turn it on, so clock can tick. */
421*4882a593Smuzhiyun if (fm3130->regs[FM3130_CAL_CONTROL] & FM3130_CAL_CONTROL_BIT_nOSCEN)
422*4882a593Smuzhiyun i2c_smbus_write_byte_data(client, FM3130_CAL_CONTROL,
423*4882a593Smuzhiyun fm3130->regs[FM3130_CAL_CONTROL] &
424*4882a593Smuzhiyun ~(FM3130_CAL_CONTROL_BIT_nOSCEN));
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun /* low battery? clear flag, and warn */
427*4882a593Smuzhiyun if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_LB) {
428*4882a593Smuzhiyun i2c_smbus_write_byte_data(client, FM3130_RTC_CONTROL,
429*4882a593Smuzhiyun fm3130->regs[FM3130_RTC_CONTROL] &
430*4882a593Smuzhiyun ~(FM3130_RTC_CONTROL_BIT_LB));
431*4882a593Smuzhiyun dev_warn(&client->dev, "Low battery!\n");
432*4882a593Smuzhiyun }
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun /* check if Power On Reset bit is set */
435*4882a593Smuzhiyun if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_POR) {
436*4882a593Smuzhiyun i2c_smbus_write_byte_data(client, FM3130_RTC_CONTROL,
437*4882a593Smuzhiyun fm3130->regs[FM3130_RTC_CONTROL] &
438*4882a593Smuzhiyun ~FM3130_RTC_CONTROL_BIT_POR);
439*4882a593Smuzhiyun dev_dbg(&client->dev, "POR bit is set\n");
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun /* ACS is controlled by alarm */
442*4882a593Smuzhiyun i2c_smbus_write_byte_data(client, FM3130_ALARM_WP_CONTROL, 0x80);
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun /* alarm registers sanity check */
445*4882a593Smuzhiyun tmp = bcd2bin(fm3130->regs[FM3130_RTC_SECONDS] & 0x7f);
446*4882a593Smuzhiyun if (tmp > 59)
447*4882a593Smuzhiyun goto bad_alarm;
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun tmp = bcd2bin(fm3130->regs[FM3130_RTC_MINUTES] & 0x7f);
450*4882a593Smuzhiyun if (tmp > 59)
451*4882a593Smuzhiyun goto bad_alarm;
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun tmp = bcd2bin(fm3130->regs[FM3130_RTC_HOURS] & 0x3f);
454*4882a593Smuzhiyun if (tmp > 23)
455*4882a593Smuzhiyun goto bad_alarm;
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun tmp = bcd2bin(fm3130->regs[FM3130_RTC_DATE] & 0x3f);
458*4882a593Smuzhiyun if (tmp == 0 || tmp > 31)
459*4882a593Smuzhiyun goto bad_alarm;
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun tmp = bcd2bin(fm3130->regs[FM3130_RTC_MONTHS] & 0x1f);
462*4882a593Smuzhiyun if (tmp == 0 || tmp > 12)
463*4882a593Smuzhiyun goto bad_alarm;
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun fm3130->alarm_valid = 1;
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun bad_alarm:
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun /* clock registers sanity chek */
470*4882a593Smuzhiyun tmp = bcd2bin(fm3130->regs[FM3130_RTC_SECONDS] & 0x7f);
471*4882a593Smuzhiyun if (tmp > 59)
472*4882a593Smuzhiyun goto bad_clock;
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun tmp = bcd2bin(fm3130->regs[FM3130_RTC_MINUTES] & 0x7f);
475*4882a593Smuzhiyun if (tmp > 59)
476*4882a593Smuzhiyun goto bad_clock;
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun tmp = bcd2bin(fm3130->regs[FM3130_RTC_HOURS] & 0x3f);
479*4882a593Smuzhiyun if (tmp > 23)
480*4882a593Smuzhiyun goto bad_clock;
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun tmp = bcd2bin(fm3130->regs[FM3130_RTC_DAY] & 0x7);
483*4882a593Smuzhiyun if (tmp == 0 || tmp > 7)
484*4882a593Smuzhiyun goto bad_clock;
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun tmp = bcd2bin(fm3130->regs[FM3130_RTC_DATE] & 0x3f);
487*4882a593Smuzhiyun if (tmp == 0 || tmp > 31)
488*4882a593Smuzhiyun goto bad_clock;
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun tmp = bcd2bin(fm3130->regs[FM3130_RTC_MONTHS] & 0x1f);
491*4882a593Smuzhiyun if (tmp == 0 || tmp > 12)
492*4882a593Smuzhiyun goto bad_clock;
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun fm3130->data_valid = 1;
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun bad_clock:
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun if (!fm3130->data_valid || !fm3130->alarm_valid)
499*4882a593Smuzhiyun dev_dbg(&client->dev, "%s: %15ph\n", "bogus registers",
500*4882a593Smuzhiyun fm3130->regs);
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun /* We won't bail out here because we just got invalid data.
503*4882a593Smuzhiyun Time setting from u-boot doesn't work anyway */
504*4882a593Smuzhiyun fm3130->rtc = devm_rtc_device_register(&client->dev, client->name,
505*4882a593Smuzhiyun &fm3130_rtc_ops, THIS_MODULE);
506*4882a593Smuzhiyun if (IS_ERR(fm3130->rtc)) {
507*4882a593Smuzhiyun err = PTR_ERR(fm3130->rtc);
508*4882a593Smuzhiyun dev_err(&client->dev,
509*4882a593Smuzhiyun "unable to register the class device\n");
510*4882a593Smuzhiyun goto exit_free;
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun return 0;
513*4882a593Smuzhiyun exit_free:
514*4882a593Smuzhiyun return err;
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun static struct i2c_driver fm3130_driver = {
518*4882a593Smuzhiyun .driver = {
519*4882a593Smuzhiyun .name = "rtc-fm3130",
520*4882a593Smuzhiyun },
521*4882a593Smuzhiyun .probe = fm3130_probe,
522*4882a593Smuzhiyun .id_table = fm3130_id,
523*4882a593Smuzhiyun };
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun module_i2c_driver(fm3130_driver);
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun MODULE_DESCRIPTION("RTC driver for FM3130");
528*4882a593Smuzhiyun MODULE_AUTHOR("Sergey Lapin <slapin@ossfans.org>");
529*4882a593Smuzhiyun MODULE_LICENSE("GPL");
530*4882a593Smuzhiyun
531