xref: /OK3568_Linux_fs/kernel/drivers/rtc/rtc-ds1511.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * An rtc driver for the Dallas DS1511
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2006 Atsushi Nemoto <anemo@mba.ocn.ne.jp>
6*4882a593Smuzhiyun  * Copyright (C) 2007 Andrew Sharp <andy.sharp@lsi.com>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Real time clock driver for the Dallas 1511 chip, which also
9*4882a593Smuzhiyun  * contains a watchdog timer.  There is a tiny amount of code that
10*4882a593Smuzhiyun  * platform code could use to mess with the watchdog device a little
11*4882a593Smuzhiyun  * bit, but not a full watchdog driver.
12*4882a593Smuzhiyun  */
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <linux/bcd.h>
15*4882a593Smuzhiyun #include <linux/init.h>
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/gfp.h>
18*4882a593Smuzhiyun #include <linux/delay.h>
19*4882a593Smuzhiyun #include <linux/interrupt.h>
20*4882a593Smuzhiyun #include <linux/rtc.h>
21*4882a593Smuzhiyun #include <linux/platform_device.h>
22*4882a593Smuzhiyun #include <linux/io.h>
23*4882a593Smuzhiyun #include <linux/module.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun enum ds1511reg {
26*4882a593Smuzhiyun 	DS1511_SEC = 0x0,
27*4882a593Smuzhiyun 	DS1511_MIN = 0x1,
28*4882a593Smuzhiyun 	DS1511_HOUR = 0x2,
29*4882a593Smuzhiyun 	DS1511_DOW = 0x3,
30*4882a593Smuzhiyun 	DS1511_DOM = 0x4,
31*4882a593Smuzhiyun 	DS1511_MONTH = 0x5,
32*4882a593Smuzhiyun 	DS1511_YEAR = 0x6,
33*4882a593Smuzhiyun 	DS1511_CENTURY = 0x7,
34*4882a593Smuzhiyun 	DS1511_AM1_SEC = 0x8,
35*4882a593Smuzhiyun 	DS1511_AM2_MIN = 0x9,
36*4882a593Smuzhiyun 	DS1511_AM3_HOUR = 0xa,
37*4882a593Smuzhiyun 	DS1511_AM4_DATE = 0xb,
38*4882a593Smuzhiyun 	DS1511_WD_MSEC = 0xc,
39*4882a593Smuzhiyun 	DS1511_WD_SEC = 0xd,
40*4882a593Smuzhiyun 	DS1511_CONTROL_A = 0xe,
41*4882a593Smuzhiyun 	DS1511_CONTROL_B = 0xf,
42*4882a593Smuzhiyun 	DS1511_RAMADDR_LSB = 0x10,
43*4882a593Smuzhiyun 	DS1511_RAMDATA = 0x13
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun #define DS1511_BLF1	0x80
47*4882a593Smuzhiyun #define DS1511_BLF2	0x40
48*4882a593Smuzhiyun #define DS1511_PRS	0x20
49*4882a593Smuzhiyun #define DS1511_PAB	0x10
50*4882a593Smuzhiyun #define DS1511_TDF	0x08
51*4882a593Smuzhiyun #define DS1511_KSF	0x04
52*4882a593Smuzhiyun #define DS1511_WDF	0x02
53*4882a593Smuzhiyun #define DS1511_IRQF	0x01
54*4882a593Smuzhiyun #define DS1511_TE	0x80
55*4882a593Smuzhiyun #define DS1511_CS	0x40
56*4882a593Smuzhiyun #define DS1511_BME	0x20
57*4882a593Smuzhiyun #define DS1511_TPE	0x10
58*4882a593Smuzhiyun #define DS1511_TIE	0x08
59*4882a593Smuzhiyun #define DS1511_KIE	0x04
60*4882a593Smuzhiyun #define DS1511_WDE	0x02
61*4882a593Smuzhiyun #define DS1511_WDS	0x01
62*4882a593Smuzhiyun #define DS1511_RAM_MAX	0x100
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #define RTC_CMD		DS1511_CONTROL_B
65*4882a593Smuzhiyun #define RTC_CMD1	DS1511_CONTROL_A
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun #define RTC_ALARM_SEC	DS1511_AM1_SEC
68*4882a593Smuzhiyun #define RTC_ALARM_MIN	DS1511_AM2_MIN
69*4882a593Smuzhiyun #define RTC_ALARM_HOUR	DS1511_AM3_HOUR
70*4882a593Smuzhiyun #define RTC_ALARM_DATE	DS1511_AM4_DATE
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun #define RTC_SEC		DS1511_SEC
73*4882a593Smuzhiyun #define RTC_MIN		DS1511_MIN
74*4882a593Smuzhiyun #define RTC_HOUR	DS1511_HOUR
75*4882a593Smuzhiyun #define RTC_DOW		DS1511_DOW
76*4882a593Smuzhiyun #define RTC_DOM		DS1511_DOM
77*4882a593Smuzhiyun #define RTC_MON		DS1511_MONTH
78*4882a593Smuzhiyun #define RTC_YEAR	DS1511_YEAR
79*4882a593Smuzhiyun #define RTC_CENTURY	DS1511_CENTURY
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun #define RTC_TIE	DS1511_TIE
82*4882a593Smuzhiyun #define RTC_TE	DS1511_TE
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun struct rtc_plat_data {
85*4882a593Smuzhiyun 	struct rtc_device *rtc;
86*4882a593Smuzhiyun 	void __iomem *ioaddr;		/* virtual base address */
87*4882a593Smuzhiyun 	int irq;
88*4882a593Smuzhiyun 	unsigned int irqen;
89*4882a593Smuzhiyun 	int alrm_sec;
90*4882a593Smuzhiyun 	int alrm_min;
91*4882a593Smuzhiyun 	int alrm_hour;
92*4882a593Smuzhiyun 	int alrm_mday;
93*4882a593Smuzhiyun 	spinlock_t lock;
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun static DEFINE_SPINLOCK(ds1511_lock);
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun static __iomem char *ds1511_base;
99*4882a593Smuzhiyun static u32 reg_spacing = 1;
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun static noinline void
rtc_write(uint8_t val,uint32_t reg)102*4882a593Smuzhiyun rtc_write(uint8_t val, uint32_t reg)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun 	writeb(val, ds1511_base + (reg * reg_spacing));
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun static inline void
rtc_write_alarm(uint8_t val,enum ds1511reg reg)108*4882a593Smuzhiyun rtc_write_alarm(uint8_t val, enum ds1511reg reg)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun 	rtc_write((val | 0x80), reg);
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun static noinline uint8_t
rtc_read(enum ds1511reg reg)114*4882a593Smuzhiyun rtc_read(enum ds1511reg reg)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun 	return readb(ds1511_base + (reg * reg_spacing));
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun static inline void
rtc_disable_update(void)120*4882a593Smuzhiyun rtc_disable_update(void)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun 	rtc_write((rtc_read(RTC_CMD) & ~RTC_TE), RTC_CMD);
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun static void
rtc_enable_update(void)126*4882a593Smuzhiyun rtc_enable_update(void)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun 	rtc_write((rtc_read(RTC_CMD) | RTC_TE), RTC_CMD);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun /*
132*4882a593Smuzhiyun  * #define DS1511_WDOG_RESET_SUPPORT
133*4882a593Smuzhiyun  *
134*4882a593Smuzhiyun  * Uncomment this if you want to use these routines in
135*4882a593Smuzhiyun  * some platform code.
136*4882a593Smuzhiyun  */
137*4882a593Smuzhiyun #ifdef DS1511_WDOG_RESET_SUPPORT
138*4882a593Smuzhiyun /*
139*4882a593Smuzhiyun  * just enough code to set the watchdog timer so that it
140*4882a593Smuzhiyun  * will reboot the system
141*4882a593Smuzhiyun  */
142*4882a593Smuzhiyun void
ds1511_wdog_set(unsigned long deciseconds)143*4882a593Smuzhiyun ds1511_wdog_set(unsigned long deciseconds)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun 	/*
146*4882a593Smuzhiyun 	 * the wdog timer can take 99.99 seconds
147*4882a593Smuzhiyun 	 */
148*4882a593Smuzhiyun 	deciseconds %= 10000;
149*4882a593Smuzhiyun 	/*
150*4882a593Smuzhiyun 	 * set the wdog values in the wdog registers
151*4882a593Smuzhiyun 	 */
152*4882a593Smuzhiyun 	rtc_write(bin2bcd(deciseconds % 100), DS1511_WD_MSEC);
153*4882a593Smuzhiyun 	rtc_write(bin2bcd(deciseconds / 100), DS1511_WD_SEC);
154*4882a593Smuzhiyun 	/*
155*4882a593Smuzhiyun 	 * set wdog enable and wdog 'steering' bit to issue a reset
156*4882a593Smuzhiyun 	 */
157*4882a593Smuzhiyun 	rtc_write(rtc_read(RTC_CMD) | DS1511_WDE | DS1511_WDS, RTC_CMD);
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun void
ds1511_wdog_disable(void)161*4882a593Smuzhiyun ds1511_wdog_disable(void)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun 	/*
164*4882a593Smuzhiyun 	 * clear wdog enable and wdog 'steering' bits
165*4882a593Smuzhiyun 	 */
166*4882a593Smuzhiyun 	rtc_write(rtc_read(RTC_CMD) & ~(DS1511_WDE | DS1511_WDS), RTC_CMD);
167*4882a593Smuzhiyun 	/*
168*4882a593Smuzhiyun 	 * clear the wdog counter
169*4882a593Smuzhiyun 	 */
170*4882a593Smuzhiyun 	rtc_write(0, DS1511_WD_MSEC);
171*4882a593Smuzhiyun 	rtc_write(0, DS1511_WD_SEC);
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun #endif
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun /*
176*4882a593Smuzhiyun  * set the rtc chip's idea of the time.
177*4882a593Smuzhiyun  * stupidly, some callers call with year unmolested;
178*4882a593Smuzhiyun  * and some call with  year = year - 1900.  thanks.
179*4882a593Smuzhiyun  */
ds1511_rtc_set_time(struct device * dev,struct rtc_time * rtc_tm)180*4882a593Smuzhiyun static int ds1511_rtc_set_time(struct device *dev, struct rtc_time *rtc_tm)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun 	u8 mon, day, dow, hrs, min, sec, yrs, cen;
183*4882a593Smuzhiyun 	unsigned long flags;
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	/*
186*4882a593Smuzhiyun 	 * won't have to change this for a while
187*4882a593Smuzhiyun 	 */
188*4882a593Smuzhiyun 	if (rtc_tm->tm_year < 1900)
189*4882a593Smuzhiyun 		rtc_tm->tm_year += 1900;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	if (rtc_tm->tm_year < 1970)
192*4882a593Smuzhiyun 		return -EINVAL;
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	yrs = rtc_tm->tm_year % 100;
195*4882a593Smuzhiyun 	cen = rtc_tm->tm_year / 100;
196*4882a593Smuzhiyun 	mon = rtc_tm->tm_mon + 1;   /* tm_mon starts at zero */
197*4882a593Smuzhiyun 	day = rtc_tm->tm_mday;
198*4882a593Smuzhiyun 	dow = rtc_tm->tm_wday & 0x7; /* automatic BCD */
199*4882a593Smuzhiyun 	hrs = rtc_tm->tm_hour;
200*4882a593Smuzhiyun 	min = rtc_tm->tm_min;
201*4882a593Smuzhiyun 	sec = rtc_tm->tm_sec;
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	if ((mon > 12) || (day == 0))
204*4882a593Smuzhiyun 		return -EINVAL;
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	if (day > rtc_month_days(rtc_tm->tm_mon, rtc_tm->tm_year))
207*4882a593Smuzhiyun 		return -EINVAL;
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	if ((hrs >= 24) || (min >= 60) || (sec >= 60))
210*4882a593Smuzhiyun 		return -EINVAL;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	/*
213*4882a593Smuzhiyun 	 * each register is a different number of valid bits
214*4882a593Smuzhiyun 	 */
215*4882a593Smuzhiyun 	sec = bin2bcd(sec) & 0x7f;
216*4882a593Smuzhiyun 	min = bin2bcd(min) & 0x7f;
217*4882a593Smuzhiyun 	hrs = bin2bcd(hrs) & 0x3f;
218*4882a593Smuzhiyun 	day = bin2bcd(day) & 0x3f;
219*4882a593Smuzhiyun 	mon = bin2bcd(mon) & 0x1f;
220*4882a593Smuzhiyun 	yrs = bin2bcd(yrs) & 0xff;
221*4882a593Smuzhiyun 	cen = bin2bcd(cen) & 0xff;
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	spin_lock_irqsave(&ds1511_lock, flags);
224*4882a593Smuzhiyun 	rtc_disable_update();
225*4882a593Smuzhiyun 	rtc_write(cen, RTC_CENTURY);
226*4882a593Smuzhiyun 	rtc_write(yrs, RTC_YEAR);
227*4882a593Smuzhiyun 	rtc_write((rtc_read(RTC_MON) & 0xe0) | mon, RTC_MON);
228*4882a593Smuzhiyun 	rtc_write(day, RTC_DOM);
229*4882a593Smuzhiyun 	rtc_write(hrs, RTC_HOUR);
230*4882a593Smuzhiyun 	rtc_write(min, RTC_MIN);
231*4882a593Smuzhiyun 	rtc_write(sec, RTC_SEC);
232*4882a593Smuzhiyun 	rtc_write(dow, RTC_DOW);
233*4882a593Smuzhiyun 	rtc_enable_update();
234*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ds1511_lock, flags);
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	return 0;
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun 
ds1511_rtc_read_time(struct device * dev,struct rtc_time * rtc_tm)239*4882a593Smuzhiyun static int ds1511_rtc_read_time(struct device *dev, struct rtc_time *rtc_tm)
240*4882a593Smuzhiyun {
241*4882a593Smuzhiyun 	unsigned int century;
242*4882a593Smuzhiyun 	unsigned long flags;
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	spin_lock_irqsave(&ds1511_lock, flags);
245*4882a593Smuzhiyun 	rtc_disable_update();
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	rtc_tm->tm_sec = rtc_read(RTC_SEC) & 0x7f;
248*4882a593Smuzhiyun 	rtc_tm->tm_min = rtc_read(RTC_MIN) & 0x7f;
249*4882a593Smuzhiyun 	rtc_tm->tm_hour = rtc_read(RTC_HOUR) & 0x3f;
250*4882a593Smuzhiyun 	rtc_tm->tm_mday = rtc_read(RTC_DOM) & 0x3f;
251*4882a593Smuzhiyun 	rtc_tm->tm_wday = rtc_read(RTC_DOW) & 0x7;
252*4882a593Smuzhiyun 	rtc_tm->tm_mon = rtc_read(RTC_MON) & 0x1f;
253*4882a593Smuzhiyun 	rtc_tm->tm_year = rtc_read(RTC_YEAR) & 0x7f;
254*4882a593Smuzhiyun 	century = rtc_read(RTC_CENTURY);
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	rtc_enable_update();
257*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ds1511_lock, flags);
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
260*4882a593Smuzhiyun 	rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
261*4882a593Smuzhiyun 	rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
262*4882a593Smuzhiyun 	rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
263*4882a593Smuzhiyun 	rtc_tm->tm_wday = bcd2bin(rtc_tm->tm_wday);
264*4882a593Smuzhiyun 	rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
265*4882a593Smuzhiyun 	rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
266*4882a593Smuzhiyun 	century = bcd2bin(century) * 100;
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	/*
269*4882a593Smuzhiyun 	 * Account for differences between how the RTC uses the values
270*4882a593Smuzhiyun 	 * and how they are defined in a struct rtc_time;
271*4882a593Smuzhiyun 	 */
272*4882a593Smuzhiyun 	century += rtc_tm->tm_year;
273*4882a593Smuzhiyun 	rtc_tm->tm_year = century - 1900;
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun 	rtc_tm->tm_mon--;
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	return 0;
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun /*
281*4882a593Smuzhiyun  * write the alarm register settings
282*4882a593Smuzhiyun  *
283*4882a593Smuzhiyun  * we only have the use to interrupt every second, otherwise
284*4882a593Smuzhiyun  * known as the update interrupt, or the interrupt if the whole
285*4882a593Smuzhiyun  * date/hours/mins/secs matches.  the ds1511 has many more
286*4882a593Smuzhiyun  * permutations, but the kernel doesn't.
287*4882a593Smuzhiyun  */
288*4882a593Smuzhiyun static void
ds1511_rtc_update_alarm(struct rtc_plat_data * pdata)289*4882a593Smuzhiyun ds1511_rtc_update_alarm(struct rtc_plat_data *pdata)
290*4882a593Smuzhiyun {
291*4882a593Smuzhiyun 	unsigned long flags;
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	spin_lock_irqsave(&pdata->lock, flags);
294*4882a593Smuzhiyun 	rtc_write(pdata->alrm_mday < 0 || (pdata->irqen & RTC_UF) ?
295*4882a593Smuzhiyun 	       0x80 : bin2bcd(pdata->alrm_mday) & 0x3f,
296*4882a593Smuzhiyun 	       RTC_ALARM_DATE);
297*4882a593Smuzhiyun 	rtc_write(pdata->alrm_hour < 0 || (pdata->irqen & RTC_UF) ?
298*4882a593Smuzhiyun 	       0x80 : bin2bcd(pdata->alrm_hour) & 0x3f,
299*4882a593Smuzhiyun 	       RTC_ALARM_HOUR);
300*4882a593Smuzhiyun 	rtc_write(pdata->alrm_min < 0 || (pdata->irqen & RTC_UF) ?
301*4882a593Smuzhiyun 	       0x80 : bin2bcd(pdata->alrm_min) & 0x7f,
302*4882a593Smuzhiyun 	       RTC_ALARM_MIN);
303*4882a593Smuzhiyun 	rtc_write(pdata->alrm_sec < 0 || (pdata->irqen & RTC_UF) ?
304*4882a593Smuzhiyun 	       0x80 : bin2bcd(pdata->alrm_sec) & 0x7f,
305*4882a593Smuzhiyun 	       RTC_ALARM_SEC);
306*4882a593Smuzhiyun 	rtc_write(rtc_read(RTC_CMD) | (pdata->irqen ? RTC_TIE : 0), RTC_CMD);
307*4882a593Smuzhiyun 	rtc_read(RTC_CMD1);	/* clear interrupts */
308*4882a593Smuzhiyun 	spin_unlock_irqrestore(&pdata->lock, flags);
309*4882a593Smuzhiyun }
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun static int
ds1511_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)312*4882a593Smuzhiyun ds1511_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
313*4882a593Smuzhiyun {
314*4882a593Smuzhiyun 	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun 	if (pdata->irq <= 0)
317*4882a593Smuzhiyun 		return -EINVAL;
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	pdata->alrm_mday = alrm->time.tm_mday;
320*4882a593Smuzhiyun 	pdata->alrm_hour = alrm->time.tm_hour;
321*4882a593Smuzhiyun 	pdata->alrm_min = alrm->time.tm_min;
322*4882a593Smuzhiyun 	pdata->alrm_sec = alrm->time.tm_sec;
323*4882a593Smuzhiyun 	if (alrm->enabled)
324*4882a593Smuzhiyun 		pdata->irqen |= RTC_AF;
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun 	ds1511_rtc_update_alarm(pdata);
327*4882a593Smuzhiyun 	return 0;
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun static int
ds1511_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)331*4882a593Smuzhiyun ds1511_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
332*4882a593Smuzhiyun {
333*4882a593Smuzhiyun 	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 	if (pdata->irq <= 0)
336*4882a593Smuzhiyun 		return -EINVAL;
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 	alrm->time.tm_mday = pdata->alrm_mday < 0 ? 0 : pdata->alrm_mday;
339*4882a593Smuzhiyun 	alrm->time.tm_hour = pdata->alrm_hour < 0 ? 0 : pdata->alrm_hour;
340*4882a593Smuzhiyun 	alrm->time.tm_min = pdata->alrm_min < 0 ? 0 : pdata->alrm_min;
341*4882a593Smuzhiyun 	alrm->time.tm_sec = pdata->alrm_sec < 0 ? 0 : pdata->alrm_sec;
342*4882a593Smuzhiyun 	alrm->enabled = (pdata->irqen & RTC_AF) ? 1 : 0;
343*4882a593Smuzhiyun 	return 0;
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun static irqreturn_t
ds1511_interrupt(int irq,void * dev_id)347*4882a593Smuzhiyun ds1511_interrupt(int irq, void *dev_id)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun 	struct platform_device *pdev = dev_id;
350*4882a593Smuzhiyun 	struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
351*4882a593Smuzhiyun 	unsigned long events = 0;
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	spin_lock(&pdata->lock);
354*4882a593Smuzhiyun 	/*
355*4882a593Smuzhiyun 	 * read and clear interrupt
356*4882a593Smuzhiyun 	 */
357*4882a593Smuzhiyun 	if (rtc_read(RTC_CMD1) & DS1511_IRQF) {
358*4882a593Smuzhiyun 		events = RTC_IRQF;
359*4882a593Smuzhiyun 		if (rtc_read(RTC_ALARM_SEC) & 0x80)
360*4882a593Smuzhiyun 			events |= RTC_UF;
361*4882a593Smuzhiyun 		else
362*4882a593Smuzhiyun 			events |= RTC_AF;
363*4882a593Smuzhiyun 		rtc_update_irq(pdata->rtc, 1, events);
364*4882a593Smuzhiyun 	}
365*4882a593Smuzhiyun 	spin_unlock(&pdata->lock);
366*4882a593Smuzhiyun 	return events ? IRQ_HANDLED : IRQ_NONE;
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun 
ds1511_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)369*4882a593Smuzhiyun static int ds1511_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
370*4882a593Smuzhiyun {
371*4882a593Smuzhiyun 	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun 	if (pdata->irq <= 0)
374*4882a593Smuzhiyun 		return -EINVAL;
375*4882a593Smuzhiyun 	if (enabled)
376*4882a593Smuzhiyun 		pdata->irqen |= RTC_AF;
377*4882a593Smuzhiyun 	else
378*4882a593Smuzhiyun 		pdata->irqen &= ~RTC_AF;
379*4882a593Smuzhiyun 	ds1511_rtc_update_alarm(pdata);
380*4882a593Smuzhiyun 	return 0;
381*4882a593Smuzhiyun }
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun static const struct rtc_class_ops ds1511_rtc_ops = {
384*4882a593Smuzhiyun 	.read_time		= ds1511_rtc_read_time,
385*4882a593Smuzhiyun 	.set_time		= ds1511_rtc_set_time,
386*4882a593Smuzhiyun 	.read_alarm		= ds1511_rtc_read_alarm,
387*4882a593Smuzhiyun 	.set_alarm		= ds1511_rtc_set_alarm,
388*4882a593Smuzhiyun 	.alarm_irq_enable	= ds1511_rtc_alarm_irq_enable,
389*4882a593Smuzhiyun };
390*4882a593Smuzhiyun 
ds1511_nvram_read(void * priv,unsigned int pos,void * buf,size_t size)391*4882a593Smuzhiyun static int ds1511_nvram_read(void *priv, unsigned int pos, void *buf,
392*4882a593Smuzhiyun 			     size_t size)
393*4882a593Smuzhiyun {
394*4882a593Smuzhiyun 	int i;
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	rtc_write(pos, DS1511_RAMADDR_LSB);
397*4882a593Smuzhiyun 	for (i = 0; i < size; i++)
398*4882a593Smuzhiyun 		*(char *)buf++ = rtc_read(DS1511_RAMDATA);
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	return 0;
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun 
ds1511_nvram_write(void * priv,unsigned int pos,void * buf,size_t size)403*4882a593Smuzhiyun static int ds1511_nvram_write(void *priv, unsigned int pos, void *buf,
404*4882a593Smuzhiyun 			      size_t size)
405*4882a593Smuzhiyun {
406*4882a593Smuzhiyun 	int i;
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 	rtc_write(pos, DS1511_RAMADDR_LSB);
409*4882a593Smuzhiyun 	for (i = 0; i < size; i++)
410*4882a593Smuzhiyun 		rtc_write(*(char *)buf++, DS1511_RAMDATA);
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun 	return 0;
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun 
ds1511_rtc_probe(struct platform_device * pdev)415*4882a593Smuzhiyun static int ds1511_rtc_probe(struct platform_device *pdev)
416*4882a593Smuzhiyun {
417*4882a593Smuzhiyun 	struct rtc_plat_data *pdata;
418*4882a593Smuzhiyun 	int ret = 0;
419*4882a593Smuzhiyun 	struct nvmem_config ds1511_nvmem_cfg = {
420*4882a593Smuzhiyun 		.name = "ds1511_nvram",
421*4882a593Smuzhiyun 		.word_size = 1,
422*4882a593Smuzhiyun 		.stride = 1,
423*4882a593Smuzhiyun 		.size = DS1511_RAM_MAX,
424*4882a593Smuzhiyun 		.reg_read = ds1511_nvram_read,
425*4882a593Smuzhiyun 		.reg_write = ds1511_nvram_write,
426*4882a593Smuzhiyun 		.priv = &pdev->dev,
427*4882a593Smuzhiyun 	};
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun 	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
430*4882a593Smuzhiyun 	if (!pdata)
431*4882a593Smuzhiyun 		return -ENOMEM;
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 	ds1511_base = devm_platform_ioremap_resource(pdev, 0);
434*4882a593Smuzhiyun 	if (IS_ERR(ds1511_base))
435*4882a593Smuzhiyun 		return PTR_ERR(ds1511_base);
436*4882a593Smuzhiyun 	pdata->ioaddr = ds1511_base;
437*4882a593Smuzhiyun 	pdata->irq = platform_get_irq(pdev, 0);
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun 	/*
440*4882a593Smuzhiyun 	 * turn on the clock and the crystal, etc.
441*4882a593Smuzhiyun 	 */
442*4882a593Smuzhiyun 	rtc_write(DS1511_BME, RTC_CMD);
443*4882a593Smuzhiyun 	rtc_write(0, RTC_CMD1);
444*4882a593Smuzhiyun 	/*
445*4882a593Smuzhiyun 	 * clear the wdog counter
446*4882a593Smuzhiyun 	 */
447*4882a593Smuzhiyun 	rtc_write(0, DS1511_WD_MSEC);
448*4882a593Smuzhiyun 	rtc_write(0, DS1511_WD_SEC);
449*4882a593Smuzhiyun 	/*
450*4882a593Smuzhiyun 	 * start the clock
451*4882a593Smuzhiyun 	 */
452*4882a593Smuzhiyun 	rtc_enable_update();
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun 	/*
455*4882a593Smuzhiyun 	 * check for a dying bat-tree
456*4882a593Smuzhiyun 	 */
457*4882a593Smuzhiyun 	if (rtc_read(RTC_CMD1) & DS1511_BLF1)
458*4882a593Smuzhiyun 		dev_warn(&pdev->dev, "voltage-low detected.\n");
459*4882a593Smuzhiyun 
460*4882a593Smuzhiyun 	spin_lock_init(&pdata->lock);
461*4882a593Smuzhiyun 	platform_set_drvdata(pdev, pdata);
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 	pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
464*4882a593Smuzhiyun 	if (IS_ERR(pdata->rtc))
465*4882a593Smuzhiyun 		return PTR_ERR(pdata->rtc);
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun 	pdata->rtc->ops = &ds1511_rtc_ops;
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun 	pdata->rtc->nvram_old_abi = true;
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun 	ret = rtc_register_device(pdata->rtc);
472*4882a593Smuzhiyun 	if (ret)
473*4882a593Smuzhiyun 		return ret;
474*4882a593Smuzhiyun 
475*4882a593Smuzhiyun 	rtc_nvmem_register(pdata->rtc, &ds1511_nvmem_cfg);
476*4882a593Smuzhiyun 
477*4882a593Smuzhiyun 	/*
478*4882a593Smuzhiyun 	 * if the platform has an interrupt in mind for this device,
479*4882a593Smuzhiyun 	 * then by all means, set it
480*4882a593Smuzhiyun 	 */
481*4882a593Smuzhiyun 	if (pdata->irq > 0) {
482*4882a593Smuzhiyun 		rtc_read(RTC_CMD1);
483*4882a593Smuzhiyun 		if (devm_request_irq(&pdev->dev, pdata->irq, ds1511_interrupt,
484*4882a593Smuzhiyun 			IRQF_SHARED, pdev->name, pdev) < 0) {
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 			dev_warn(&pdev->dev, "interrupt not available.\n");
487*4882a593Smuzhiyun 			pdata->irq = 0;
488*4882a593Smuzhiyun 		}
489*4882a593Smuzhiyun 	}
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun 	return 0;
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun /* work with hotplug and coldplug */
495*4882a593Smuzhiyun MODULE_ALIAS("platform:ds1511");
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun static struct platform_driver ds1511_rtc_driver = {
498*4882a593Smuzhiyun 	.probe		= ds1511_rtc_probe,
499*4882a593Smuzhiyun 	.driver		= {
500*4882a593Smuzhiyun 		.name	= "ds1511",
501*4882a593Smuzhiyun 	},
502*4882a593Smuzhiyun };
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun module_platform_driver(ds1511_rtc_driver);
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun MODULE_AUTHOR("Andrew Sharp <andy.sharp@lsi.com>");
507*4882a593Smuzhiyun MODULE_DESCRIPTION("Dallas DS1511 RTC driver");
508*4882a593Smuzhiyun MODULE_LICENSE("GPL");
509