xref: /OK3568_Linux_fs/kernel/drivers/rtc/rtc-ds1347.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /* rtc-ds1347.c
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Driver for Dallas Semiconductor DS1347 Low Current, SPI Compatible
5*4882a593Smuzhiyun  * Real Time Clock
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author : Raghavendra Chandra Ganiga <ravi23ganiga@gmail.com>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/rtc.h>
15*4882a593Smuzhiyun #include <linux/spi/spi.h>
16*4882a593Smuzhiyun #include <linux/bcd.h>
17*4882a593Smuzhiyun #include <linux/regmap.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun /* Registers in ds1347 rtc */
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define DS1347_SECONDS_REG	0x01
22*4882a593Smuzhiyun #define DS1347_MINUTES_REG	0x03
23*4882a593Smuzhiyun #define DS1347_HOURS_REG	0x05
24*4882a593Smuzhiyun #define DS1347_DATE_REG		0x07
25*4882a593Smuzhiyun #define DS1347_MONTH_REG	0x09
26*4882a593Smuzhiyun #define DS1347_DAY_REG		0x0B
27*4882a593Smuzhiyun #define DS1347_YEAR_REG		0x0D
28*4882a593Smuzhiyun #define DS1347_CONTROL_REG	0x0F
29*4882a593Smuzhiyun #define DS1347_CENTURY_REG	0x13
30*4882a593Smuzhiyun #define DS1347_STATUS_REG	0x17
31*4882a593Smuzhiyun #define DS1347_CLOCK_BURST	0x3F
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define DS1347_WP_BIT		BIT(7)
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #define DS1347_NEOSC_BIT	BIT(7)
36*4882a593Smuzhiyun #define DS1347_OSF_BIT		BIT(2)
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun static const struct regmap_range ds1347_ranges[] = {
39*4882a593Smuzhiyun 	{
40*4882a593Smuzhiyun 		.range_min = DS1347_SECONDS_REG,
41*4882a593Smuzhiyun 		.range_max = DS1347_STATUS_REG,
42*4882a593Smuzhiyun 	},
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun static const struct regmap_access_table ds1347_access_table = {
46*4882a593Smuzhiyun 	.yes_ranges = ds1347_ranges,
47*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(ds1347_ranges),
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun 
ds1347_read_time(struct device * dev,struct rtc_time * dt)50*4882a593Smuzhiyun static int ds1347_read_time(struct device *dev, struct rtc_time *dt)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun 	struct regmap *map = dev_get_drvdata(dev);
53*4882a593Smuzhiyun 	unsigned int status, century, secs;
54*4882a593Smuzhiyun 	unsigned char buf[8];
55*4882a593Smuzhiyun 	int err;
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	err = regmap_read(map, DS1347_STATUS_REG, &status);
58*4882a593Smuzhiyun 	if (err)
59*4882a593Smuzhiyun 		return err;
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	if (status & DS1347_OSF_BIT)
62*4882a593Smuzhiyun 		return -EINVAL;
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	do {
65*4882a593Smuzhiyun 		err = regmap_bulk_read(map, DS1347_CLOCK_BURST, buf, 8);
66*4882a593Smuzhiyun 		if (err)
67*4882a593Smuzhiyun 			return err;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 		err = regmap_read(map, DS1347_CENTURY_REG, &century);
70*4882a593Smuzhiyun 		if (err)
71*4882a593Smuzhiyun 			return err;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 		err = regmap_read(map, DS1347_SECONDS_REG, &secs);
74*4882a593Smuzhiyun 		if (err)
75*4882a593Smuzhiyun 			return err;
76*4882a593Smuzhiyun 	} while (buf[0] != secs);
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	dt->tm_sec = bcd2bin(buf[0]);
79*4882a593Smuzhiyun 	dt->tm_min = bcd2bin(buf[1] & 0x7f);
80*4882a593Smuzhiyun 	dt->tm_hour = bcd2bin(buf[2] & 0x3F);
81*4882a593Smuzhiyun 	dt->tm_mday = bcd2bin(buf[3]);
82*4882a593Smuzhiyun 	dt->tm_mon = bcd2bin(buf[4]) - 1;
83*4882a593Smuzhiyun 	dt->tm_wday = bcd2bin(buf[5]) - 1;
84*4882a593Smuzhiyun 	dt->tm_year = (bcd2bin(century) * 100) + bcd2bin(buf[6]) - 1900;
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	return 0;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun 
ds1347_set_time(struct device * dev,struct rtc_time * dt)89*4882a593Smuzhiyun static int ds1347_set_time(struct device *dev, struct rtc_time *dt)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun 	struct regmap *map = dev_get_drvdata(dev);
92*4882a593Smuzhiyun 	unsigned int century;
93*4882a593Smuzhiyun 	unsigned char buf[8];
94*4882a593Smuzhiyun 	int err;
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	err = regmap_update_bits(map, DS1347_STATUS_REG,
97*4882a593Smuzhiyun 				 DS1347_NEOSC_BIT, DS1347_NEOSC_BIT);
98*4882a593Smuzhiyun 	if (err)
99*4882a593Smuzhiyun 		return err;
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	buf[0] = bin2bcd(dt->tm_sec);
102*4882a593Smuzhiyun 	buf[1] = bin2bcd(dt->tm_min);
103*4882a593Smuzhiyun 	buf[2] = (bin2bcd(dt->tm_hour) & 0x3F);
104*4882a593Smuzhiyun 	buf[3] = bin2bcd(dt->tm_mday);
105*4882a593Smuzhiyun 	buf[4] = bin2bcd(dt->tm_mon + 1);
106*4882a593Smuzhiyun 	buf[5] = bin2bcd(dt->tm_wday + 1);
107*4882a593Smuzhiyun 	buf[6] = bin2bcd(dt->tm_year % 100);
108*4882a593Smuzhiyun 	buf[7] = bin2bcd(0x00);
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	err = regmap_bulk_write(map, DS1347_CLOCK_BURST, buf, 8);
111*4882a593Smuzhiyun 	if (err)
112*4882a593Smuzhiyun 		return err;
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	century = (dt->tm_year / 100) + 19;
115*4882a593Smuzhiyun 	err = regmap_write(map, DS1347_CENTURY_REG, century);
116*4882a593Smuzhiyun 	if (err)
117*4882a593Smuzhiyun 		return err;
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	return regmap_update_bits(map, DS1347_STATUS_REG,
120*4882a593Smuzhiyun 				  DS1347_NEOSC_BIT | DS1347_OSF_BIT, 0);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun static const struct rtc_class_ops ds1347_rtc_ops = {
124*4882a593Smuzhiyun 	.read_time = ds1347_read_time,
125*4882a593Smuzhiyun 	.set_time = ds1347_set_time,
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun 
ds1347_probe(struct spi_device * spi)128*4882a593Smuzhiyun static int ds1347_probe(struct spi_device *spi)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun 	struct rtc_device *rtc;
131*4882a593Smuzhiyun 	struct regmap_config config;
132*4882a593Smuzhiyun 	struct regmap *map;
133*4882a593Smuzhiyun 	int err;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	memset(&config, 0, sizeof(config));
136*4882a593Smuzhiyun 	config.reg_bits = 8;
137*4882a593Smuzhiyun 	config.val_bits = 8;
138*4882a593Smuzhiyun 	config.read_flag_mask = 0x80;
139*4882a593Smuzhiyun 	config.max_register = 0x3F;
140*4882a593Smuzhiyun 	config.wr_table = &ds1347_access_table;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	/* spi setup with ds1347 in mode 3 and bits per word as 8 */
143*4882a593Smuzhiyun 	spi->mode = SPI_MODE_3;
144*4882a593Smuzhiyun 	spi->bits_per_word = 8;
145*4882a593Smuzhiyun 	spi_setup(spi);
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	map = devm_regmap_init_spi(spi, &config);
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	if (IS_ERR(map)) {
150*4882a593Smuzhiyun 		dev_err(&spi->dev, "ds1347 regmap init spi failed\n");
151*4882a593Smuzhiyun 		return PTR_ERR(map);
152*4882a593Smuzhiyun 	}
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	spi_set_drvdata(spi, map);
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	/* Disable the write protect of rtc */
157*4882a593Smuzhiyun 	err = regmap_update_bits(map, DS1347_CONTROL_REG, DS1347_WP_BIT, 0);
158*4882a593Smuzhiyun 	if (err)
159*4882a593Smuzhiyun 		return err;
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	rtc = devm_rtc_allocate_device(&spi->dev);
162*4882a593Smuzhiyun 	if (IS_ERR(rtc))
163*4882a593Smuzhiyun 		return PTR_ERR(rtc);
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	rtc->ops = &ds1347_rtc_ops;
166*4882a593Smuzhiyun 	rtc->range_min = RTC_TIMESTAMP_BEGIN_0000;
167*4882a593Smuzhiyun 	rtc->range_max = RTC_TIMESTAMP_END_9999;
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	return rtc_register_device(rtc);
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun static struct spi_driver ds1347_driver = {
173*4882a593Smuzhiyun 	.driver = {
174*4882a593Smuzhiyun 		.name = "ds1347",
175*4882a593Smuzhiyun 	},
176*4882a593Smuzhiyun 	.probe = ds1347_probe,
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun module_spi_driver(ds1347_driver);
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun MODULE_DESCRIPTION("DS1347 SPI RTC DRIVER");
182*4882a593Smuzhiyun MODULE_AUTHOR("Raghavendra C Ganiga <ravi23ganiga@gmail.com>");
183*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
184