xref: /OK3568_Linux_fs/kernel/drivers/rtc/rtc-ds1302.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Dallas DS1302 RTC Support
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Copyright (C) 2002 David McCullough
6*4882a593Smuzhiyun  *  Copyright (C) 2003 - 2007 Paul Mundt
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/bcd.h>
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/of.h>
15*4882a593Smuzhiyun #include <linux/rtc.h>
16*4882a593Smuzhiyun #include <linux/spi/spi.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define	RTC_CMD_READ	0x81		/* Read command */
19*4882a593Smuzhiyun #define	RTC_CMD_WRITE	0x80		/* Write command */
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define	RTC_CMD_WRITE_ENABLE	0x00		/* Write enable */
22*4882a593Smuzhiyun #define	RTC_CMD_WRITE_DISABLE	0x80		/* Write disable */
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #define RTC_ADDR_RAM0	0x20		/* Address of RAM0 */
25*4882a593Smuzhiyun #define RTC_ADDR_TCR	0x08		/* Address of trickle charge register */
26*4882a593Smuzhiyun #define RTC_CLCK_BURST	0x1F		/* Address of clock burst */
27*4882a593Smuzhiyun #define	RTC_CLCK_LEN	0x08		/* Size of clock burst */
28*4882a593Smuzhiyun #define	RTC_ADDR_CTRL	0x07		/* Address of control register */
29*4882a593Smuzhiyun #define	RTC_ADDR_YEAR	0x06		/* Address of year register */
30*4882a593Smuzhiyun #define	RTC_ADDR_DAY	0x05		/* Address of day of week register */
31*4882a593Smuzhiyun #define	RTC_ADDR_MON	0x04		/* Address of month register */
32*4882a593Smuzhiyun #define	RTC_ADDR_DATE	0x03		/* Address of day of month register */
33*4882a593Smuzhiyun #define	RTC_ADDR_HOUR	0x02		/* Address of hour register */
34*4882a593Smuzhiyun #define	RTC_ADDR_MIN	0x01		/* Address of minute register */
35*4882a593Smuzhiyun #define	RTC_ADDR_SEC	0x00		/* Address of second register */
36*4882a593Smuzhiyun 
ds1302_rtc_set_time(struct device * dev,struct rtc_time * time)37*4882a593Smuzhiyun static int ds1302_rtc_set_time(struct device *dev, struct rtc_time *time)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun 	struct spi_device	*spi = dev_get_drvdata(dev);
40*4882a593Smuzhiyun 	u8		buf[1 + RTC_CLCK_LEN];
41*4882a593Smuzhiyun 	u8		*bp;
42*4882a593Smuzhiyun 	int		status;
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun 	/* Enable writing */
45*4882a593Smuzhiyun 	bp = buf;
46*4882a593Smuzhiyun 	*bp++ = RTC_ADDR_CTRL << 1 | RTC_CMD_WRITE;
47*4882a593Smuzhiyun 	*bp++ = RTC_CMD_WRITE_ENABLE;
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	status = spi_write_then_read(spi, buf, 2,
50*4882a593Smuzhiyun 			NULL, 0);
51*4882a593Smuzhiyun 	if (status)
52*4882a593Smuzhiyun 		return status;
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	/* Write registers starting at the first time/date address. */
55*4882a593Smuzhiyun 	bp = buf;
56*4882a593Smuzhiyun 	*bp++ = RTC_CLCK_BURST << 1 | RTC_CMD_WRITE;
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	*bp++ = bin2bcd(time->tm_sec);
59*4882a593Smuzhiyun 	*bp++ = bin2bcd(time->tm_min);
60*4882a593Smuzhiyun 	*bp++ = bin2bcd(time->tm_hour);
61*4882a593Smuzhiyun 	*bp++ = bin2bcd(time->tm_mday);
62*4882a593Smuzhiyun 	*bp++ = bin2bcd(time->tm_mon + 1);
63*4882a593Smuzhiyun 	*bp++ = time->tm_wday + 1;
64*4882a593Smuzhiyun 	*bp++ = bin2bcd(time->tm_year % 100);
65*4882a593Smuzhiyun 	*bp++ = RTC_CMD_WRITE_DISABLE;
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	/* use write-then-read since dma from stack is nonportable */
68*4882a593Smuzhiyun 	return spi_write_then_read(spi, buf, sizeof(buf),
69*4882a593Smuzhiyun 			NULL, 0);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun 
ds1302_rtc_get_time(struct device * dev,struct rtc_time * time)72*4882a593Smuzhiyun static int ds1302_rtc_get_time(struct device *dev, struct rtc_time *time)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun 	struct spi_device	*spi = dev_get_drvdata(dev);
75*4882a593Smuzhiyun 	u8		addr = RTC_CLCK_BURST << 1 | RTC_CMD_READ;
76*4882a593Smuzhiyun 	u8		buf[RTC_CLCK_LEN - 1];
77*4882a593Smuzhiyun 	int		status;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	/* Use write-then-read to get all the date/time registers
80*4882a593Smuzhiyun 	 * since dma from stack is nonportable
81*4882a593Smuzhiyun 	 */
82*4882a593Smuzhiyun 	status = spi_write_then_read(spi, &addr, sizeof(addr),
83*4882a593Smuzhiyun 			buf, sizeof(buf));
84*4882a593Smuzhiyun 	if (status < 0)
85*4882a593Smuzhiyun 		return status;
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	/* Decode the registers */
88*4882a593Smuzhiyun 	time->tm_sec = bcd2bin(buf[RTC_ADDR_SEC]);
89*4882a593Smuzhiyun 	time->tm_min = bcd2bin(buf[RTC_ADDR_MIN]);
90*4882a593Smuzhiyun 	time->tm_hour = bcd2bin(buf[RTC_ADDR_HOUR]);
91*4882a593Smuzhiyun 	time->tm_wday = buf[RTC_ADDR_DAY] - 1;
92*4882a593Smuzhiyun 	time->tm_mday = bcd2bin(buf[RTC_ADDR_DATE]);
93*4882a593Smuzhiyun 	time->tm_mon = bcd2bin(buf[RTC_ADDR_MON]) - 1;
94*4882a593Smuzhiyun 	time->tm_year = bcd2bin(buf[RTC_ADDR_YEAR]) + 100;
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	return 0;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun static const struct rtc_class_ops ds1302_rtc_ops = {
100*4882a593Smuzhiyun 	.read_time	= ds1302_rtc_get_time,
101*4882a593Smuzhiyun 	.set_time	= ds1302_rtc_set_time,
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun 
ds1302_probe(struct spi_device * spi)104*4882a593Smuzhiyun static int ds1302_probe(struct spi_device *spi)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun 	struct rtc_device	*rtc;
107*4882a593Smuzhiyun 	u8		addr;
108*4882a593Smuzhiyun 	u8		buf[4];
109*4882a593Smuzhiyun 	u8		*bp;
110*4882a593Smuzhiyun 	int		status;
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	/* Sanity check board setup data.  This may be hooked up
113*4882a593Smuzhiyun 	 * in 3wire mode, but we don't care.  Note that unless
114*4882a593Smuzhiyun 	 * there's an inverter in place, this needs SPI_CS_HIGH!
115*4882a593Smuzhiyun 	 */
116*4882a593Smuzhiyun 	if (spi->bits_per_word && (spi->bits_per_word != 8)) {
117*4882a593Smuzhiyun 		dev_err(&spi->dev, "bad word length\n");
118*4882a593Smuzhiyun 		return -EINVAL;
119*4882a593Smuzhiyun 	} else if (spi->max_speed_hz > 2000000) {
120*4882a593Smuzhiyun 		dev_err(&spi->dev, "speed is too high\n");
121*4882a593Smuzhiyun 		return -EINVAL;
122*4882a593Smuzhiyun 	} else if (spi->mode & SPI_CPHA) {
123*4882a593Smuzhiyun 		dev_err(&spi->dev, "bad mode\n");
124*4882a593Smuzhiyun 		return -EINVAL;
125*4882a593Smuzhiyun 	}
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	addr = RTC_ADDR_CTRL << 1 | RTC_CMD_READ;
128*4882a593Smuzhiyun 	status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
129*4882a593Smuzhiyun 	if (status < 0) {
130*4882a593Smuzhiyun 		dev_err(&spi->dev, "control register read error %d\n",
131*4882a593Smuzhiyun 				status);
132*4882a593Smuzhiyun 		return status;
133*4882a593Smuzhiyun 	}
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	if ((buf[0] & ~RTC_CMD_WRITE_DISABLE) != 0) {
136*4882a593Smuzhiyun 		status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
137*4882a593Smuzhiyun 		if (status < 0) {
138*4882a593Smuzhiyun 			dev_err(&spi->dev, "control register read error %d\n",
139*4882a593Smuzhiyun 					status);
140*4882a593Smuzhiyun 			return status;
141*4882a593Smuzhiyun 		}
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 		if ((buf[0] & ~RTC_CMD_WRITE_DISABLE) != 0) {
144*4882a593Smuzhiyun 			dev_err(&spi->dev, "junk in control register\n");
145*4882a593Smuzhiyun 			return -ENODEV;
146*4882a593Smuzhiyun 		}
147*4882a593Smuzhiyun 	}
148*4882a593Smuzhiyun 	if (buf[0] == 0) {
149*4882a593Smuzhiyun 		bp = buf;
150*4882a593Smuzhiyun 		*bp++ = RTC_ADDR_CTRL << 1 | RTC_CMD_WRITE;
151*4882a593Smuzhiyun 		*bp++ = RTC_CMD_WRITE_DISABLE;
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 		status = spi_write_then_read(spi, buf, 2, NULL, 0);
154*4882a593Smuzhiyun 		if (status < 0) {
155*4882a593Smuzhiyun 			dev_err(&spi->dev, "control register write error %d\n",
156*4882a593Smuzhiyun 					status);
157*4882a593Smuzhiyun 			return status;
158*4882a593Smuzhiyun 		}
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 		addr = RTC_ADDR_CTRL << 1 | RTC_CMD_READ;
161*4882a593Smuzhiyun 		status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
162*4882a593Smuzhiyun 		if (status < 0) {
163*4882a593Smuzhiyun 			dev_err(&spi->dev,
164*4882a593Smuzhiyun 					"error %d reading control register\n",
165*4882a593Smuzhiyun 					status);
166*4882a593Smuzhiyun 			return status;
167*4882a593Smuzhiyun 		}
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 		if (buf[0] != RTC_CMD_WRITE_DISABLE) {
170*4882a593Smuzhiyun 			dev_err(&spi->dev, "failed to detect chip\n");
171*4882a593Smuzhiyun 			return -ENODEV;
172*4882a593Smuzhiyun 		}
173*4882a593Smuzhiyun 	}
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	spi_set_drvdata(spi, spi);
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	rtc = devm_rtc_device_register(&spi->dev, "ds1302",
178*4882a593Smuzhiyun 			&ds1302_rtc_ops, THIS_MODULE);
179*4882a593Smuzhiyun 	if (IS_ERR(rtc)) {
180*4882a593Smuzhiyun 		status = PTR_ERR(rtc);
181*4882a593Smuzhiyun 		dev_err(&spi->dev, "error %d registering rtc\n", status);
182*4882a593Smuzhiyun 		return status;
183*4882a593Smuzhiyun 	}
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	return 0;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun 
ds1302_remove(struct spi_device * spi)188*4882a593Smuzhiyun static int ds1302_remove(struct spi_device *spi)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun 	spi_set_drvdata(spi, NULL);
191*4882a593Smuzhiyun 	return 0;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun #ifdef CONFIG_OF
195*4882a593Smuzhiyun static const struct of_device_id ds1302_dt_ids[] = {
196*4882a593Smuzhiyun 	{ .compatible = "maxim,ds1302", },
197*4882a593Smuzhiyun 	{ /* sentinel */ }
198*4882a593Smuzhiyun };
199*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ds1302_dt_ids);
200*4882a593Smuzhiyun #endif
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun static struct spi_driver ds1302_driver = {
203*4882a593Smuzhiyun 	.driver.name	= "rtc-ds1302",
204*4882a593Smuzhiyun 	.driver.of_match_table = of_match_ptr(ds1302_dt_ids),
205*4882a593Smuzhiyun 	.probe		= ds1302_probe,
206*4882a593Smuzhiyun 	.remove		= ds1302_remove,
207*4882a593Smuzhiyun };
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun module_spi_driver(ds1302_driver);
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun MODULE_DESCRIPTION("Dallas DS1302 RTC driver");
212*4882a593Smuzhiyun MODULE_AUTHOR("Paul Mundt, David McCullough");
213*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
214