1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Real time clock device driver for DA9063
4*4882a593Smuzhiyun * Copyright (C) 2013-2015 Dialog Semiconductor Ltd.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/delay.h>
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/interrupt.h>
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/of.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/regmap.h>
15*4882a593Smuzhiyun #include <linux/rtc.h>
16*4882a593Smuzhiyun #include <linux/slab.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <linux/mfd/da9062/registers.h>
19*4882a593Smuzhiyun #include <linux/mfd/da9063/registers.h>
20*4882a593Smuzhiyun #include <linux/mfd/da9063/core.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define YEARS_TO_DA9063(year) ((year) - 100)
23*4882a593Smuzhiyun #define MONTHS_TO_DA9063(month) ((month) + 1)
24*4882a593Smuzhiyun #define YEARS_FROM_DA9063(year) ((year) + 100)
25*4882a593Smuzhiyun #define MONTHS_FROM_DA9063(month) ((month) - 1)
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun enum {
28*4882a593Smuzhiyun RTC_SEC = 0,
29*4882a593Smuzhiyun RTC_MIN = 1,
30*4882a593Smuzhiyun RTC_HOUR = 2,
31*4882a593Smuzhiyun RTC_DAY = 3,
32*4882a593Smuzhiyun RTC_MONTH = 4,
33*4882a593Smuzhiyun RTC_YEAR = 5,
34*4882a593Smuzhiyun RTC_DATA_LEN
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun struct da9063_compatible_rtc_regmap {
38*4882a593Smuzhiyun /* REGS */
39*4882a593Smuzhiyun int rtc_enable_reg;
40*4882a593Smuzhiyun int rtc_enable_32k_crystal_reg;
41*4882a593Smuzhiyun int rtc_alarm_secs_reg;
42*4882a593Smuzhiyun int rtc_alarm_year_reg;
43*4882a593Smuzhiyun int rtc_count_secs_reg;
44*4882a593Smuzhiyun int rtc_count_year_reg;
45*4882a593Smuzhiyun int rtc_event_reg;
46*4882a593Smuzhiyun /* MASKS */
47*4882a593Smuzhiyun int rtc_enable_mask;
48*4882a593Smuzhiyun int rtc_crystal_mask;
49*4882a593Smuzhiyun int rtc_event_alarm_mask;
50*4882a593Smuzhiyun int rtc_alarm_on_mask;
51*4882a593Smuzhiyun int rtc_alarm_status_mask;
52*4882a593Smuzhiyun int rtc_tick_on_mask;
53*4882a593Smuzhiyun int rtc_ready_to_read_mask;
54*4882a593Smuzhiyun int rtc_count_sec_mask;
55*4882a593Smuzhiyun int rtc_count_min_mask;
56*4882a593Smuzhiyun int rtc_count_hour_mask;
57*4882a593Smuzhiyun int rtc_count_day_mask;
58*4882a593Smuzhiyun int rtc_count_month_mask;
59*4882a593Smuzhiyun int rtc_count_year_mask;
60*4882a593Smuzhiyun /* ALARM CONFIG */
61*4882a593Smuzhiyun int rtc_data_start;
62*4882a593Smuzhiyun int rtc_alarm_len;
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun struct da9063_compatible_rtc {
66*4882a593Smuzhiyun struct rtc_device *rtc_dev;
67*4882a593Smuzhiyun struct rtc_time alarm_time;
68*4882a593Smuzhiyun struct regmap *regmap;
69*4882a593Smuzhiyun const struct da9063_compatible_rtc_regmap *config;
70*4882a593Smuzhiyun bool rtc_sync;
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun static const struct da9063_compatible_rtc_regmap da9063_ad_regs = {
74*4882a593Smuzhiyun /* REGS */
75*4882a593Smuzhiyun .rtc_enable_reg = DA9063_REG_CONTROL_E,
76*4882a593Smuzhiyun .rtc_alarm_secs_reg = DA9063_AD_REG_ALARM_MI,
77*4882a593Smuzhiyun .rtc_alarm_year_reg = DA9063_AD_REG_ALARM_Y,
78*4882a593Smuzhiyun .rtc_count_secs_reg = DA9063_REG_COUNT_S,
79*4882a593Smuzhiyun .rtc_count_year_reg = DA9063_REG_COUNT_Y,
80*4882a593Smuzhiyun .rtc_event_reg = DA9063_REG_EVENT_A,
81*4882a593Smuzhiyun /* MASKS */
82*4882a593Smuzhiyun .rtc_enable_mask = DA9063_RTC_EN,
83*4882a593Smuzhiyun .rtc_crystal_mask = DA9063_CRYSTAL,
84*4882a593Smuzhiyun .rtc_enable_32k_crystal_reg = DA9063_REG_EN_32K,
85*4882a593Smuzhiyun .rtc_event_alarm_mask = DA9063_E_ALARM,
86*4882a593Smuzhiyun .rtc_alarm_on_mask = DA9063_ALARM_ON,
87*4882a593Smuzhiyun .rtc_alarm_status_mask = DA9063_ALARM_STATUS_ALARM |
88*4882a593Smuzhiyun DA9063_ALARM_STATUS_TICK,
89*4882a593Smuzhiyun .rtc_tick_on_mask = DA9063_TICK_ON,
90*4882a593Smuzhiyun .rtc_ready_to_read_mask = DA9063_RTC_READ,
91*4882a593Smuzhiyun .rtc_count_sec_mask = DA9063_COUNT_SEC_MASK,
92*4882a593Smuzhiyun .rtc_count_min_mask = DA9063_COUNT_MIN_MASK,
93*4882a593Smuzhiyun .rtc_count_hour_mask = DA9063_COUNT_HOUR_MASK,
94*4882a593Smuzhiyun .rtc_count_day_mask = DA9063_COUNT_DAY_MASK,
95*4882a593Smuzhiyun .rtc_count_month_mask = DA9063_COUNT_MONTH_MASK,
96*4882a593Smuzhiyun .rtc_count_year_mask = DA9063_COUNT_YEAR_MASK,
97*4882a593Smuzhiyun /* ALARM CONFIG */
98*4882a593Smuzhiyun .rtc_data_start = RTC_MIN,
99*4882a593Smuzhiyun .rtc_alarm_len = RTC_DATA_LEN - 1,
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun static const struct da9063_compatible_rtc_regmap da9063_bb_regs = {
103*4882a593Smuzhiyun /* REGS */
104*4882a593Smuzhiyun .rtc_enable_reg = DA9063_REG_CONTROL_E,
105*4882a593Smuzhiyun .rtc_alarm_secs_reg = DA9063_BB_REG_ALARM_S,
106*4882a593Smuzhiyun .rtc_alarm_year_reg = DA9063_BB_REG_ALARM_Y,
107*4882a593Smuzhiyun .rtc_count_secs_reg = DA9063_REG_COUNT_S,
108*4882a593Smuzhiyun .rtc_count_year_reg = DA9063_REG_COUNT_Y,
109*4882a593Smuzhiyun .rtc_event_reg = DA9063_REG_EVENT_A,
110*4882a593Smuzhiyun /* MASKS */
111*4882a593Smuzhiyun .rtc_enable_mask = DA9063_RTC_EN,
112*4882a593Smuzhiyun .rtc_crystal_mask = DA9063_CRYSTAL,
113*4882a593Smuzhiyun .rtc_enable_32k_crystal_reg = DA9063_REG_EN_32K,
114*4882a593Smuzhiyun .rtc_event_alarm_mask = DA9063_E_ALARM,
115*4882a593Smuzhiyun .rtc_alarm_on_mask = DA9063_ALARM_ON,
116*4882a593Smuzhiyun .rtc_alarm_status_mask = DA9063_ALARM_STATUS_ALARM |
117*4882a593Smuzhiyun DA9063_ALARM_STATUS_TICK,
118*4882a593Smuzhiyun .rtc_tick_on_mask = DA9063_TICK_ON,
119*4882a593Smuzhiyun .rtc_ready_to_read_mask = DA9063_RTC_READ,
120*4882a593Smuzhiyun .rtc_count_sec_mask = DA9063_COUNT_SEC_MASK,
121*4882a593Smuzhiyun .rtc_count_min_mask = DA9063_COUNT_MIN_MASK,
122*4882a593Smuzhiyun .rtc_count_hour_mask = DA9063_COUNT_HOUR_MASK,
123*4882a593Smuzhiyun .rtc_count_day_mask = DA9063_COUNT_DAY_MASK,
124*4882a593Smuzhiyun .rtc_count_month_mask = DA9063_COUNT_MONTH_MASK,
125*4882a593Smuzhiyun .rtc_count_year_mask = DA9063_COUNT_YEAR_MASK,
126*4882a593Smuzhiyun /* ALARM CONFIG */
127*4882a593Smuzhiyun .rtc_data_start = RTC_SEC,
128*4882a593Smuzhiyun .rtc_alarm_len = RTC_DATA_LEN,
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun static const struct da9063_compatible_rtc_regmap da9062_aa_regs = {
132*4882a593Smuzhiyun /* REGS */
133*4882a593Smuzhiyun .rtc_enable_reg = DA9062AA_CONTROL_E,
134*4882a593Smuzhiyun .rtc_alarm_secs_reg = DA9062AA_ALARM_S,
135*4882a593Smuzhiyun .rtc_alarm_year_reg = DA9062AA_ALARM_Y,
136*4882a593Smuzhiyun .rtc_count_secs_reg = DA9062AA_COUNT_S,
137*4882a593Smuzhiyun .rtc_count_year_reg = DA9062AA_COUNT_Y,
138*4882a593Smuzhiyun .rtc_event_reg = DA9062AA_EVENT_A,
139*4882a593Smuzhiyun /* MASKS */
140*4882a593Smuzhiyun .rtc_enable_mask = DA9062AA_RTC_EN_MASK,
141*4882a593Smuzhiyun .rtc_crystal_mask = DA9062AA_CRYSTAL_MASK,
142*4882a593Smuzhiyun .rtc_enable_32k_crystal_reg = DA9062AA_EN_32K,
143*4882a593Smuzhiyun .rtc_event_alarm_mask = DA9062AA_M_ALARM_MASK,
144*4882a593Smuzhiyun .rtc_alarm_on_mask = DA9062AA_ALARM_ON_MASK,
145*4882a593Smuzhiyun .rtc_alarm_status_mask = (0x02 << 6),
146*4882a593Smuzhiyun .rtc_tick_on_mask = DA9062AA_TICK_ON_MASK,
147*4882a593Smuzhiyun .rtc_ready_to_read_mask = DA9062AA_RTC_READ_MASK,
148*4882a593Smuzhiyun .rtc_count_sec_mask = DA9062AA_COUNT_SEC_MASK,
149*4882a593Smuzhiyun .rtc_count_min_mask = DA9062AA_COUNT_MIN_MASK,
150*4882a593Smuzhiyun .rtc_count_hour_mask = DA9062AA_COUNT_HOUR_MASK,
151*4882a593Smuzhiyun .rtc_count_day_mask = DA9062AA_COUNT_DAY_MASK,
152*4882a593Smuzhiyun .rtc_count_month_mask = DA9062AA_COUNT_MONTH_MASK,
153*4882a593Smuzhiyun .rtc_count_year_mask = DA9062AA_COUNT_YEAR_MASK,
154*4882a593Smuzhiyun /* ALARM CONFIG */
155*4882a593Smuzhiyun .rtc_data_start = RTC_SEC,
156*4882a593Smuzhiyun .rtc_alarm_len = RTC_DATA_LEN,
157*4882a593Smuzhiyun };
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun static const struct of_device_id da9063_compatible_reg_id_table[] = {
160*4882a593Smuzhiyun { .compatible = "dlg,da9063-rtc", .data = &da9063_bb_regs },
161*4882a593Smuzhiyun { .compatible = "dlg,da9062-rtc", .data = &da9062_aa_regs },
162*4882a593Smuzhiyun { },
163*4882a593Smuzhiyun };
164*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, da9063_compatible_reg_id_table);
165*4882a593Smuzhiyun
da9063_data_to_tm(u8 * data,struct rtc_time * tm,struct da9063_compatible_rtc * rtc)166*4882a593Smuzhiyun static void da9063_data_to_tm(u8 *data, struct rtc_time *tm,
167*4882a593Smuzhiyun struct da9063_compatible_rtc *rtc)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun const struct da9063_compatible_rtc_regmap *config = rtc->config;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun tm->tm_sec = data[RTC_SEC] & config->rtc_count_sec_mask;
172*4882a593Smuzhiyun tm->tm_min = data[RTC_MIN] & config->rtc_count_min_mask;
173*4882a593Smuzhiyun tm->tm_hour = data[RTC_HOUR] & config->rtc_count_hour_mask;
174*4882a593Smuzhiyun tm->tm_mday = data[RTC_DAY] & config->rtc_count_day_mask;
175*4882a593Smuzhiyun tm->tm_mon = MONTHS_FROM_DA9063(data[RTC_MONTH] &
176*4882a593Smuzhiyun config->rtc_count_month_mask);
177*4882a593Smuzhiyun tm->tm_year = YEARS_FROM_DA9063(data[RTC_YEAR] &
178*4882a593Smuzhiyun config->rtc_count_year_mask);
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
da9063_tm_to_data(struct rtc_time * tm,u8 * data,struct da9063_compatible_rtc * rtc)181*4882a593Smuzhiyun static void da9063_tm_to_data(struct rtc_time *tm, u8 *data,
182*4882a593Smuzhiyun struct da9063_compatible_rtc *rtc)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun const struct da9063_compatible_rtc_regmap *config = rtc->config;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun data[RTC_SEC] = tm->tm_sec & config->rtc_count_sec_mask;
187*4882a593Smuzhiyun data[RTC_MIN] = tm->tm_min & config->rtc_count_min_mask;
188*4882a593Smuzhiyun data[RTC_HOUR] = tm->tm_hour & config->rtc_count_hour_mask;
189*4882a593Smuzhiyun data[RTC_DAY] = tm->tm_mday & config->rtc_count_day_mask;
190*4882a593Smuzhiyun data[RTC_MONTH] = MONTHS_TO_DA9063(tm->tm_mon) &
191*4882a593Smuzhiyun config->rtc_count_month_mask;
192*4882a593Smuzhiyun data[RTC_YEAR] = YEARS_TO_DA9063(tm->tm_year) &
193*4882a593Smuzhiyun config->rtc_count_year_mask;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
da9063_rtc_stop_alarm(struct device * dev)196*4882a593Smuzhiyun static int da9063_rtc_stop_alarm(struct device *dev)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun struct da9063_compatible_rtc *rtc = dev_get_drvdata(dev);
199*4882a593Smuzhiyun const struct da9063_compatible_rtc_regmap *config = rtc->config;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun return regmap_update_bits(rtc->regmap,
202*4882a593Smuzhiyun config->rtc_alarm_year_reg,
203*4882a593Smuzhiyun config->rtc_alarm_on_mask,
204*4882a593Smuzhiyun 0);
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
da9063_rtc_start_alarm(struct device * dev)207*4882a593Smuzhiyun static int da9063_rtc_start_alarm(struct device *dev)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun struct da9063_compatible_rtc *rtc = dev_get_drvdata(dev);
210*4882a593Smuzhiyun const struct da9063_compatible_rtc_regmap *config = rtc->config;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun return regmap_update_bits(rtc->regmap,
213*4882a593Smuzhiyun config->rtc_alarm_year_reg,
214*4882a593Smuzhiyun config->rtc_alarm_on_mask,
215*4882a593Smuzhiyun config->rtc_alarm_on_mask);
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun
da9063_rtc_read_time(struct device * dev,struct rtc_time * tm)218*4882a593Smuzhiyun static int da9063_rtc_read_time(struct device *dev, struct rtc_time *tm)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun struct da9063_compatible_rtc *rtc = dev_get_drvdata(dev);
221*4882a593Smuzhiyun const struct da9063_compatible_rtc_regmap *config = rtc->config;
222*4882a593Smuzhiyun unsigned long tm_secs;
223*4882a593Smuzhiyun unsigned long al_secs;
224*4882a593Smuzhiyun u8 data[RTC_DATA_LEN];
225*4882a593Smuzhiyun int ret;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun ret = regmap_bulk_read(rtc->regmap,
228*4882a593Smuzhiyun config->rtc_count_secs_reg,
229*4882a593Smuzhiyun data, RTC_DATA_LEN);
230*4882a593Smuzhiyun if (ret < 0) {
231*4882a593Smuzhiyun dev_err(dev, "Failed to read RTC time data: %d\n", ret);
232*4882a593Smuzhiyun return ret;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun if (!(data[RTC_SEC] & config->rtc_ready_to_read_mask)) {
236*4882a593Smuzhiyun dev_dbg(dev, "RTC not yet ready to be read by the host\n");
237*4882a593Smuzhiyun return -EINVAL;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun da9063_data_to_tm(data, tm, rtc);
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun tm_secs = rtc_tm_to_time64(tm);
243*4882a593Smuzhiyun al_secs = rtc_tm_to_time64(&rtc->alarm_time);
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun /* handle the rtc synchronisation delay */
246*4882a593Smuzhiyun if (rtc->rtc_sync == true && al_secs - tm_secs == 1)
247*4882a593Smuzhiyun memcpy(tm, &rtc->alarm_time, sizeof(struct rtc_time));
248*4882a593Smuzhiyun else
249*4882a593Smuzhiyun rtc->rtc_sync = false;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun return 0;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
da9063_rtc_set_time(struct device * dev,struct rtc_time * tm)254*4882a593Smuzhiyun static int da9063_rtc_set_time(struct device *dev, struct rtc_time *tm)
255*4882a593Smuzhiyun {
256*4882a593Smuzhiyun struct da9063_compatible_rtc *rtc = dev_get_drvdata(dev);
257*4882a593Smuzhiyun const struct da9063_compatible_rtc_regmap *config = rtc->config;
258*4882a593Smuzhiyun u8 data[RTC_DATA_LEN];
259*4882a593Smuzhiyun int ret;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun da9063_tm_to_data(tm, data, rtc);
262*4882a593Smuzhiyun ret = regmap_bulk_write(rtc->regmap,
263*4882a593Smuzhiyun config->rtc_count_secs_reg,
264*4882a593Smuzhiyun data, RTC_DATA_LEN);
265*4882a593Smuzhiyun if (ret < 0)
266*4882a593Smuzhiyun dev_err(dev, "Failed to set RTC time data: %d\n", ret);
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun return ret;
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
da9063_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)271*4882a593Smuzhiyun static int da9063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
272*4882a593Smuzhiyun {
273*4882a593Smuzhiyun struct da9063_compatible_rtc *rtc = dev_get_drvdata(dev);
274*4882a593Smuzhiyun const struct da9063_compatible_rtc_regmap *config = rtc->config;
275*4882a593Smuzhiyun u8 data[RTC_DATA_LEN];
276*4882a593Smuzhiyun int ret;
277*4882a593Smuzhiyun unsigned int val;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun data[RTC_SEC] = 0;
280*4882a593Smuzhiyun ret = regmap_bulk_read(rtc->regmap,
281*4882a593Smuzhiyun config->rtc_alarm_secs_reg,
282*4882a593Smuzhiyun &data[config->rtc_data_start],
283*4882a593Smuzhiyun config->rtc_alarm_len);
284*4882a593Smuzhiyun if (ret < 0)
285*4882a593Smuzhiyun return ret;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun da9063_data_to_tm(data, &alrm->time, rtc);
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun alrm->enabled = !!(data[RTC_YEAR] & config->rtc_alarm_on_mask);
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun ret = regmap_read(rtc->regmap,
292*4882a593Smuzhiyun config->rtc_event_reg,
293*4882a593Smuzhiyun &val);
294*4882a593Smuzhiyun if (ret < 0)
295*4882a593Smuzhiyun return ret;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun if (val & config->rtc_event_alarm_mask)
298*4882a593Smuzhiyun alrm->pending = 1;
299*4882a593Smuzhiyun else
300*4882a593Smuzhiyun alrm->pending = 0;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun return 0;
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
da9063_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)305*4882a593Smuzhiyun static int da9063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
306*4882a593Smuzhiyun {
307*4882a593Smuzhiyun struct da9063_compatible_rtc *rtc = dev_get_drvdata(dev);
308*4882a593Smuzhiyun const struct da9063_compatible_rtc_regmap *config = rtc->config;
309*4882a593Smuzhiyun u8 data[RTC_DATA_LEN];
310*4882a593Smuzhiyun int ret;
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun da9063_tm_to_data(&alrm->time, data, rtc);
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun ret = da9063_rtc_stop_alarm(dev);
315*4882a593Smuzhiyun if (ret < 0) {
316*4882a593Smuzhiyun dev_err(dev, "Failed to stop alarm: %d\n", ret);
317*4882a593Smuzhiyun return ret;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun ret = regmap_bulk_write(rtc->regmap,
321*4882a593Smuzhiyun config->rtc_alarm_secs_reg,
322*4882a593Smuzhiyun &data[config->rtc_data_start],
323*4882a593Smuzhiyun config->rtc_alarm_len);
324*4882a593Smuzhiyun if (ret < 0) {
325*4882a593Smuzhiyun dev_err(dev, "Failed to write alarm: %d\n", ret);
326*4882a593Smuzhiyun return ret;
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun da9063_data_to_tm(data, &rtc->alarm_time, rtc);
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun if (alrm->enabled) {
332*4882a593Smuzhiyun ret = da9063_rtc_start_alarm(dev);
333*4882a593Smuzhiyun if (ret < 0) {
334*4882a593Smuzhiyun dev_err(dev, "Failed to start alarm: %d\n", ret);
335*4882a593Smuzhiyun return ret;
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun return ret;
340*4882a593Smuzhiyun }
341*4882a593Smuzhiyun
da9063_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)342*4882a593Smuzhiyun static int da9063_rtc_alarm_irq_enable(struct device *dev,
343*4882a593Smuzhiyun unsigned int enabled)
344*4882a593Smuzhiyun {
345*4882a593Smuzhiyun if (enabled)
346*4882a593Smuzhiyun return da9063_rtc_start_alarm(dev);
347*4882a593Smuzhiyun else
348*4882a593Smuzhiyun return da9063_rtc_stop_alarm(dev);
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun
da9063_alarm_event(int irq,void * data)351*4882a593Smuzhiyun static irqreturn_t da9063_alarm_event(int irq, void *data)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun struct da9063_compatible_rtc *rtc = data;
354*4882a593Smuzhiyun const struct da9063_compatible_rtc_regmap *config = rtc->config;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun regmap_update_bits(rtc->regmap,
357*4882a593Smuzhiyun config->rtc_alarm_year_reg,
358*4882a593Smuzhiyun config->rtc_alarm_on_mask,
359*4882a593Smuzhiyun 0);
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun rtc->rtc_sync = true;
362*4882a593Smuzhiyun rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun return IRQ_HANDLED;
365*4882a593Smuzhiyun }
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun static const struct rtc_class_ops da9063_rtc_ops = {
368*4882a593Smuzhiyun .read_time = da9063_rtc_read_time,
369*4882a593Smuzhiyun .set_time = da9063_rtc_set_time,
370*4882a593Smuzhiyun .read_alarm = da9063_rtc_read_alarm,
371*4882a593Smuzhiyun .set_alarm = da9063_rtc_set_alarm,
372*4882a593Smuzhiyun .alarm_irq_enable = da9063_rtc_alarm_irq_enable,
373*4882a593Smuzhiyun };
374*4882a593Smuzhiyun
da9063_rtc_probe(struct platform_device * pdev)375*4882a593Smuzhiyun static int da9063_rtc_probe(struct platform_device *pdev)
376*4882a593Smuzhiyun {
377*4882a593Smuzhiyun struct da9063_compatible_rtc *rtc;
378*4882a593Smuzhiyun const struct da9063_compatible_rtc_regmap *config;
379*4882a593Smuzhiyun const struct of_device_id *match;
380*4882a593Smuzhiyun int irq_alarm;
381*4882a593Smuzhiyun u8 data[RTC_DATA_LEN];
382*4882a593Smuzhiyun int ret;
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun if (!pdev->dev.of_node)
385*4882a593Smuzhiyun return -ENXIO;
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun match = of_match_node(da9063_compatible_reg_id_table,
388*4882a593Smuzhiyun pdev->dev.of_node);
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
391*4882a593Smuzhiyun if (!rtc)
392*4882a593Smuzhiyun return -ENOMEM;
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun rtc->config = match->data;
395*4882a593Smuzhiyun if (of_device_is_compatible(pdev->dev.of_node, "dlg,da9063-rtc")) {
396*4882a593Smuzhiyun struct da9063 *chip = dev_get_drvdata(pdev->dev.parent);
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun if (chip->variant_code == PMIC_DA9063_AD)
399*4882a593Smuzhiyun rtc->config = &da9063_ad_regs;
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun rtc->regmap = dev_get_regmap(pdev->dev.parent, NULL);
403*4882a593Smuzhiyun if (!rtc->regmap) {
404*4882a593Smuzhiyun dev_warn(&pdev->dev, "Parent regmap unavailable.\n");
405*4882a593Smuzhiyun return -ENXIO;
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun config = rtc->config;
409*4882a593Smuzhiyun ret = regmap_update_bits(rtc->regmap,
410*4882a593Smuzhiyun config->rtc_enable_reg,
411*4882a593Smuzhiyun config->rtc_enable_mask,
412*4882a593Smuzhiyun config->rtc_enable_mask);
413*4882a593Smuzhiyun if (ret < 0) {
414*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to enable RTC\n");
415*4882a593Smuzhiyun return ret;
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun ret = regmap_update_bits(rtc->regmap,
419*4882a593Smuzhiyun config->rtc_enable_32k_crystal_reg,
420*4882a593Smuzhiyun config->rtc_crystal_mask,
421*4882a593Smuzhiyun config->rtc_crystal_mask);
422*4882a593Smuzhiyun if (ret < 0) {
423*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to run 32kHz oscillator\n");
424*4882a593Smuzhiyun return ret;
425*4882a593Smuzhiyun }
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun ret = regmap_update_bits(rtc->regmap,
428*4882a593Smuzhiyun config->rtc_alarm_secs_reg,
429*4882a593Smuzhiyun config->rtc_alarm_status_mask,
430*4882a593Smuzhiyun 0);
431*4882a593Smuzhiyun if (ret < 0) {
432*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to access RTC alarm register\n");
433*4882a593Smuzhiyun return ret;
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun ret = regmap_update_bits(rtc->regmap,
437*4882a593Smuzhiyun config->rtc_alarm_secs_reg,
438*4882a593Smuzhiyun DA9063_ALARM_STATUS_ALARM,
439*4882a593Smuzhiyun DA9063_ALARM_STATUS_ALARM);
440*4882a593Smuzhiyun if (ret < 0) {
441*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to access RTC alarm register\n");
442*4882a593Smuzhiyun return ret;
443*4882a593Smuzhiyun }
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun ret = regmap_update_bits(rtc->regmap,
446*4882a593Smuzhiyun config->rtc_alarm_year_reg,
447*4882a593Smuzhiyun config->rtc_tick_on_mask,
448*4882a593Smuzhiyun 0);
449*4882a593Smuzhiyun if (ret < 0) {
450*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to disable TICKs\n");
451*4882a593Smuzhiyun return ret;
452*4882a593Smuzhiyun }
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun data[RTC_SEC] = 0;
455*4882a593Smuzhiyun ret = regmap_bulk_read(rtc->regmap,
456*4882a593Smuzhiyun config->rtc_alarm_secs_reg,
457*4882a593Smuzhiyun &data[config->rtc_data_start],
458*4882a593Smuzhiyun config->rtc_alarm_len);
459*4882a593Smuzhiyun if (ret < 0) {
460*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to read initial alarm data: %d\n",
461*4882a593Smuzhiyun ret);
462*4882a593Smuzhiyun return ret;
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun platform_set_drvdata(pdev, rtc);
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
468*4882a593Smuzhiyun if (IS_ERR(rtc->rtc_dev))
469*4882a593Smuzhiyun return PTR_ERR(rtc->rtc_dev);
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun rtc->rtc_dev->ops = &da9063_rtc_ops;
472*4882a593Smuzhiyun rtc->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
473*4882a593Smuzhiyun rtc->rtc_dev->range_max = RTC_TIMESTAMP_END_2063;
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun da9063_data_to_tm(data, &rtc->alarm_time, rtc);
476*4882a593Smuzhiyun rtc->rtc_sync = false;
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun /*
479*4882a593Smuzhiyun * TODO: some models have alarms on a minute boundary but still support
480*4882a593Smuzhiyun * real hardware interrupts. Add this once the core supports it.
481*4882a593Smuzhiyun */
482*4882a593Smuzhiyun if (config->rtc_data_start != RTC_SEC)
483*4882a593Smuzhiyun rtc->rtc_dev->uie_unsupported = 1;
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun irq_alarm = platform_get_irq_byname(pdev, "ALARM");
486*4882a593Smuzhiyun if (irq_alarm < 0)
487*4882a593Smuzhiyun return irq_alarm;
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun ret = devm_request_threaded_irq(&pdev->dev, irq_alarm, NULL,
490*4882a593Smuzhiyun da9063_alarm_event,
491*4882a593Smuzhiyun IRQF_TRIGGER_LOW | IRQF_ONESHOT,
492*4882a593Smuzhiyun "ALARM", rtc);
493*4882a593Smuzhiyun if (ret)
494*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to request ALARM IRQ %d: %d\n",
495*4882a593Smuzhiyun irq_alarm, ret);
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun return rtc_register_device(rtc->rtc_dev);
498*4882a593Smuzhiyun }
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun static struct platform_driver da9063_rtc_driver = {
501*4882a593Smuzhiyun .probe = da9063_rtc_probe,
502*4882a593Smuzhiyun .driver = {
503*4882a593Smuzhiyun .name = DA9063_DRVNAME_RTC,
504*4882a593Smuzhiyun .of_match_table = da9063_compatible_reg_id_table,
505*4882a593Smuzhiyun },
506*4882a593Smuzhiyun };
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun module_platform_driver(da9063_rtc_driver);
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun MODULE_AUTHOR("S Twiss <stwiss.opensource@diasemi.com>");
511*4882a593Smuzhiyun MODULE_DESCRIPTION("Real time clock device driver for Dialog DA9063");
512*4882a593Smuzhiyun MODULE_LICENSE("GPL");
513*4882a593Smuzhiyun MODULE_ALIAS("platform:" DA9063_DRVNAME_RTC);
514