1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2007-2009 ST-Ericsson AB
4*4882a593Smuzhiyun * Real Time Clock interface for ST-Ericsson AB COH 901 331 RTC.
5*4882a593Smuzhiyun * Author: Linus Walleij <linus.walleij@stericsson.com>
6*4882a593Smuzhiyun * Based on rtc-pl031.c by Deepak Saxena <dsaxena@plexity.net>
7*4882a593Smuzhiyun * Copyright 2006 (c) MontaVista Software, Inc.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
12*4882a593Smuzhiyun #include <linux/rtc.h>
13*4882a593Smuzhiyun #include <linux/clk.h>
14*4882a593Smuzhiyun #include <linux/interrupt.h>
15*4882a593Smuzhiyun #include <linux/pm.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/io.h>
18*4882a593Smuzhiyun #include <linux/slab.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * Registers in the COH 901 331
22*4882a593Smuzhiyun */
23*4882a593Smuzhiyun /* Alarm value 32bit (R/W) */
24*4882a593Smuzhiyun #define COH901331_ALARM 0x00U
25*4882a593Smuzhiyun /* Used to set current time 32bit (R/W) */
26*4882a593Smuzhiyun #define COH901331_SET_TIME 0x04U
27*4882a593Smuzhiyun /* Indication if current time is valid 32bit (R/-) */
28*4882a593Smuzhiyun #define COH901331_VALID 0x08U
29*4882a593Smuzhiyun /* Read the current time 32bit (R/-) */
30*4882a593Smuzhiyun #define COH901331_CUR_TIME 0x0cU
31*4882a593Smuzhiyun /* Event register for the "alarm" interrupt */
32*4882a593Smuzhiyun #define COH901331_IRQ_EVENT 0x10U
33*4882a593Smuzhiyun /* Mask register for the "alarm" interrupt */
34*4882a593Smuzhiyun #define COH901331_IRQ_MASK 0x14U
35*4882a593Smuzhiyun /* Force register for the "alarm" interrupt */
36*4882a593Smuzhiyun #define COH901331_IRQ_FORCE 0x18U
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /*
39*4882a593Smuzhiyun * Reference to RTC block clock
40*4882a593Smuzhiyun * Notice that the frequent clk_enable()/clk_disable() on this
41*4882a593Smuzhiyun * clock is mainly to be able to turn on/off other clocks in the
42*4882a593Smuzhiyun * hierarchy as needed, the RTC clock is always on anyway.
43*4882a593Smuzhiyun */
44*4882a593Smuzhiyun struct coh901331_port {
45*4882a593Smuzhiyun struct rtc_device *rtc;
46*4882a593Smuzhiyun struct clk *clk;
47*4882a593Smuzhiyun void __iomem *virtbase;
48*4882a593Smuzhiyun int irq;
49*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
50*4882a593Smuzhiyun u32 irqmaskstore;
51*4882a593Smuzhiyun #endif
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
coh901331_interrupt(int irq,void * data)54*4882a593Smuzhiyun static irqreturn_t coh901331_interrupt(int irq, void *data)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun struct coh901331_port *rtap = data;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun clk_enable(rtap->clk);
59*4882a593Smuzhiyun /* Ack IRQ */
60*4882a593Smuzhiyun writel(1, rtap->virtbase + COH901331_IRQ_EVENT);
61*4882a593Smuzhiyun /*
62*4882a593Smuzhiyun * Disable the interrupt. This is necessary because
63*4882a593Smuzhiyun * the RTC lives on a lower-clocked line and will
64*4882a593Smuzhiyun * not release the IRQ line until after a few (slower)
65*4882a593Smuzhiyun * clock cycles. The interrupt will be re-enabled when
66*4882a593Smuzhiyun * a new alarm is set anyway.
67*4882a593Smuzhiyun */
68*4882a593Smuzhiyun writel(0, rtap->virtbase + COH901331_IRQ_MASK);
69*4882a593Smuzhiyun clk_disable(rtap->clk);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /* Set alarm flag */
72*4882a593Smuzhiyun rtc_update_irq(rtap->rtc, 1, RTC_AF);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun return IRQ_HANDLED;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
coh901331_read_time(struct device * dev,struct rtc_time * tm)77*4882a593Smuzhiyun static int coh901331_read_time(struct device *dev, struct rtc_time *tm)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun struct coh901331_port *rtap = dev_get_drvdata(dev);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun clk_enable(rtap->clk);
82*4882a593Smuzhiyun /* Check if the time is valid */
83*4882a593Smuzhiyun if (!readl(rtap->virtbase + COH901331_VALID)) {
84*4882a593Smuzhiyun clk_disable(rtap->clk);
85*4882a593Smuzhiyun return -EINVAL;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun rtc_time64_to_tm(readl(rtap->virtbase + COH901331_CUR_TIME), tm);
89*4882a593Smuzhiyun clk_disable(rtap->clk);
90*4882a593Smuzhiyun return 0;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
coh901331_set_time(struct device * dev,struct rtc_time * tm)93*4882a593Smuzhiyun static int coh901331_set_time(struct device *dev, struct rtc_time *tm)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun struct coh901331_port *rtap = dev_get_drvdata(dev);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun clk_enable(rtap->clk);
98*4882a593Smuzhiyun writel(rtc_tm_to_time64(tm), rtap->virtbase + COH901331_SET_TIME);
99*4882a593Smuzhiyun clk_disable(rtap->clk);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun return 0;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
coh901331_read_alarm(struct device * dev,struct rtc_wkalrm * alarm)104*4882a593Smuzhiyun static int coh901331_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun struct coh901331_port *rtap = dev_get_drvdata(dev);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun clk_enable(rtap->clk);
109*4882a593Smuzhiyun rtc_time64_to_tm(readl(rtap->virtbase + COH901331_ALARM), &alarm->time);
110*4882a593Smuzhiyun alarm->pending = readl(rtap->virtbase + COH901331_IRQ_EVENT) & 1U;
111*4882a593Smuzhiyun alarm->enabled = readl(rtap->virtbase + COH901331_IRQ_MASK) & 1U;
112*4882a593Smuzhiyun clk_disable(rtap->clk);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun return 0;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
coh901331_set_alarm(struct device * dev,struct rtc_wkalrm * alarm)117*4882a593Smuzhiyun static int coh901331_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun struct coh901331_port *rtap = dev_get_drvdata(dev);
120*4882a593Smuzhiyun unsigned long time = rtc_tm_to_time64(&alarm->time);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun clk_enable(rtap->clk);
123*4882a593Smuzhiyun writel(time, rtap->virtbase + COH901331_ALARM);
124*4882a593Smuzhiyun writel(alarm->enabled, rtap->virtbase + COH901331_IRQ_MASK);
125*4882a593Smuzhiyun clk_disable(rtap->clk);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun return 0;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
coh901331_alarm_irq_enable(struct device * dev,unsigned int enabled)130*4882a593Smuzhiyun static int coh901331_alarm_irq_enable(struct device *dev, unsigned int enabled)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun struct coh901331_port *rtap = dev_get_drvdata(dev);
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun clk_enable(rtap->clk);
135*4882a593Smuzhiyun if (enabled)
136*4882a593Smuzhiyun writel(1, rtap->virtbase + COH901331_IRQ_MASK);
137*4882a593Smuzhiyun else
138*4882a593Smuzhiyun writel(0, rtap->virtbase + COH901331_IRQ_MASK);
139*4882a593Smuzhiyun clk_disable(rtap->clk);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun return 0;
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun static const struct rtc_class_ops coh901331_ops = {
145*4882a593Smuzhiyun .read_time = coh901331_read_time,
146*4882a593Smuzhiyun .set_time = coh901331_set_time,
147*4882a593Smuzhiyun .read_alarm = coh901331_read_alarm,
148*4882a593Smuzhiyun .set_alarm = coh901331_set_alarm,
149*4882a593Smuzhiyun .alarm_irq_enable = coh901331_alarm_irq_enable,
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun
coh901331_remove(struct platform_device * pdev)152*4882a593Smuzhiyun static int __exit coh901331_remove(struct platform_device *pdev)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun struct coh901331_port *rtap = platform_get_drvdata(pdev);
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun if (rtap)
157*4882a593Smuzhiyun clk_unprepare(rtap->clk);
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun return 0;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun
coh901331_probe(struct platform_device * pdev)163*4882a593Smuzhiyun static int __init coh901331_probe(struct platform_device *pdev)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun int ret;
166*4882a593Smuzhiyun struct coh901331_port *rtap;
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun rtap = devm_kzalloc(&pdev->dev,
169*4882a593Smuzhiyun sizeof(struct coh901331_port), GFP_KERNEL);
170*4882a593Smuzhiyun if (!rtap)
171*4882a593Smuzhiyun return -ENOMEM;
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun rtap->virtbase = devm_platform_ioremap_resource(pdev, 0);
174*4882a593Smuzhiyun if (IS_ERR(rtap->virtbase))
175*4882a593Smuzhiyun return PTR_ERR(rtap->virtbase);
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun rtap->irq = platform_get_irq(pdev, 0);
178*4882a593Smuzhiyun if (devm_request_irq(&pdev->dev, rtap->irq, coh901331_interrupt, 0,
179*4882a593Smuzhiyun "RTC COH 901 331 Alarm", rtap))
180*4882a593Smuzhiyun return -EIO;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun rtap->clk = devm_clk_get(&pdev->dev, NULL);
183*4882a593Smuzhiyun if (IS_ERR(rtap->clk)) {
184*4882a593Smuzhiyun ret = PTR_ERR(rtap->clk);
185*4882a593Smuzhiyun dev_err(&pdev->dev, "could not get clock\n");
186*4882a593Smuzhiyun return ret;
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun rtap->rtc = devm_rtc_allocate_device(&pdev->dev);
190*4882a593Smuzhiyun if (IS_ERR(rtap->rtc))
191*4882a593Smuzhiyun return PTR_ERR(rtap->rtc);
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun rtap->rtc->ops = &coh901331_ops;
194*4882a593Smuzhiyun rtap->rtc->range_max = U32_MAX;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun /* We enable/disable the clock only to assure it works */
197*4882a593Smuzhiyun ret = clk_prepare_enable(rtap->clk);
198*4882a593Smuzhiyun if (ret) {
199*4882a593Smuzhiyun dev_err(&pdev->dev, "could not enable clock\n");
200*4882a593Smuzhiyun return ret;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun clk_disable(rtap->clk);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun platform_set_drvdata(pdev, rtap);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun ret = rtc_register_device(rtap->rtc);
207*4882a593Smuzhiyun if (ret)
208*4882a593Smuzhiyun goto out_no_rtc;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun return 0;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun out_no_rtc:
213*4882a593Smuzhiyun clk_unprepare(rtap->clk);
214*4882a593Smuzhiyun return ret;
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
coh901331_suspend(struct device * dev)218*4882a593Smuzhiyun static int coh901331_suspend(struct device *dev)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun struct coh901331_port *rtap = dev_get_drvdata(dev);
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun /*
223*4882a593Smuzhiyun * If this RTC alarm will be used for waking the system up,
224*4882a593Smuzhiyun * don't disable it of course. Else we just disable the alarm
225*4882a593Smuzhiyun * and await suspension.
226*4882a593Smuzhiyun */
227*4882a593Smuzhiyun if (device_may_wakeup(dev)) {
228*4882a593Smuzhiyun enable_irq_wake(rtap->irq);
229*4882a593Smuzhiyun } else {
230*4882a593Smuzhiyun clk_enable(rtap->clk);
231*4882a593Smuzhiyun rtap->irqmaskstore = readl(rtap->virtbase + COH901331_IRQ_MASK);
232*4882a593Smuzhiyun writel(0, rtap->virtbase + COH901331_IRQ_MASK);
233*4882a593Smuzhiyun clk_disable(rtap->clk);
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun clk_unprepare(rtap->clk);
236*4882a593Smuzhiyun return 0;
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun
coh901331_resume(struct device * dev)239*4882a593Smuzhiyun static int coh901331_resume(struct device *dev)
240*4882a593Smuzhiyun {
241*4882a593Smuzhiyun int ret;
242*4882a593Smuzhiyun struct coh901331_port *rtap = dev_get_drvdata(dev);
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun ret = clk_prepare(rtap->clk);
245*4882a593Smuzhiyun if (ret)
246*4882a593Smuzhiyun return ret;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun if (device_may_wakeup(dev)) {
249*4882a593Smuzhiyun disable_irq_wake(rtap->irq);
250*4882a593Smuzhiyun } else {
251*4882a593Smuzhiyun clk_enable(rtap->clk);
252*4882a593Smuzhiyun writel(rtap->irqmaskstore, rtap->virtbase + COH901331_IRQ_MASK);
253*4882a593Smuzhiyun clk_disable(rtap->clk);
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun return 0;
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun #endif
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(coh901331_pm_ops, coh901331_suspend, coh901331_resume);
260*4882a593Smuzhiyun
coh901331_shutdown(struct platform_device * pdev)261*4882a593Smuzhiyun static void coh901331_shutdown(struct platform_device *pdev)
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun struct coh901331_port *rtap = platform_get_drvdata(pdev);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun clk_enable(rtap->clk);
266*4882a593Smuzhiyun writel(0, rtap->virtbase + COH901331_IRQ_MASK);
267*4882a593Smuzhiyun clk_disable_unprepare(rtap->clk);
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun static const struct of_device_id coh901331_dt_match[] = {
271*4882a593Smuzhiyun { .compatible = "stericsson,coh901331" },
272*4882a593Smuzhiyun {},
273*4882a593Smuzhiyun };
274*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, coh901331_dt_match);
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun static struct platform_driver coh901331_driver = {
277*4882a593Smuzhiyun .driver = {
278*4882a593Smuzhiyun .name = "rtc-coh901331",
279*4882a593Smuzhiyun .pm = &coh901331_pm_ops,
280*4882a593Smuzhiyun .of_match_table = coh901331_dt_match,
281*4882a593Smuzhiyun },
282*4882a593Smuzhiyun .remove = __exit_p(coh901331_remove),
283*4882a593Smuzhiyun .shutdown = coh901331_shutdown,
284*4882a593Smuzhiyun };
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun module_platform_driver_probe(coh901331_driver, coh901331_probe);
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
289*4882a593Smuzhiyun MODULE_DESCRIPTION("ST-Ericsson AB COH 901 331 RTC Driver");
290*4882a593Smuzhiyun MODULE_LICENSE("GPL");
291