1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (C) 2018 ROHM Semiconductors
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // RTC driver for ROHM BD70528 PMIC
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/bcd.h>
8*4882a593Smuzhiyun #include <linux/mfd/rohm-bd70528.h>
9*4882a593Smuzhiyun #include <linux/mfd/rohm-bd71828.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/regmap.h>
14*4882a593Smuzhiyun #include <linux/rtc.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /*
17*4882a593Smuzhiyun * We read regs RTC_SEC => RTC_YEAR
18*4882a593Smuzhiyun * this struct is ordered according to chip registers.
19*4882a593Smuzhiyun * Keep it u8 only (or packed) to avoid padding issues.
20*4882a593Smuzhiyun */
21*4882a593Smuzhiyun struct bd70528_rtc_day {
22*4882a593Smuzhiyun u8 sec;
23*4882a593Smuzhiyun u8 min;
24*4882a593Smuzhiyun u8 hour;
25*4882a593Smuzhiyun } __packed;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun struct bd70528_rtc_data {
28*4882a593Smuzhiyun struct bd70528_rtc_day time;
29*4882a593Smuzhiyun u8 week;
30*4882a593Smuzhiyun u8 day;
31*4882a593Smuzhiyun u8 month;
32*4882a593Smuzhiyun u8 year;
33*4882a593Smuzhiyun } __packed;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun struct bd70528_rtc_wake {
36*4882a593Smuzhiyun struct bd70528_rtc_day time;
37*4882a593Smuzhiyun u8 ctrl;
38*4882a593Smuzhiyun } __packed;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun struct bd71828_rtc_alm {
41*4882a593Smuzhiyun struct bd70528_rtc_data alm0;
42*4882a593Smuzhiyun struct bd70528_rtc_data alm1;
43*4882a593Smuzhiyun u8 alm_mask;
44*4882a593Smuzhiyun u8 alm1_mask;
45*4882a593Smuzhiyun } __packed;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun struct bd70528_rtc_alm {
48*4882a593Smuzhiyun struct bd70528_rtc_data data;
49*4882a593Smuzhiyun u8 alm_mask;
50*4882a593Smuzhiyun u8 alm_repeat;
51*4882a593Smuzhiyun } __packed;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun struct bd70528_rtc {
54*4882a593Smuzhiyun struct rohm_regmap_dev *parent;
55*4882a593Smuzhiyun struct device *dev;
56*4882a593Smuzhiyun u8 reg_time_start;
57*4882a593Smuzhiyun bool has_rtc_timers;
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
bd70528_set_wake(struct rohm_regmap_dev * bd70528,int enable,int * old_state)60*4882a593Smuzhiyun static int bd70528_set_wake(struct rohm_regmap_dev *bd70528,
61*4882a593Smuzhiyun int enable, int *old_state)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun int ret;
64*4882a593Smuzhiyun unsigned int ctrl_reg;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun ret = regmap_read(bd70528->regmap, BD70528_REG_WAKE_EN, &ctrl_reg);
67*4882a593Smuzhiyun if (ret)
68*4882a593Smuzhiyun return ret;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun if (old_state) {
71*4882a593Smuzhiyun if (ctrl_reg & BD70528_MASK_WAKE_EN)
72*4882a593Smuzhiyun *old_state |= BD70528_WAKE_STATE_BIT;
73*4882a593Smuzhiyun else
74*4882a593Smuzhiyun *old_state &= ~BD70528_WAKE_STATE_BIT;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun if (!enable == !(*old_state & BD70528_WAKE_STATE_BIT))
77*4882a593Smuzhiyun return 0;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun if (enable)
81*4882a593Smuzhiyun ctrl_reg |= BD70528_MASK_WAKE_EN;
82*4882a593Smuzhiyun else
83*4882a593Smuzhiyun ctrl_reg &= ~BD70528_MASK_WAKE_EN;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun return regmap_write(bd70528->regmap, BD70528_REG_WAKE_EN,
86*4882a593Smuzhiyun ctrl_reg);
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
bd70528_set_elapsed_tmr(struct rohm_regmap_dev * bd70528,int enable,int * old_state)89*4882a593Smuzhiyun static int bd70528_set_elapsed_tmr(struct rohm_regmap_dev *bd70528,
90*4882a593Smuzhiyun int enable, int *old_state)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun int ret;
93*4882a593Smuzhiyun unsigned int ctrl_reg;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /*
96*4882a593Smuzhiyun * TBD
97*4882a593Smuzhiyun * What is the purpose of elapsed timer ?
98*4882a593Smuzhiyun * Is the timeout registers counting down, or is the disable - re-enable
99*4882a593Smuzhiyun * going to restart the elapsed-time counting? If counting is restarted
100*4882a593Smuzhiyun * the timeout should be decreased by the amount of time that has
101*4882a593Smuzhiyun * elapsed since starting the timer. Maybe we should store the monotonic
102*4882a593Smuzhiyun * clock value when timer is started so that if RTC is set while timer
103*4882a593Smuzhiyun * is armed we could do the compensation. This is a hack if RTC/system
104*4882a593Smuzhiyun * clk are drifting. OTOH, RTC controlled via I2C is in any case
105*4882a593Smuzhiyun * inaccurate...
106*4882a593Smuzhiyun */
107*4882a593Smuzhiyun ret = regmap_read(bd70528->regmap, BD70528_REG_ELAPSED_TIMER_EN,
108*4882a593Smuzhiyun &ctrl_reg);
109*4882a593Smuzhiyun if (ret)
110*4882a593Smuzhiyun return ret;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun if (old_state) {
113*4882a593Smuzhiyun if (ctrl_reg & BD70528_MASK_ELAPSED_TIMER_EN)
114*4882a593Smuzhiyun *old_state |= BD70528_ELAPSED_STATE_BIT;
115*4882a593Smuzhiyun else
116*4882a593Smuzhiyun *old_state &= ~BD70528_ELAPSED_STATE_BIT;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun if ((!enable) == (!(*old_state & BD70528_ELAPSED_STATE_BIT)))
119*4882a593Smuzhiyun return 0;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun if (enable)
123*4882a593Smuzhiyun ctrl_reg |= BD70528_MASK_ELAPSED_TIMER_EN;
124*4882a593Smuzhiyun else
125*4882a593Smuzhiyun ctrl_reg &= ~BD70528_MASK_ELAPSED_TIMER_EN;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun return regmap_write(bd70528->regmap, BD70528_REG_ELAPSED_TIMER_EN,
128*4882a593Smuzhiyun ctrl_reg);
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
bd70528_set_rtc_based_timers(struct bd70528_rtc * r,int new_state,int * old_state)131*4882a593Smuzhiyun static int bd70528_set_rtc_based_timers(struct bd70528_rtc *r, int new_state,
132*4882a593Smuzhiyun int *old_state)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun int ret;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun ret = bd70528_wdt_set(r->parent, new_state & BD70528_WDT_STATE_BIT,
137*4882a593Smuzhiyun old_state);
138*4882a593Smuzhiyun if (ret) {
139*4882a593Smuzhiyun dev_err(r->dev,
140*4882a593Smuzhiyun "Failed to disable WDG for RTC setting (%d)\n", ret);
141*4882a593Smuzhiyun return ret;
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun ret = bd70528_set_elapsed_tmr(r->parent,
144*4882a593Smuzhiyun new_state & BD70528_ELAPSED_STATE_BIT,
145*4882a593Smuzhiyun old_state);
146*4882a593Smuzhiyun if (ret) {
147*4882a593Smuzhiyun dev_err(r->dev,
148*4882a593Smuzhiyun "Failed to disable 'elapsed timer' for RTC setting\n");
149*4882a593Smuzhiyun return ret;
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun ret = bd70528_set_wake(r->parent, new_state & BD70528_WAKE_STATE_BIT,
152*4882a593Smuzhiyun old_state);
153*4882a593Smuzhiyun if (ret) {
154*4882a593Smuzhiyun dev_err(r->dev,
155*4882a593Smuzhiyun "Failed to disable 'wake timer' for RTC setting\n");
156*4882a593Smuzhiyun return ret;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun return ret;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
bd70528_re_enable_rtc_based_timers(struct bd70528_rtc * r,int old_state)162*4882a593Smuzhiyun static int bd70528_re_enable_rtc_based_timers(struct bd70528_rtc *r,
163*4882a593Smuzhiyun int old_state)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun if (!r->has_rtc_timers)
166*4882a593Smuzhiyun return 0;
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun return bd70528_set_rtc_based_timers(r, old_state, NULL);
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
bd70528_disable_rtc_based_timers(struct bd70528_rtc * r,int * old_state)171*4882a593Smuzhiyun static int bd70528_disable_rtc_based_timers(struct bd70528_rtc *r,
172*4882a593Smuzhiyun int *old_state)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun if (!r->has_rtc_timers)
175*4882a593Smuzhiyun return 0;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun return bd70528_set_rtc_based_timers(r, 0, old_state);
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun
tmday2rtc(struct rtc_time * t,struct bd70528_rtc_day * d)180*4882a593Smuzhiyun static inline void tmday2rtc(struct rtc_time *t, struct bd70528_rtc_day *d)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun d->sec &= ~BD70528_MASK_RTC_SEC;
183*4882a593Smuzhiyun d->min &= ~BD70528_MASK_RTC_MINUTE;
184*4882a593Smuzhiyun d->hour &= ~BD70528_MASK_RTC_HOUR;
185*4882a593Smuzhiyun d->sec |= bin2bcd(t->tm_sec);
186*4882a593Smuzhiyun d->min |= bin2bcd(t->tm_min);
187*4882a593Smuzhiyun d->hour |= bin2bcd(t->tm_hour);
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
tm2rtc(struct rtc_time * t,struct bd70528_rtc_data * r)190*4882a593Smuzhiyun static inline void tm2rtc(struct rtc_time *t, struct bd70528_rtc_data *r)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun r->day &= ~BD70528_MASK_RTC_DAY;
193*4882a593Smuzhiyun r->week &= ~BD70528_MASK_RTC_WEEK;
194*4882a593Smuzhiyun r->month &= ~BD70528_MASK_RTC_MONTH;
195*4882a593Smuzhiyun /*
196*4882a593Smuzhiyun * PM and 24H bits are not used by Wake - thus we clear them
197*4882a593Smuzhiyun * here and not in tmday2rtc() which is also used by wake.
198*4882a593Smuzhiyun */
199*4882a593Smuzhiyun r->time.hour &= ~(BD70528_MASK_RTC_HOUR_PM | BD70528_MASK_RTC_HOUR_24H);
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun tmday2rtc(t, &r->time);
202*4882a593Smuzhiyun /*
203*4882a593Smuzhiyun * We do always set time in 24H mode.
204*4882a593Smuzhiyun */
205*4882a593Smuzhiyun r->time.hour |= BD70528_MASK_RTC_HOUR_24H;
206*4882a593Smuzhiyun r->day |= bin2bcd(t->tm_mday);
207*4882a593Smuzhiyun r->week |= bin2bcd(t->tm_wday);
208*4882a593Smuzhiyun r->month |= bin2bcd(t->tm_mon + 1);
209*4882a593Smuzhiyun r->year = bin2bcd(t->tm_year - 100);
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun
rtc2tm(struct bd70528_rtc_data * r,struct rtc_time * t)212*4882a593Smuzhiyun static inline void rtc2tm(struct bd70528_rtc_data *r, struct rtc_time *t)
213*4882a593Smuzhiyun {
214*4882a593Smuzhiyun t->tm_sec = bcd2bin(r->time.sec & BD70528_MASK_RTC_SEC);
215*4882a593Smuzhiyun t->tm_min = bcd2bin(r->time.min & BD70528_MASK_RTC_MINUTE);
216*4882a593Smuzhiyun t->tm_hour = bcd2bin(r->time.hour & BD70528_MASK_RTC_HOUR);
217*4882a593Smuzhiyun /*
218*4882a593Smuzhiyun * If RTC is in 12H mode, then bit BD70528_MASK_RTC_HOUR_PM
219*4882a593Smuzhiyun * is not BCD value but tells whether it is AM or PM
220*4882a593Smuzhiyun */
221*4882a593Smuzhiyun if (!(r->time.hour & BD70528_MASK_RTC_HOUR_24H)) {
222*4882a593Smuzhiyun t->tm_hour %= 12;
223*4882a593Smuzhiyun if (r->time.hour & BD70528_MASK_RTC_HOUR_PM)
224*4882a593Smuzhiyun t->tm_hour += 12;
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun t->tm_mday = bcd2bin(r->day & BD70528_MASK_RTC_DAY);
227*4882a593Smuzhiyun t->tm_mon = bcd2bin(r->month & BD70528_MASK_RTC_MONTH) - 1;
228*4882a593Smuzhiyun t->tm_year = 100 + bcd2bin(r->year & BD70528_MASK_RTC_YEAR);
229*4882a593Smuzhiyun t->tm_wday = bcd2bin(r->week & BD70528_MASK_RTC_WEEK);
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun
bd71828_set_alarm(struct device * dev,struct rtc_wkalrm * a)232*4882a593Smuzhiyun static int bd71828_set_alarm(struct device *dev, struct rtc_wkalrm *a)
233*4882a593Smuzhiyun {
234*4882a593Smuzhiyun int ret;
235*4882a593Smuzhiyun struct bd71828_rtc_alm alm;
236*4882a593Smuzhiyun struct bd70528_rtc *r = dev_get_drvdata(dev);
237*4882a593Smuzhiyun struct rohm_regmap_dev *parent = r->parent;
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun ret = regmap_bulk_read(parent->regmap, BD71828_REG_RTC_ALM_START,
240*4882a593Smuzhiyun &alm, sizeof(alm));
241*4882a593Smuzhiyun if (ret) {
242*4882a593Smuzhiyun dev_err(dev, "Failed to read alarm regs\n");
243*4882a593Smuzhiyun return ret;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun tm2rtc(&a->time, &alm.alm0);
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun if (!a->enabled)
249*4882a593Smuzhiyun alm.alm_mask &= ~BD70528_MASK_ALM_EN;
250*4882a593Smuzhiyun else
251*4882a593Smuzhiyun alm.alm_mask |= BD70528_MASK_ALM_EN;
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun ret = regmap_bulk_write(parent->regmap, BD71828_REG_RTC_ALM_START,
254*4882a593Smuzhiyun &alm, sizeof(alm));
255*4882a593Smuzhiyun if (ret)
256*4882a593Smuzhiyun dev_err(dev, "Failed to set alarm time\n");
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun return ret;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
bd70528_set_alarm(struct device * dev,struct rtc_wkalrm * a)262*4882a593Smuzhiyun static int bd70528_set_alarm(struct device *dev, struct rtc_wkalrm *a)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun struct bd70528_rtc_wake wake;
265*4882a593Smuzhiyun struct bd70528_rtc_alm alm;
266*4882a593Smuzhiyun int ret;
267*4882a593Smuzhiyun struct bd70528_rtc *r = dev_get_drvdata(dev);
268*4882a593Smuzhiyun struct rohm_regmap_dev *parent = r->parent;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun ret = regmap_bulk_read(parent->regmap, BD70528_REG_RTC_WAKE_START,
271*4882a593Smuzhiyun &wake, sizeof(wake));
272*4882a593Smuzhiyun if (ret) {
273*4882a593Smuzhiyun dev_err(dev, "Failed to read wake regs\n");
274*4882a593Smuzhiyun return ret;
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun ret = regmap_bulk_read(parent->regmap, BD70528_REG_RTC_ALM_START,
278*4882a593Smuzhiyun &alm, sizeof(alm));
279*4882a593Smuzhiyun if (ret) {
280*4882a593Smuzhiyun dev_err(dev, "Failed to read alarm regs\n");
281*4882a593Smuzhiyun return ret;
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun tm2rtc(&a->time, &alm.data);
285*4882a593Smuzhiyun tmday2rtc(&a->time, &wake.time);
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun if (a->enabled) {
288*4882a593Smuzhiyun alm.alm_mask &= ~BD70528_MASK_ALM_EN;
289*4882a593Smuzhiyun wake.ctrl |= BD70528_MASK_WAKE_EN;
290*4882a593Smuzhiyun } else {
291*4882a593Smuzhiyun alm.alm_mask |= BD70528_MASK_ALM_EN;
292*4882a593Smuzhiyun wake.ctrl &= ~BD70528_MASK_WAKE_EN;
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun ret = regmap_bulk_write(parent->regmap,
296*4882a593Smuzhiyun BD70528_REG_RTC_WAKE_START, &wake,
297*4882a593Smuzhiyun sizeof(wake));
298*4882a593Smuzhiyun if (ret) {
299*4882a593Smuzhiyun dev_err(dev, "Failed to set wake time\n");
300*4882a593Smuzhiyun return ret;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun ret = regmap_bulk_write(parent->regmap, BD70528_REG_RTC_ALM_START,
303*4882a593Smuzhiyun &alm, sizeof(alm));
304*4882a593Smuzhiyun if (ret)
305*4882a593Smuzhiyun dev_err(dev, "Failed to set alarm time\n");
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun return ret;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
bd71828_read_alarm(struct device * dev,struct rtc_wkalrm * a)310*4882a593Smuzhiyun static int bd71828_read_alarm(struct device *dev, struct rtc_wkalrm *a)
311*4882a593Smuzhiyun {
312*4882a593Smuzhiyun int ret;
313*4882a593Smuzhiyun struct bd71828_rtc_alm alm;
314*4882a593Smuzhiyun struct bd70528_rtc *r = dev_get_drvdata(dev);
315*4882a593Smuzhiyun struct rohm_regmap_dev *parent = r->parent;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun ret = regmap_bulk_read(parent->regmap, BD71828_REG_RTC_ALM_START,
318*4882a593Smuzhiyun &alm, sizeof(alm));
319*4882a593Smuzhiyun if (ret) {
320*4882a593Smuzhiyun dev_err(dev, "Failed to read alarm regs\n");
321*4882a593Smuzhiyun return ret;
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun rtc2tm(&alm.alm0, &a->time);
325*4882a593Smuzhiyun a->time.tm_mday = -1;
326*4882a593Smuzhiyun a->time.tm_mon = -1;
327*4882a593Smuzhiyun a->time.tm_year = -1;
328*4882a593Smuzhiyun a->enabled = !!(alm.alm_mask & BD70528_MASK_ALM_EN);
329*4882a593Smuzhiyun a->pending = 0;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun return 0;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun
bd70528_read_alarm(struct device * dev,struct rtc_wkalrm * a)334*4882a593Smuzhiyun static int bd70528_read_alarm(struct device *dev, struct rtc_wkalrm *a)
335*4882a593Smuzhiyun {
336*4882a593Smuzhiyun struct bd70528_rtc_alm alm;
337*4882a593Smuzhiyun int ret;
338*4882a593Smuzhiyun struct bd70528_rtc *r = dev_get_drvdata(dev);
339*4882a593Smuzhiyun struct rohm_regmap_dev *parent = r->parent;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun ret = regmap_bulk_read(parent->regmap, BD70528_REG_RTC_ALM_START,
342*4882a593Smuzhiyun &alm, sizeof(alm));
343*4882a593Smuzhiyun if (ret) {
344*4882a593Smuzhiyun dev_err(dev, "Failed to read alarm regs\n");
345*4882a593Smuzhiyun return ret;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun rtc2tm(&alm.data, &a->time);
349*4882a593Smuzhiyun a->time.tm_mday = -1;
350*4882a593Smuzhiyun a->time.tm_mon = -1;
351*4882a593Smuzhiyun a->time.tm_year = -1;
352*4882a593Smuzhiyun a->enabled = !(alm.alm_mask & BD70528_MASK_ALM_EN);
353*4882a593Smuzhiyun a->pending = 0;
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun return 0;
356*4882a593Smuzhiyun }
357*4882a593Smuzhiyun
bd70528_set_time_locked(struct device * dev,struct rtc_time * t)358*4882a593Smuzhiyun static int bd70528_set_time_locked(struct device *dev, struct rtc_time *t)
359*4882a593Smuzhiyun {
360*4882a593Smuzhiyun int ret, tmpret, old_states;
361*4882a593Smuzhiyun struct bd70528_rtc_data rtc_data;
362*4882a593Smuzhiyun struct bd70528_rtc *r = dev_get_drvdata(dev);
363*4882a593Smuzhiyun struct rohm_regmap_dev *parent = r->parent;
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun ret = bd70528_disable_rtc_based_timers(r, &old_states);
366*4882a593Smuzhiyun if (ret)
367*4882a593Smuzhiyun return ret;
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun tmpret = regmap_bulk_read(parent->regmap,
370*4882a593Smuzhiyun r->reg_time_start, &rtc_data,
371*4882a593Smuzhiyun sizeof(rtc_data));
372*4882a593Smuzhiyun if (tmpret) {
373*4882a593Smuzhiyun dev_err(dev, "Failed to read RTC time registers\n");
374*4882a593Smuzhiyun goto renable_out;
375*4882a593Smuzhiyun }
376*4882a593Smuzhiyun tm2rtc(t, &rtc_data);
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun tmpret = regmap_bulk_write(parent->regmap,
379*4882a593Smuzhiyun r->reg_time_start, &rtc_data,
380*4882a593Smuzhiyun sizeof(rtc_data));
381*4882a593Smuzhiyun if (tmpret) {
382*4882a593Smuzhiyun dev_err(dev, "Failed to set RTC time\n");
383*4882a593Smuzhiyun goto renable_out;
384*4882a593Smuzhiyun }
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun renable_out:
387*4882a593Smuzhiyun ret = bd70528_re_enable_rtc_based_timers(r, old_states);
388*4882a593Smuzhiyun if (tmpret)
389*4882a593Smuzhiyun ret = tmpret;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun return ret;
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun
bd71828_set_time(struct device * dev,struct rtc_time * t)394*4882a593Smuzhiyun static int bd71828_set_time(struct device *dev, struct rtc_time *t)
395*4882a593Smuzhiyun {
396*4882a593Smuzhiyun return bd70528_set_time_locked(dev, t);
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun
bd70528_set_time(struct device * dev,struct rtc_time * t)399*4882a593Smuzhiyun static int bd70528_set_time(struct device *dev, struct rtc_time *t)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun int ret;
402*4882a593Smuzhiyun struct bd70528_rtc *r = dev_get_drvdata(dev);
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun bd70528_wdt_lock(r->parent);
405*4882a593Smuzhiyun ret = bd70528_set_time_locked(dev, t);
406*4882a593Smuzhiyun bd70528_wdt_unlock(r->parent);
407*4882a593Smuzhiyun return ret;
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun
bd70528_get_time(struct device * dev,struct rtc_time * t)410*4882a593Smuzhiyun static int bd70528_get_time(struct device *dev, struct rtc_time *t)
411*4882a593Smuzhiyun {
412*4882a593Smuzhiyun struct bd70528_rtc *r = dev_get_drvdata(dev);
413*4882a593Smuzhiyun struct rohm_regmap_dev *parent = r->parent;
414*4882a593Smuzhiyun struct bd70528_rtc_data rtc_data;
415*4882a593Smuzhiyun int ret;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun /* read the RTC date and time registers all at once */
418*4882a593Smuzhiyun ret = regmap_bulk_read(parent->regmap,
419*4882a593Smuzhiyun r->reg_time_start, &rtc_data,
420*4882a593Smuzhiyun sizeof(rtc_data));
421*4882a593Smuzhiyun if (ret) {
422*4882a593Smuzhiyun dev_err(dev, "Failed to read RTC time (err %d)\n", ret);
423*4882a593Smuzhiyun return ret;
424*4882a593Smuzhiyun }
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun rtc2tm(&rtc_data, t);
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun return 0;
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun
bd70528_alm_enable(struct device * dev,unsigned int enabled)431*4882a593Smuzhiyun static int bd70528_alm_enable(struct device *dev, unsigned int enabled)
432*4882a593Smuzhiyun {
433*4882a593Smuzhiyun int ret;
434*4882a593Smuzhiyun unsigned int enableval = BD70528_MASK_ALM_EN;
435*4882a593Smuzhiyun struct bd70528_rtc *r = dev_get_drvdata(dev);
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun if (enabled)
438*4882a593Smuzhiyun enableval = 0;
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun bd70528_wdt_lock(r->parent);
441*4882a593Smuzhiyun ret = bd70528_set_wake(r->parent, enabled, NULL);
442*4882a593Smuzhiyun if (ret) {
443*4882a593Smuzhiyun dev_err(dev, "Failed to change wake state\n");
444*4882a593Smuzhiyun goto out_unlock;
445*4882a593Smuzhiyun }
446*4882a593Smuzhiyun ret = regmap_update_bits(r->parent->regmap, BD70528_REG_RTC_ALM_MASK,
447*4882a593Smuzhiyun BD70528_MASK_ALM_EN, enableval);
448*4882a593Smuzhiyun if (ret)
449*4882a593Smuzhiyun dev_err(dev, "Failed to change alarm state\n");
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun out_unlock:
452*4882a593Smuzhiyun bd70528_wdt_unlock(r->parent);
453*4882a593Smuzhiyun return ret;
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun
bd71828_alm_enable(struct device * dev,unsigned int enabled)456*4882a593Smuzhiyun static int bd71828_alm_enable(struct device *dev, unsigned int enabled)
457*4882a593Smuzhiyun {
458*4882a593Smuzhiyun int ret;
459*4882a593Smuzhiyun struct bd70528_rtc *r = dev_get_drvdata(dev);
460*4882a593Smuzhiyun unsigned int enableval = BD70528_MASK_ALM_EN;
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun if (!enabled)
463*4882a593Smuzhiyun enableval = 0;
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun ret = regmap_update_bits(r->parent->regmap, BD71828_REG_RTC_ALM0_MASK,
466*4882a593Smuzhiyun BD70528_MASK_ALM_EN, enableval);
467*4882a593Smuzhiyun if (ret)
468*4882a593Smuzhiyun dev_err(dev, "Failed to change alarm state\n");
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun return ret;
471*4882a593Smuzhiyun }
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun static const struct rtc_class_ops bd70528_rtc_ops = {
474*4882a593Smuzhiyun .read_time = bd70528_get_time,
475*4882a593Smuzhiyun .set_time = bd70528_set_time,
476*4882a593Smuzhiyun .read_alarm = bd70528_read_alarm,
477*4882a593Smuzhiyun .set_alarm = bd70528_set_alarm,
478*4882a593Smuzhiyun .alarm_irq_enable = bd70528_alm_enable,
479*4882a593Smuzhiyun };
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun static const struct rtc_class_ops bd71828_rtc_ops = {
482*4882a593Smuzhiyun .read_time = bd70528_get_time,
483*4882a593Smuzhiyun .set_time = bd71828_set_time,
484*4882a593Smuzhiyun .read_alarm = bd71828_read_alarm,
485*4882a593Smuzhiyun .set_alarm = bd71828_set_alarm,
486*4882a593Smuzhiyun .alarm_irq_enable = bd71828_alm_enable,
487*4882a593Smuzhiyun };
488*4882a593Smuzhiyun
alm_hndlr(int irq,void * data)489*4882a593Smuzhiyun static irqreturn_t alm_hndlr(int irq, void *data)
490*4882a593Smuzhiyun {
491*4882a593Smuzhiyun struct rtc_device *rtc = data;
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF | RTC_PF);
494*4882a593Smuzhiyun return IRQ_HANDLED;
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun
bd70528_probe(struct platform_device * pdev)497*4882a593Smuzhiyun static int bd70528_probe(struct platform_device *pdev)
498*4882a593Smuzhiyun {
499*4882a593Smuzhiyun struct bd70528_rtc *bd_rtc;
500*4882a593Smuzhiyun const struct rtc_class_ops *rtc_ops;
501*4882a593Smuzhiyun struct rohm_regmap_dev *parent;
502*4882a593Smuzhiyun const char *irq_name;
503*4882a593Smuzhiyun int ret;
504*4882a593Smuzhiyun struct rtc_device *rtc;
505*4882a593Smuzhiyun int irq;
506*4882a593Smuzhiyun unsigned int hr;
507*4882a593Smuzhiyun bool enable_main_irq = false;
508*4882a593Smuzhiyun u8 hour_reg;
509*4882a593Smuzhiyun enum rohm_chip_type chip = platform_get_device_id(pdev)->driver_data;
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun parent = dev_get_drvdata(pdev->dev.parent);
512*4882a593Smuzhiyun if (!parent) {
513*4882a593Smuzhiyun dev_err(&pdev->dev, "No MFD driver data\n");
514*4882a593Smuzhiyun return -EINVAL;
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun bd_rtc = devm_kzalloc(&pdev->dev, sizeof(*bd_rtc), GFP_KERNEL);
517*4882a593Smuzhiyun if (!bd_rtc)
518*4882a593Smuzhiyun return -ENOMEM;
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun bd_rtc->parent = parent;
521*4882a593Smuzhiyun bd_rtc->dev = &pdev->dev;
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun switch (chip) {
524*4882a593Smuzhiyun case ROHM_CHIP_TYPE_BD70528:
525*4882a593Smuzhiyun irq_name = "bd70528-rtc-alm";
526*4882a593Smuzhiyun bd_rtc->has_rtc_timers = true;
527*4882a593Smuzhiyun bd_rtc->reg_time_start = BD70528_REG_RTC_START;
528*4882a593Smuzhiyun hour_reg = BD70528_REG_RTC_HOUR;
529*4882a593Smuzhiyun enable_main_irq = true;
530*4882a593Smuzhiyun rtc_ops = &bd70528_rtc_ops;
531*4882a593Smuzhiyun break;
532*4882a593Smuzhiyun case ROHM_CHIP_TYPE_BD71828:
533*4882a593Smuzhiyun irq_name = "bd71828-rtc-alm-0";
534*4882a593Smuzhiyun bd_rtc->reg_time_start = BD71828_REG_RTC_START;
535*4882a593Smuzhiyun hour_reg = BD71828_REG_RTC_HOUR;
536*4882a593Smuzhiyun rtc_ops = &bd71828_rtc_ops;
537*4882a593Smuzhiyun break;
538*4882a593Smuzhiyun default:
539*4882a593Smuzhiyun dev_err(&pdev->dev, "Unknown chip\n");
540*4882a593Smuzhiyun return -ENOENT;
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun irq = platform_get_irq_byname(pdev, irq_name);
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun if (irq < 0)
546*4882a593Smuzhiyun return irq;
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun platform_set_drvdata(pdev, bd_rtc);
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun ret = regmap_read(parent->regmap, hour_reg, &hr);
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun if (ret) {
553*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to reag RTC clock\n");
554*4882a593Smuzhiyun return ret;
555*4882a593Smuzhiyun }
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun if (!(hr & BD70528_MASK_RTC_HOUR_24H)) {
558*4882a593Smuzhiyun struct rtc_time t;
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun ret = rtc_ops->read_time(&pdev->dev, &t);
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun if (!ret)
563*4882a593Smuzhiyun ret = rtc_ops->set_time(&pdev->dev, &t);
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun if (ret) {
566*4882a593Smuzhiyun dev_err(&pdev->dev,
567*4882a593Smuzhiyun "Setting 24H clock for RTC failed\n");
568*4882a593Smuzhiyun return ret;
569*4882a593Smuzhiyun }
570*4882a593Smuzhiyun }
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun device_set_wakeup_capable(&pdev->dev, true);
573*4882a593Smuzhiyun device_wakeup_enable(&pdev->dev);
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun rtc = devm_rtc_allocate_device(&pdev->dev);
576*4882a593Smuzhiyun if (IS_ERR(rtc)) {
577*4882a593Smuzhiyun dev_err(&pdev->dev, "RTC device creation failed\n");
578*4882a593Smuzhiyun return PTR_ERR(rtc);
579*4882a593Smuzhiyun }
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
582*4882a593Smuzhiyun rtc->range_max = RTC_TIMESTAMP_END_2099;
583*4882a593Smuzhiyun rtc->ops = rtc_ops;
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun /* Request alarm IRQ prior to registerig the RTC */
586*4882a593Smuzhiyun ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, &alm_hndlr,
587*4882a593Smuzhiyun IRQF_ONESHOT, "bd70528-rtc", rtc);
588*4882a593Smuzhiyun if (ret)
589*4882a593Smuzhiyun return ret;
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun /*
592*4882a593Smuzhiyun * BD70528 irq controller is not touching the main mask register.
593*4882a593Smuzhiyun * So enable the RTC block interrupts at main level. We can just
594*4882a593Smuzhiyun * leave them enabled as irq-controller should disable irqs
595*4882a593Smuzhiyun * from sub-registers when IRQ is disabled or freed.
596*4882a593Smuzhiyun */
597*4882a593Smuzhiyun if (enable_main_irq) {
598*4882a593Smuzhiyun ret = regmap_update_bits(parent->regmap,
599*4882a593Smuzhiyun BD70528_REG_INT_MAIN_MASK,
600*4882a593Smuzhiyun BD70528_INT_RTC_MASK, 0);
601*4882a593Smuzhiyun if (ret) {
602*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to enable RTC interrupts\n");
603*4882a593Smuzhiyun return ret;
604*4882a593Smuzhiyun }
605*4882a593Smuzhiyun }
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun return rtc_register_device(rtc);
608*4882a593Smuzhiyun }
609*4882a593Smuzhiyun
610*4882a593Smuzhiyun static const struct platform_device_id bd718x7_rtc_id[] = {
611*4882a593Smuzhiyun { "bd70528-rtc", ROHM_CHIP_TYPE_BD70528 },
612*4882a593Smuzhiyun { "bd71828-rtc", ROHM_CHIP_TYPE_BD71828 },
613*4882a593Smuzhiyun { },
614*4882a593Smuzhiyun };
615*4882a593Smuzhiyun MODULE_DEVICE_TABLE(platform, bd718x7_rtc_id);
616*4882a593Smuzhiyun
617*4882a593Smuzhiyun static struct platform_driver bd70528_rtc = {
618*4882a593Smuzhiyun .driver = {
619*4882a593Smuzhiyun .name = "bd70528-rtc"
620*4882a593Smuzhiyun },
621*4882a593Smuzhiyun .probe = bd70528_probe,
622*4882a593Smuzhiyun .id_table = bd718x7_rtc_id,
623*4882a593Smuzhiyun };
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun module_platform_driver(bd70528_rtc);
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
628*4882a593Smuzhiyun MODULE_DESCRIPTION("ROHM BD70528 and BD71828 PMIC RTC driver");
629*4882a593Smuzhiyun MODULE_LICENSE("GPL");
630*4882a593Smuzhiyun MODULE_ALIAS("platform:bd70528-rtc");
631