1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Au1xxx counter0 (aka Time-Of-Year counter) RTC interface driver.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
7*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive
8*4882a593Smuzhiyun * for more details.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun /* All current Au1xxx SoCs have 2 counters fed by an external 32.768 kHz
12*4882a593Smuzhiyun * crystal. Counter 0, which keeps counting during sleep/powerdown, is
13*4882a593Smuzhiyun * used to count seconds since the beginning of the unix epoch.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * The counters must be configured and enabled by bootloader/board code;
16*4882a593Smuzhiyun * no checks as to whether they really get a proper 32.768kHz clock are
17*4882a593Smuzhiyun * made as this would take far too long.
18*4882a593Smuzhiyun */
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <linux/module.h>
21*4882a593Smuzhiyun #include <linux/kernel.h>
22*4882a593Smuzhiyun #include <linux/rtc.h>
23*4882a593Smuzhiyun #include <linux/init.h>
24*4882a593Smuzhiyun #include <linux/platform_device.h>
25*4882a593Smuzhiyun #include <linux/io.h>
26*4882a593Smuzhiyun #include <asm/mach-au1x00/au1000.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* 32kHz clock enabled and detected */
29*4882a593Smuzhiyun #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
30*4882a593Smuzhiyun
au1xtoy_rtc_read_time(struct device * dev,struct rtc_time * tm)31*4882a593Smuzhiyun static int au1xtoy_rtc_read_time(struct device *dev, struct rtc_time *tm)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun unsigned long t;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun t = alchemy_rdsys(AU1000_SYS_TOYREAD);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun rtc_time64_to_tm(t, tm);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun return 0;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
au1xtoy_rtc_set_time(struct device * dev,struct rtc_time * tm)42*4882a593Smuzhiyun static int au1xtoy_rtc_set_time(struct device *dev, struct rtc_time *tm)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun unsigned long t;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun t = rtc_tm_to_time64(tm);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun alchemy_wrsys(t, AU1000_SYS_TOYWRITE);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* wait for the pending register write to succeed. This can
51*4882a593Smuzhiyun * take up to 6 seconds...
52*4882a593Smuzhiyun */
53*4882a593Smuzhiyun while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C0S)
54*4882a593Smuzhiyun msleep(1);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun return 0;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static const struct rtc_class_ops au1xtoy_rtc_ops = {
60*4882a593Smuzhiyun .read_time = au1xtoy_rtc_read_time,
61*4882a593Smuzhiyun .set_time = au1xtoy_rtc_set_time,
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
au1xtoy_rtc_probe(struct platform_device * pdev)64*4882a593Smuzhiyun static int au1xtoy_rtc_probe(struct platform_device *pdev)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun struct rtc_device *rtcdev;
67*4882a593Smuzhiyun unsigned long t;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun t = alchemy_rdsys(AU1000_SYS_CNTRCTRL);
70*4882a593Smuzhiyun if (!(t & CNTR_OK)) {
71*4882a593Smuzhiyun dev_err(&pdev->dev, "counters not working; aborting.\n");
72*4882a593Smuzhiyun return -ENODEV;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* set counter0 tickrate to 1Hz if necessary */
76*4882a593Smuzhiyun if (alchemy_rdsys(AU1000_SYS_TOYTRIM) != 32767) {
77*4882a593Smuzhiyun /* wait until hardware gives access to TRIM register */
78*4882a593Smuzhiyun t = 0x00100000;
79*4882a593Smuzhiyun while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_T0S) && --t)
80*4882a593Smuzhiyun msleep(1);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun if (!t) {
83*4882a593Smuzhiyun /* timed out waiting for register access; assume
84*4882a593Smuzhiyun * counters are unusable.
85*4882a593Smuzhiyun */
86*4882a593Smuzhiyun dev_err(&pdev->dev, "timeout waiting for access\n");
87*4882a593Smuzhiyun return -ETIMEDOUT;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* set 1Hz TOY tick rate */
91*4882a593Smuzhiyun alchemy_wrsys(32767, AU1000_SYS_TOYTRIM);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* wait until the hardware allows writes to the counter reg */
95*4882a593Smuzhiyun while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C0S)
96*4882a593Smuzhiyun msleep(1);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun rtcdev = devm_rtc_allocate_device(&pdev->dev);
99*4882a593Smuzhiyun if (IS_ERR(rtcdev))
100*4882a593Smuzhiyun return PTR_ERR(rtcdev);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun rtcdev->ops = &au1xtoy_rtc_ops;
103*4882a593Smuzhiyun rtcdev->range_max = U32_MAX;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun platform_set_drvdata(pdev, rtcdev);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun return rtc_register_device(rtcdev);
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun static struct platform_driver au1xrtc_driver = {
111*4882a593Smuzhiyun .driver = {
112*4882a593Smuzhiyun .name = "rtc-au1xxx",
113*4882a593Smuzhiyun },
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun module_platform_driver_probe(au1xrtc_driver, au1xtoy_rtc_probe);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun MODULE_DESCRIPTION("Au1xxx TOY-counter-based RTC driver");
119*4882a593Smuzhiyun MODULE_AUTHOR("Manuel Lauss <manuel.lauss@gmail.com>");
120*4882a593Smuzhiyun MODULE_LICENSE("GPL");
121*4882a593Smuzhiyun MODULE_ALIAS("platform:rtc-au1xxx");
122