1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * A driver for the I2C members of the Abracon AB x8xx RTC family,
4*4882a593Smuzhiyun * and compatible: AB 1805 and AB 0805
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright 2014-2015 Macq S.A.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Author: Philippe De Muyter <phdm@macqel.be>
9*4882a593Smuzhiyun * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/bcd.h>
14*4882a593Smuzhiyun #include <linux/i2c.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/of_device.h>
17*4882a593Smuzhiyun #include <linux/rtc.h>
18*4882a593Smuzhiyun #include <linux/watchdog.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define ABX8XX_REG_HTH 0x00
21*4882a593Smuzhiyun #define ABX8XX_REG_SC 0x01
22*4882a593Smuzhiyun #define ABX8XX_REG_MN 0x02
23*4882a593Smuzhiyun #define ABX8XX_REG_HR 0x03
24*4882a593Smuzhiyun #define ABX8XX_REG_DA 0x04
25*4882a593Smuzhiyun #define ABX8XX_REG_MO 0x05
26*4882a593Smuzhiyun #define ABX8XX_REG_YR 0x06
27*4882a593Smuzhiyun #define ABX8XX_REG_WD 0x07
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define ABX8XX_REG_AHTH 0x08
30*4882a593Smuzhiyun #define ABX8XX_REG_ASC 0x09
31*4882a593Smuzhiyun #define ABX8XX_REG_AMN 0x0a
32*4882a593Smuzhiyun #define ABX8XX_REG_AHR 0x0b
33*4882a593Smuzhiyun #define ABX8XX_REG_ADA 0x0c
34*4882a593Smuzhiyun #define ABX8XX_REG_AMO 0x0d
35*4882a593Smuzhiyun #define ABX8XX_REG_AWD 0x0e
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define ABX8XX_REG_STATUS 0x0f
38*4882a593Smuzhiyun #define ABX8XX_STATUS_AF BIT(2)
39*4882a593Smuzhiyun #define ABX8XX_STATUS_BLF BIT(4)
40*4882a593Smuzhiyun #define ABX8XX_STATUS_WDT BIT(6)
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define ABX8XX_REG_CTRL1 0x10
43*4882a593Smuzhiyun #define ABX8XX_CTRL_WRITE BIT(0)
44*4882a593Smuzhiyun #define ABX8XX_CTRL_ARST BIT(2)
45*4882a593Smuzhiyun #define ABX8XX_CTRL_12_24 BIT(6)
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define ABX8XX_REG_CTRL2 0x11
48*4882a593Smuzhiyun #define ABX8XX_CTRL2_RSVD BIT(5)
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #define ABX8XX_REG_IRQ 0x12
51*4882a593Smuzhiyun #define ABX8XX_IRQ_AIE BIT(2)
52*4882a593Smuzhiyun #define ABX8XX_IRQ_IM_1_4 (0x3 << 5)
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define ABX8XX_REG_CD_TIMER_CTL 0x18
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #define ABX8XX_REG_OSC 0x1c
57*4882a593Smuzhiyun #define ABX8XX_OSC_FOS BIT(3)
58*4882a593Smuzhiyun #define ABX8XX_OSC_BOS BIT(4)
59*4882a593Smuzhiyun #define ABX8XX_OSC_ACAL_512 BIT(5)
60*4882a593Smuzhiyun #define ABX8XX_OSC_ACAL_1024 BIT(6)
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun #define ABX8XX_OSC_OSEL BIT(7)
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #define ABX8XX_REG_OSS 0x1d
65*4882a593Smuzhiyun #define ABX8XX_OSS_OF BIT(1)
66*4882a593Smuzhiyun #define ABX8XX_OSS_OMODE BIT(4)
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun #define ABX8XX_REG_WDT 0x1b
69*4882a593Smuzhiyun #define ABX8XX_WDT_WDS BIT(7)
70*4882a593Smuzhiyun #define ABX8XX_WDT_BMB_MASK 0x7c
71*4882a593Smuzhiyun #define ABX8XX_WDT_BMB_SHIFT 2
72*4882a593Smuzhiyun #define ABX8XX_WDT_MAX_TIME (ABX8XX_WDT_BMB_MASK >> ABX8XX_WDT_BMB_SHIFT)
73*4882a593Smuzhiyun #define ABX8XX_WDT_WRB_MASK 0x03
74*4882a593Smuzhiyun #define ABX8XX_WDT_WRB_1HZ 0x02
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #define ABX8XX_REG_CFG_KEY 0x1f
77*4882a593Smuzhiyun #define ABX8XX_CFG_KEY_OSC 0xa1
78*4882a593Smuzhiyun #define ABX8XX_CFG_KEY_MISC 0x9d
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun #define ABX8XX_REG_ID0 0x28
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun #define ABX8XX_REG_OUT_CTRL 0x30
83*4882a593Smuzhiyun #define ABX8XX_OUT_CTRL_EXDS BIT(4)
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #define ABX8XX_REG_TRICKLE 0x20
86*4882a593Smuzhiyun #define ABX8XX_TRICKLE_CHARGE_ENABLE 0xa0
87*4882a593Smuzhiyun #define ABX8XX_TRICKLE_STANDARD_DIODE 0x8
88*4882a593Smuzhiyun #define ABX8XX_TRICKLE_SCHOTTKY_DIODE 0x4
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun static u8 trickle_resistors[] = {0, 3, 6, 11};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun enum abx80x_chip {AB0801, AB0803, AB0804, AB0805,
93*4882a593Smuzhiyun AB1801, AB1803, AB1804, AB1805, RV1805, ABX80X};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun struct abx80x_cap {
96*4882a593Smuzhiyun u16 pn;
97*4882a593Smuzhiyun bool has_tc;
98*4882a593Smuzhiyun bool has_wdog;
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun static struct abx80x_cap abx80x_caps[] = {
102*4882a593Smuzhiyun [AB0801] = {.pn = 0x0801},
103*4882a593Smuzhiyun [AB0803] = {.pn = 0x0803},
104*4882a593Smuzhiyun [AB0804] = {.pn = 0x0804, .has_tc = true, .has_wdog = true},
105*4882a593Smuzhiyun [AB0805] = {.pn = 0x0805, .has_tc = true, .has_wdog = true},
106*4882a593Smuzhiyun [AB1801] = {.pn = 0x1801},
107*4882a593Smuzhiyun [AB1803] = {.pn = 0x1803},
108*4882a593Smuzhiyun [AB1804] = {.pn = 0x1804, .has_tc = true, .has_wdog = true},
109*4882a593Smuzhiyun [AB1805] = {.pn = 0x1805, .has_tc = true, .has_wdog = true},
110*4882a593Smuzhiyun [RV1805] = {.pn = 0x1805, .has_tc = true, .has_wdog = true},
111*4882a593Smuzhiyun [ABX80X] = {.pn = 0}
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun struct abx80x_priv {
115*4882a593Smuzhiyun struct rtc_device *rtc;
116*4882a593Smuzhiyun struct i2c_client *client;
117*4882a593Smuzhiyun struct watchdog_device wdog;
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun
abx80x_is_rc_mode(struct i2c_client * client)120*4882a593Smuzhiyun static int abx80x_is_rc_mode(struct i2c_client *client)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun int flags = 0;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSS);
125*4882a593Smuzhiyun if (flags < 0) {
126*4882a593Smuzhiyun dev_err(&client->dev,
127*4882a593Smuzhiyun "Failed to read autocalibration attribute\n");
128*4882a593Smuzhiyun return flags;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun return (flags & ABX8XX_OSS_OMODE) ? 1 : 0;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
abx80x_enable_trickle_charger(struct i2c_client * client,u8 trickle_cfg)134*4882a593Smuzhiyun static int abx80x_enable_trickle_charger(struct i2c_client *client,
135*4882a593Smuzhiyun u8 trickle_cfg)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun int err;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun /*
140*4882a593Smuzhiyun * Write the configuration key register to enable access to the Trickle
141*4882a593Smuzhiyun * register
142*4882a593Smuzhiyun */
143*4882a593Smuzhiyun err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CFG_KEY,
144*4882a593Smuzhiyun ABX8XX_CFG_KEY_MISC);
145*4882a593Smuzhiyun if (err < 0) {
146*4882a593Smuzhiyun dev_err(&client->dev, "Unable to write configuration key\n");
147*4882a593Smuzhiyun return -EIO;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun err = i2c_smbus_write_byte_data(client, ABX8XX_REG_TRICKLE,
151*4882a593Smuzhiyun ABX8XX_TRICKLE_CHARGE_ENABLE |
152*4882a593Smuzhiyun trickle_cfg);
153*4882a593Smuzhiyun if (err < 0) {
154*4882a593Smuzhiyun dev_err(&client->dev, "Unable to write trickle register\n");
155*4882a593Smuzhiyun return -EIO;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun return 0;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
abx80x_rtc_read_time(struct device * dev,struct rtc_time * tm)161*4882a593Smuzhiyun static int abx80x_rtc_read_time(struct device *dev, struct rtc_time *tm)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
164*4882a593Smuzhiyun unsigned char buf[8];
165*4882a593Smuzhiyun int err, flags, rc_mode = 0;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun /* Read the Oscillator Failure only in XT mode */
168*4882a593Smuzhiyun rc_mode = abx80x_is_rc_mode(client);
169*4882a593Smuzhiyun if (rc_mode < 0)
170*4882a593Smuzhiyun return rc_mode;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun if (!rc_mode) {
173*4882a593Smuzhiyun flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSS);
174*4882a593Smuzhiyun if (flags < 0)
175*4882a593Smuzhiyun return flags;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun if (flags & ABX8XX_OSS_OF) {
178*4882a593Smuzhiyun dev_err(dev, "Oscillator failure, data is invalid.\n");
179*4882a593Smuzhiyun return -EINVAL;
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun err = i2c_smbus_read_i2c_block_data(client, ABX8XX_REG_HTH,
184*4882a593Smuzhiyun sizeof(buf), buf);
185*4882a593Smuzhiyun if (err < 0) {
186*4882a593Smuzhiyun dev_err(&client->dev, "Unable to read date\n");
187*4882a593Smuzhiyun return -EIO;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun tm->tm_sec = bcd2bin(buf[ABX8XX_REG_SC] & 0x7F);
191*4882a593Smuzhiyun tm->tm_min = bcd2bin(buf[ABX8XX_REG_MN] & 0x7F);
192*4882a593Smuzhiyun tm->tm_hour = bcd2bin(buf[ABX8XX_REG_HR] & 0x3F);
193*4882a593Smuzhiyun tm->tm_wday = buf[ABX8XX_REG_WD] & 0x7;
194*4882a593Smuzhiyun tm->tm_mday = bcd2bin(buf[ABX8XX_REG_DA] & 0x3F);
195*4882a593Smuzhiyun tm->tm_mon = bcd2bin(buf[ABX8XX_REG_MO] & 0x1F) - 1;
196*4882a593Smuzhiyun tm->tm_year = bcd2bin(buf[ABX8XX_REG_YR]) + 100;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun return 0;
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun
abx80x_rtc_set_time(struct device * dev,struct rtc_time * tm)201*4882a593Smuzhiyun static int abx80x_rtc_set_time(struct device *dev, struct rtc_time *tm)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
204*4882a593Smuzhiyun unsigned char buf[8];
205*4882a593Smuzhiyun int err, flags;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun if (tm->tm_year < 100)
208*4882a593Smuzhiyun return -EINVAL;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun buf[ABX8XX_REG_HTH] = 0;
211*4882a593Smuzhiyun buf[ABX8XX_REG_SC] = bin2bcd(tm->tm_sec);
212*4882a593Smuzhiyun buf[ABX8XX_REG_MN] = bin2bcd(tm->tm_min);
213*4882a593Smuzhiyun buf[ABX8XX_REG_HR] = bin2bcd(tm->tm_hour);
214*4882a593Smuzhiyun buf[ABX8XX_REG_DA] = bin2bcd(tm->tm_mday);
215*4882a593Smuzhiyun buf[ABX8XX_REG_MO] = bin2bcd(tm->tm_mon + 1);
216*4882a593Smuzhiyun buf[ABX8XX_REG_YR] = bin2bcd(tm->tm_year - 100);
217*4882a593Smuzhiyun buf[ABX8XX_REG_WD] = tm->tm_wday;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun err = i2c_smbus_write_i2c_block_data(client, ABX8XX_REG_HTH,
220*4882a593Smuzhiyun sizeof(buf), buf);
221*4882a593Smuzhiyun if (err < 0) {
222*4882a593Smuzhiyun dev_err(&client->dev, "Unable to write to date registers\n");
223*4882a593Smuzhiyun return -EIO;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun /* Clear the OF bit of Oscillator Status Register */
227*4882a593Smuzhiyun flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSS);
228*4882a593Smuzhiyun if (flags < 0)
229*4882a593Smuzhiyun return flags;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun err = i2c_smbus_write_byte_data(client, ABX8XX_REG_OSS,
232*4882a593Smuzhiyun flags & ~ABX8XX_OSS_OF);
233*4882a593Smuzhiyun if (err < 0) {
234*4882a593Smuzhiyun dev_err(&client->dev, "Unable to write oscillator status register\n");
235*4882a593Smuzhiyun return err;
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun return 0;
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun
abx80x_handle_irq(int irq,void * dev_id)241*4882a593Smuzhiyun static irqreturn_t abx80x_handle_irq(int irq, void *dev_id)
242*4882a593Smuzhiyun {
243*4882a593Smuzhiyun struct i2c_client *client = dev_id;
244*4882a593Smuzhiyun struct abx80x_priv *priv = i2c_get_clientdata(client);
245*4882a593Smuzhiyun struct rtc_device *rtc = priv->rtc;
246*4882a593Smuzhiyun int status;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun status = i2c_smbus_read_byte_data(client, ABX8XX_REG_STATUS);
249*4882a593Smuzhiyun if (status < 0)
250*4882a593Smuzhiyun return IRQ_NONE;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun if (status & ABX8XX_STATUS_AF)
253*4882a593Smuzhiyun rtc_update_irq(rtc, 1, RTC_AF | RTC_IRQF);
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun /*
256*4882a593Smuzhiyun * It is unclear if we'll get an interrupt before the external
257*4882a593Smuzhiyun * reset kicks in.
258*4882a593Smuzhiyun */
259*4882a593Smuzhiyun if (status & ABX8XX_STATUS_WDT)
260*4882a593Smuzhiyun dev_alert(&client->dev, "watchdog timeout interrupt.\n");
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun i2c_smbus_write_byte_data(client, ABX8XX_REG_STATUS, 0);
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun return IRQ_HANDLED;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun
abx80x_read_alarm(struct device * dev,struct rtc_wkalrm * t)267*4882a593Smuzhiyun static int abx80x_read_alarm(struct device *dev, struct rtc_wkalrm *t)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
270*4882a593Smuzhiyun unsigned char buf[7];
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun int irq_mask, err;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun if (client->irq <= 0)
275*4882a593Smuzhiyun return -EINVAL;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun err = i2c_smbus_read_i2c_block_data(client, ABX8XX_REG_ASC,
278*4882a593Smuzhiyun sizeof(buf), buf);
279*4882a593Smuzhiyun if (err)
280*4882a593Smuzhiyun return err;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun irq_mask = i2c_smbus_read_byte_data(client, ABX8XX_REG_IRQ);
283*4882a593Smuzhiyun if (irq_mask < 0)
284*4882a593Smuzhiyun return irq_mask;
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun t->time.tm_sec = bcd2bin(buf[0] & 0x7F);
287*4882a593Smuzhiyun t->time.tm_min = bcd2bin(buf[1] & 0x7F);
288*4882a593Smuzhiyun t->time.tm_hour = bcd2bin(buf[2] & 0x3F);
289*4882a593Smuzhiyun t->time.tm_mday = bcd2bin(buf[3] & 0x3F);
290*4882a593Smuzhiyun t->time.tm_mon = bcd2bin(buf[4] & 0x1F) - 1;
291*4882a593Smuzhiyun t->time.tm_wday = buf[5] & 0x7;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun t->enabled = !!(irq_mask & ABX8XX_IRQ_AIE);
294*4882a593Smuzhiyun t->pending = (buf[6] & ABX8XX_STATUS_AF) && t->enabled;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun return err;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun
abx80x_set_alarm(struct device * dev,struct rtc_wkalrm * t)299*4882a593Smuzhiyun static int abx80x_set_alarm(struct device *dev, struct rtc_wkalrm *t)
300*4882a593Smuzhiyun {
301*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
302*4882a593Smuzhiyun u8 alarm[6];
303*4882a593Smuzhiyun int err;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun if (client->irq <= 0)
306*4882a593Smuzhiyun return -EINVAL;
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun alarm[0] = 0x0;
309*4882a593Smuzhiyun alarm[1] = bin2bcd(t->time.tm_sec);
310*4882a593Smuzhiyun alarm[2] = bin2bcd(t->time.tm_min);
311*4882a593Smuzhiyun alarm[3] = bin2bcd(t->time.tm_hour);
312*4882a593Smuzhiyun alarm[4] = bin2bcd(t->time.tm_mday);
313*4882a593Smuzhiyun alarm[5] = bin2bcd(t->time.tm_mon + 1);
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun err = i2c_smbus_write_i2c_block_data(client, ABX8XX_REG_AHTH,
316*4882a593Smuzhiyun sizeof(alarm), alarm);
317*4882a593Smuzhiyun if (err < 0) {
318*4882a593Smuzhiyun dev_err(&client->dev, "Unable to write alarm registers\n");
319*4882a593Smuzhiyun return -EIO;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun if (t->enabled) {
323*4882a593Smuzhiyun err = i2c_smbus_write_byte_data(client, ABX8XX_REG_IRQ,
324*4882a593Smuzhiyun (ABX8XX_IRQ_IM_1_4 |
325*4882a593Smuzhiyun ABX8XX_IRQ_AIE));
326*4882a593Smuzhiyun if (err)
327*4882a593Smuzhiyun return err;
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun return 0;
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun
abx80x_rtc_set_autocalibration(struct device * dev,int autocalibration)333*4882a593Smuzhiyun static int abx80x_rtc_set_autocalibration(struct device *dev,
334*4882a593Smuzhiyun int autocalibration)
335*4882a593Smuzhiyun {
336*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
337*4882a593Smuzhiyun int retval, flags = 0;
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun if ((autocalibration != 0) && (autocalibration != 1024) &&
340*4882a593Smuzhiyun (autocalibration != 512)) {
341*4882a593Smuzhiyun dev_err(dev, "autocalibration value outside permitted range\n");
342*4882a593Smuzhiyun return -EINVAL;
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSC);
346*4882a593Smuzhiyun if (flags < 0)
347*4882a593Smuzhiyun return flags;
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun if (autocalibration == 0) {
350*4882a593Smuzhiyun flags &= ~(ABX8XX_OSC_ACAL_512 | ABX8XX_OSC_ACAL_1024);
351*4882a593Smuzhiyun } else if (autocalibration == 1024) {
352*4882a593Smuzhiyun /* 1024 autocalibration is 0x10 */
353*4882a593Smuzhiyun flags |= ABX8XX_OSC_ACAL_1024;
354*4882a593Smuzhiyun flags &= ~(ABX8XX_OSC_ACAL_512);
355*4882a593Smuzhiyun } else {
356*4882a593Smuzhiyun /* 512 autocalibration is 0x11 */
357*4882a593Smuzhiyun flags |= (ABX8XX_OSC_ACAL_1024 | ABX8XX_OSC_ACAL_512);
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun /* Unlock write access to Oscillator Control Register */
361*4882a593Smuzhiyun retval = i2c_smbus_write_byte_data(client, ABX8XX_REG_CFG_KEY,
362*4882a593Smuzhiyun ABX8XX_CFG_KEY_OSC);
363*4882a593Smuzhiyun if (retval < 0) {
364*4882a593Smuzhiyun dev_err(dev, "Failed to write CONFIG_KEY register\n");
365*4882a593Smuzhiyun return retval;
366*4882a593Smuzhiyun }
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun retval = i2c_smbus_write_byte_data(client, ABX8XX_REG_OSC, flags);
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun return retval;
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun
abx80x_rtc_get_autocalibration(struct device * dev)373*4882a593Smuzhiyun static int abx80x_rtc_get_autocalibration(struct device *dev)
374*4882a593Smuzhiyun {
375*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
376*4882a593Smuzhiyun int flags = 0, autocalibration;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSC);
379*4882a593Smuzhiyun if (flags < 0)
380*4882a593Smuzhiyun return flags;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun if (flags & ABX8XX_OSC_ACAL_512)
383*4882a593Smuzhiyun autocalibration = 512;
384*4882a593Smuzhiyun else if (flags & ABX8XX_OSC_ACAL_1024)
385*4882a593Smuzhiyun autocalibration = 1024;
386*4882a593Smuzhiyun else
387*4882a593Smuzhiyun autocalibration = 0;
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun return autocalibration;
390*4882a593Smuzhiyun }
391*4882a593Smuzhiyun
autocalibration_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)392*4882a593Smuzhiyun static ssize_t autocalibration_store(struct device *dev,
393*4882a593Smuzhiyun struct device_attribute *attr,
394*4882a593Smuzhiyun const char *buf, size_t count)
395*4882a593Smuzhiyun {
396*4882a593Smuzhiyun int retval;
397*4882a593Smuzhiyun unsigned long autocalibration = 0;
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun retval = kstrtoul(buf, 10, &autocalibration);
400*4882a593Smuzhiyun if (retval < 0) {
401*4882a593Smuzhiyun dev_err(dev, "Failed to store RTC autocalibration attribute\n");
402*4882a593Smuzhiyun return -EINVAL;
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun retval = abx80x_rtc_set_autocalibration(dev->parent, autocalibration);
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun return retval ? retval : count;
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun
autocalibration_show(struct device * dev,struct device_attribute * attr,char * buf)410*4882a593Smuzhiyun static ssize_t autocalibration_show(struct device *dev,
411*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
412*4882a593Smuzhiyun {
413*4882a593Smuzhiyun int autocalibration = 0;
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun autocalibration = abx80x_rtc_get_autocalibration(dev->parent);
416*4882a593Smuzhiyun if (autocalibration < 0) {
417*4882a593Smuzhiyun dev_err(dev, "Failed to read RTC autocalibration\n");
418*4882a593Smuzhiyun sprintf(buf, "0\n");
419*4882a593Smuzhiyun return autocalibration;
420*4882a593Smuzhiyun }
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun return sprintf(buf, "%d\n", autocalibration);
423*4882a593Smuzhiyun }
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun static DEVICE_ATTR_RW(autocalibration);
426*4882a593Smuzhiyun
oscillator_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)427*4882a593Smuzhiyun static ssize_t oscillator_store(struct device *dev,
428*4882a593Smuzhiyun struct device_attribute *attr,
429*4882a593Smuzhiyun const char *buf, size_t count)
430*4882a593Smuzhiyun {
431*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev->parent);
432*4882a593Smuzhiyun int retval, flags, rc_mode = 0;
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun if (strncmp(buf, "rc", 2) == 0) {
435*4882a593Smuzhiyun rc_mode = 1;
436*4882a593Smuzhiyun } else if (strncmp(buf, "xtal", 4) == 0) {
437*4882a593Smuzhiyun rc_mode = 0;
438*4882a593Smuzhiyun } else {
439*4882a593Smuzhiyun dev_err(dev, "Oscillator selection value outside permitted ones\n");
440*4882a593Smuzhiyun return -EINVAL;
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun flags = i2c_smbus_read_byte_data(client, ABX8XX_REG_OSC);
444*4882a593Smuzhiyun if (flags < 0)
445*4882a593Smuzhiyun return flags;
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun if (rc_mode == 0)
448*4882a593Smuzhiyun flags &= ~(ABX8XX_OSC_OSEL);
449*4882a593Smuzhiyun else
450*4882a593Smuzhiyun flags |= (ABX8XX_OSC_OSEL);
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun /* Unlock write access on Oscillator Control register */
453*4882a593Smuzhiyun retval = i2c_smbus_write_byte_data(client, ABX8XX_REG_CFG_KEY,
454*4882a593Smuzhiyun ABX8XX_CFG_KEY_OSC);
455*4882a593Smuzhiyun if (retval < 0) {
456*4882a593Smuzhiyun dev_err(dev, "Failed to write CONFIG_KEY register\n");
457*4882a593Smuzhiyun return retval;
458*4882a593Smuzhiyun }
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun retval = i2c_smbus_write_byte_data(client, ABX8XX_REG_OSC, flags);
461*4882a593Smuzhiyun if (retval < 0) {
462*4882a593Smuzhiyun dev_err(dev, "Failed to write Oscillator Control register\n");
463*4882a593Smuzhiyun return retval;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun return retval ? retval : count;
467*4882a593Smuzhiyun }
468*4882a593Smuzhiyun
oscillator_show(struct device * dev,struct device_attribute * attr,char * buf)469*4882a593Smuzhiyun static ssize_t oscillator_show(struct device *dev,
470*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
471*4882a593Smuzhiyun {
472*4882a593Smuzhiyun int rc_mode = 0;
473*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev->parent);
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun rc_mode = abx80x_is_rc_mode(client);
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun if (rc_mode < 0) {
478*4882a593Smuzhiyun dev_err(dev, "Failed to read RTC oscillator selection\n");
479*4882a593Smuzhiyun sprintf(buf, "\n");
480*4882a593Smuzhiyun return rc_mode;
481*4882a593Smuzhiyun }
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun if (rc_mode)
484*4882a593Smuzhiyun return sprintf(buf, "rc\n");
485*4882a593Smuzhiyun else
486*4882a593Smuzhiyun return sprintf(buf, "xtal\n");
487*4882a593Smuzhiyun }
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun static DEVICE_ATTR_RW(oscillator);
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun static struct attribute *rtc_calib_attrs[] = {
492*4882a593Smuzhiyun &dev_attr_autocalibration.attr,
493*4882a593Smuzhiyun &dev_attr_oscillator.attr,
494*4882a593Smuzhiyun NULL,
495*4882a593Smuzhiyun };
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun static const struct attribute_group rtc_calib_attr_group = {
498*4882a593Smuzhiyun .attrs = rtc_calib_attrs,
499*4882a593Smuzhiyun };
500*4882a593Smuzhiyun
abx80x_alarm_irq_enable(struct device * dev,unsigned int enabled)501*4882a593Smuzhiyun static int abx80x_alarm_irq_enable(struct device *dev, unsigned int enabled)
502*4882a593Smuzhiyun {
503*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
504*4882a593Smuzhiyun int err;
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun if (enabled)
507*4882a593Smuzhiyun err = i2c_smbus_write_byte_data(client, ABX8XX_REG_IRQ,
508*4882a593Smuzhiyun (ABX8XX_IRQ_IM_1_4 |
509*4882a593Smuzhiyun ABX8XX_IRQ_AIE));
510*4882a593Smuzhiyun else
511*4882a593Smuzhiyun err = i2c_smbus_write_byte_data(client, ABX8XX_REG_IRQ,
512*4882a593Smuzhiyun ABX8XX_IRQ_IM_1_4);
513*4882a593Smuzhiyun return err;
514*4882a593Smuzhiyun }
515*4882a593Smuzhiyun
abx80x_ioctl(struct device * dev,unsigned int cmd,unsigned long arg)516*4882a593Smuzhiyun static int abx80x_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
517*4882a593Smuzhiyun {
518*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
519*4882a593Smuzhiyun int status, tmp;
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun switch (cmd) {
522*4882a593Smuzhiyun case RTC_VL_READ:
523*4882a593Smuzhiyun status = i2c_smbus_read_byte_data(client, ABX8XX_REG_STATUS);
524*4882a593Smuzhiyun if (status < 0)
525*4882a593Smuzhiyun return status;
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun tmp = status & ABX8XX_STATUS_BLF ? RTC_VL_BACKUP_LOW : 0;
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun return put_user(tmp, (unsigned int __user *)arg);
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun case RTC_VL_CLR:
532*4882a593Smuzhiyun status = i2c_smbus_read_byte_data(client, ABX8XX_REG_STATUS);
533*4882a593Smuzhiyun if (status < 0)
534*4882a593Smuzhiyun return status;
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun status &= ~ABX8XX_STATUS_BLF;
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun tmp = i2c_smbus_write_byte_data(client, ABX8XX_REG_STATUS, 0);
539*4882a593Smuzhiyun if (tmp < 0)
540*4882a593Smuzhiyun return tmp;
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun return 0;
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun default:
545*4882a593Smuzhiyun return -ENOIOCTLCMD;
546*4882a593Smuzhiyun }
547*4882a593Smuzhiyun }
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun static const struct rtc_class_ops abx80x_rtc_ops = {
550*4882a593Smuzhiyun .read_time = abx80x_rtc_read_time,
551*4882a593Smuzhiyun .set_time = abx80x_rtc_set_time,
552*4882a593Smuzhiyun .read_alarm = abx80x_read_alarm,
553*4882a593Smuzhiyun .set_alarm = abx80x_set_alarm,
554*4882a593Smuzhiyun .alarm_irq_enable = abx80x_alarm_irq_enable,
555*4882a593Smuzhiyun .ioctl = abx80x_ioctl,
556*4882a593Smuzhiyun };
557*4882a593Smuzhiyun
abx80x_dt_trickle_cfg(struct i2c_client * client)558*4882a593Smuzhiyun static int abx80x_dt_trickle_cfg(struct i2c_client *client)
559*4882a593Smuzhiyun {
560*4882a593Smuzhiyun struct device_node *np = client->dev.of_node;
561*4882a593Smuzhiyun const char *diode;
562*4882a593Smuzhiyun int trickle_cfg = 0;
563*4882a593Smuzhiyun int i, ret;
564*4882a593Smuzhiyun u32 tmp;
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun ret = of_property_read_string(np, "abracon,tc-diode", &diode);
567*4882a593Smuzhiyun if (ret)
568*4882a593Smuzhiyun return ret;
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun if (!strcmp(diode, "standard")) {
571*4882a593Smuzhiyun trickle_cfg |= ABX8XX_TRICKLE_STANDARD_DIODE;
572*4882a593Smuzhiyun } else if (!strcmp(diode, "schottky")) {
573*4882a593Smuzhiyun trickle_cfg |= ABX8XX_TRICKLE_SCHOTTKY_DIODE;
574*4882a593Smuzhiyun } else {
575*4882a593Smuzhiyun dev_dbg(&client->dev, "Invalid tc-diode value: %s\n", diode);
576*4882a593Smuzhiyun return -EINVAL;
577*4882a593Smuzhiyun }
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun ret = of_property_read_u32(np, "abracon,tc-resistor", &tmp);
580*4882a593Smuzhiyun if (ret)
581*4882a593Smuzhiyun return ret;
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun for (i = 0; i < sizeof(trickle_resistors); i++)
584*4882a593Smuzhiyun if (trickle_resistors[i] == tmp)
585*4882a593Smuzhiyun break;
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun if (i == sizeof(trickle_resistors)) {
588*4882a593Smuzhiyun dev_dbg(&client->dev, "Invalid tc-resistor value: %u\n", tmp);
589*4882a593Smuzhiyun return -EINVAL;
590*4882a593Smuzhiyun }
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun return (trickle_cfg | i);
593*4882a593Smuzhiyun }
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun #ifdef CONFIG_WATCHDOG
596*4882a593Smuzhiyun
timeout_bits(unsigned int timeout)597*4882a593Smuzhiyun static inline u8 timeout_bits(unsigned int timeout)
598*4882a593Smuzhiyun {
599*4882a593Smuzhiyun return ((timeout << ABX8XX_WDT_BMB_SHIFT) & ABX8XX_WDT_BMB_MASK) |
600*4882a593Smuzhiyun ABX8XX_WDT_WRB_1HZ;
601*4882a593Smuzhiyun }
602*4882a593Smuzhiyun
__abx80x_wdog_set_timeout(struct watchdog_device * wdog,unsigned int timeout)603*4882a593Smuzhiyun static int __abx80x_wdog_set_timeout(struct watchdog_device *wdog,
604*4882a593Smuzhiyun unsigned int timeout)
605*4882a593Smuzhiyun {
606*4882a593Smuzhiyun struct abx80x_priv *priv = watchdog_get_drvdata(wdog);
607*4882a593Smuzhiyun u8 val = ABX8XX_WDT_WDS | timeout_bits(timeout);
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun /*
610*4882a593Smuzhiyun * Writing any timeout to the WDT register resets the watchdog timer.
611*4882a593Smuzhiyun * Writing 0 disables it.
612*4882a593Smuzhiyun */
613*4882a593Smuzhiyun return i2c_smbus_write_byte_data(priv->client, ABX8XX_REG_WDT, val);
614*4882a593Smuzhiyun }
615*4882a593Smuzhiyun
abx80x_wdog_set_timeout(struct watchdog_device * wdog,unsigned int new_timeout)616*4882a593Smuzhiyun static int abx80x_wdog_set_timeout(struct watchdog_device *wdog,
617*4882a593Smuzhiyun unsigned int new_timeout)
618*4882a593Smuzhiyun {
619*4882a593Smuzhiyun int err = 0;
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun if (watchdog_hw_running(wdog))
622*4882a593Smuzhiyun err = __abx80x_wdog_set_timeout(wdog, new_timeout);
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun if (err == 0)
625*4882a593Smuzhiyun wdog->timeout = new_timeout;
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun return err;
628*4882a593Smuzhiyun }
629*4882a593Smuzhiyun
abx80x_wdog_ping(struct watchdog_device * wdog)630*4882a593Smuzhiyun static int abx80x_wdog_ping(struct watchdog_device *wdog)
631*4882a593Smuzhiyun {
632*4882a593Smuzhiyun return __abx80x_wdog_set_timeout(wdog, wdog->timeout);
633*4882a593Smuzhiyun }
634*4882a593Smuzhiyun
abx80x_wdog_start(struct watchdog_device * wdog)635*4882a593Smuzhiyun static int abx80x_wdog_start(struct watchdog_device *wdog)
636*4882a593Smuzhiyun {
637*4882a593Smuzhiyun return __abx80x_wdog_set_timeout(wdog, wdog->timeout);
638*4882a593Smuzhiyun }
639*4882a593Smuzhiyun
abx80x_wdog_stop(struct watchdog_device * wdog)640*4882a593Smuzhiyun static int abx80x_wdog_stop(struct watchdog_device *wdog)
641*4882a593Smuzhiyun {
642*4882a593Smuzhiyun return __abx80x_wdog_set_timeout(wdog, 0);
643*4882a593Smuzhiyun }
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun static const struct watchdog_info abx80x_wdog_info = {
646*4882a593Smuzhiyun .identity = "abx80x watchdog",
647*4882a593Smuzhiyun .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
648*4882a593Smuzhiyun };
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun static const struct watchdog_ops abx80x_wdog_ops = {
651*4882a593Smuzhiyun .owner = THIS_MODULE,
652*4882a593Smuzhiyun .start = abx80x_wdog_start,
653*4882a593Smuzhiyun .stop = abx80x_wdog_stop,
654*4882a593Smuzhiyun .ping = abx80x_wdog_ping,
655*4882a593Smuzhiyun .set_timeout = abx80x_wdog_set_timeout,
656*4882a593Smuzhiyun };
657*4882a593Smuzhiyun
abx80x_setup_watchdog(struct abx80x_priv * priv)658*4882a593Smuzhiyun static int abx80x_setup_watchdog(struct abx80x_priv *priv)
659*4882a593Smuzhiyun {
660*4882a593Smuzhiyun priv->wdog.parent = &priv->client->dev;
661*4882a593Smuzhiyun priv->wdog.ops = &abx80x_wdog_ops;
662*4882a593Smuzhiyun priv->wdog.info = &abx80x_wdog_info;
663*4882a593Smuzhiyun priv->wdog.min_timeout = 1;
664*4882a593Smuzhiyun priv->wdog.max_timeout = ABX8XX_WDT_MAX_TIME;
665*4882a593Smuzhiyun priv->wdog.timeout = ABX8XX_WDT_MAX_TIME;
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun watchdog_set_drvdata(&priv->wdog, priv);
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun return devm_watchdog_register_device(&priv->client->dev, &priv->wdog);
670*4882a593Smuzhiyun }
671*4882a593Smuzhiyun #else
abx80x_setup_watchdog(struct abx80x_priv * priv)672*4882a593Smuzhiyun static int abx80x_setup_watchdog(struct abx80x_priv *priv)
673*4882a593Smuzhiyun {
674*4882a593Smuzhiyun return 0;
675*4882a593Smuzhiyun }
676*4882a593Smuzhiyun #endif
677*4882a593Smuzhiyun
abx80x_probe(struct i2c_client * client,const struct i2c_device_id * id)678*4882a593Smuzhiyun static int abx80x_probe(struct i2c_client *client,
679*4882a593Smuzhiyun const struct i2c_device_id *id)
680*4882a593Smuzhiyun {
681*4882a593Smuzhiyun struct device_node *np = client->dev.of_node;
682*4882a593Smuzhiyun struct abx80x_priv *priv;
683*4882a593Smuzhiyun int i, data, err, trickle_cfg = -EINVAL;
684*4882a593Smuzhiyun char buf[7];
685*4882a593Smuzhiyun unsigned int part = id->driver_data;
686*4882a593Smuzhiyun unsigned int partnumber;
687*4882a593Smuzhiyun unsigned int majrev, minrev;
688*4882a593Smuzhiyun unsigned int lot;
689*4882a593Smuzhiyun unsigned int wafer;
690*4882a593Smuzhiyun unsigned int uid;
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
693*4882a593Smuzhiyun return -ENODEV;
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun err = i2c_smbus_read_i2c_block_data(client, ABX8XX_REG_ID0,
696*4882a593Smuzhiyun sizeof(buf), buf);
697*4882a593Smuzhiyun if (err < 0) {
698*4882a593Smuzhiyun dev_err(&client->dev, "Unable to read partnumber\n");
699*4882a593Smuzhiyun return -EIO;
700*4882a593Smuzhiyun }
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun partnumber = (buf[0] << 8) | buf[1];
703*4882a593Smuzhiyun majrev = buf[2] >> 3;
704*4882a593Smuzhiyun minrev = buf[2] & 0x7;
705*4882a593Smuzhiyun lot = ((buf[4] & 0x80) << 2) | ((buf[6] & 0x80) << 1) | buf[3];
706*4882a593Smuzhiyun uid = ((buf[4] & 0x7f) << 8) | buf[5];
707*4882a593Smuzhiyun wafer = (buf[6] & 0x7c) >> 2;
708*4882a593Smuzhiyun dev_info(&client->dev, "model %04x, revision %u.%u, lot %x, wafer %x, uid %x\n",
709*4882a593Smuzhiyun partnumber, majrev, minrev, lot, wafer, uid);
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun data = i2c_smbus_read_byte_data(client, ABX8XX_REG_CTRL1);
712*4882a593Smuzhiyun if (data < 0) {
713*4882a593Smuzhiyun dev_err(&client->dev, "Unable to read control register\n");
714*4882a593Smuzhiyun return -EIO;
715*4882a593Smuzhiyun }
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CTRL1,
718*4882a593Smuzhiyun ((data & ~(ABX8XX_CTRL_12_24 |
719*4882a593Smuzhiyun ABX8XX_CTRL_ARST)) |
720*4882a593Smuzhiyun ABX8XX_CTRL_WRITE));
721*4882a593Smuzhiyun if (err < 0) {
722*4882a593Smuzhiyun dev_err(&client->dev, "Unable to write control register\n");
723*4882a593Smuzhiyun return -EIO;
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun /* Configure RV1805 specifics */
727*4882a593Smuzhiyun if (part == RV1805) {
728*4882a593Smuzhiyun /*
729*4882a593Smuzhiyun * Avoid accidentally entering test mode. This can happen
730*4882a593Smuzhiyun * on the RV1805 in case the reserved bit 5 in control2
731*4882a593Smuzhiyun * register is set. RV-1805-C3 datasheet indicates that
732*4882a593Smuzhiyun * the bit should be cleared in section 11h - Control2.
733*4882a593Smuzhiyun */
734*4882a593Smuzhiyun data = i2c_smbus_read_byte_data(client, ABX8XX_REG_CTRL2);
735*4882a593Smuzhiyun if (data < 0) {
736*4882a593Smuzhiyun dev_err(&client->dev,
737*4882a593Smuzhiyun "Unable to read control2 register\n");
738*4882a593Smuzhiyun return -EIO;
739*4882a593Smuzhiyun }
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CTRL2,
742*4882a593Smuzhiyun data & ~ABX8XX_CTRL2_RSVD);
743*4882a593Smuzhiyun if (err < 0) {
744*4882a593Smuzhiyun dev_err(&client->dev,
745*4882a593Smuzhiyun "Unable to write control2 register\n");
746*4882a593Smuzhiyun return -EIO;
747*4882a593Smuzhiyun }
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun /*
750*4882a593Smuzhiyun * Avoid extra power leakage. The RV1805 uses smaller
751*4882a593Smuzhiyun * 10pin package and the EXTI input is not present.
752*4882a593Smuzhiyun * Disable it to avoid leakage.
753*4882a593Smuzhiyun */
754*4882a593Smuzhiyun data = i2c_smbus_read_byte_data(client, ABX8XX_REG_OUT_CTRL);
755*4882a593Smuzhiyun if (data < 0) {
756*4882a593Smuzhiyun dev_err(&client->dev,
757*4882a593Smuzhiyun "Unable to read output control register\n");
758*4882a593Smuzhiyun return -EIO;
759*4882a593Smuzhiyun }
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun /*
762*4882a593Smuzhiyun * Write the configuration key register to enable access to
763*4882a593Smuzhiyun * the config2 register
764*4882a593Smuzhiyun */
765*4882a593Smuzhiyun err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CFG_KEY,
766*4882a593Smuzhiyun ABX8XX_CFG_KEY_MISC);
767*4882a593Smuzhiyun if (err < 0) {
768*4882a593Smuzhiyun dev_err(&client->dev,
769*4882a593Smuzhiyun "Unable to write configuration key\n");
770*4882a593Smuzhiyun return -EIO;
771*4882a593Smuzhiyun }
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun err = i2c_smbus_write_byte_data(client, ABX8XX_REG_OUT_CTRL,
774*4882a593Smuzhiyun data | ABX8XX_OUT_CTRL_EXDS);
775*4882a593Smuzhiyun if (err < 0) {
776*4882a593Smuzhiyun dev_err(&client->dev,
777*4882a593Smuzhiyun "Unable to write output control register\n");
778*4882a593Smuzhiyun return -EIO;
779*4882a593Smuzhiyun }
780*4882a593Smuzhiyun }
781*4882a593Smuzhiyun
782*4882a593Smuzhiyun /* part autodetection */
783*4882a593Smuzhiyun if (part == ABX80X) {
784*4882a593Smuzhiyun for (i = 0; abx80x_caps[i].pn; i++)
785*4882a593Smuzhiyun if (partnumber == abx80x_caps[i].pn)
786*4882a593Smuzhiyun break;
787*4882a593Smuzhiyun if (abx80x_caps[i].pn == 0) {
788*4882a593Smuzhiyun dev_err(&client->dev, "Unknown part: %04x\n",
789*4882a593Smuzhiyun partnumber);
790*4882a593Smuzhiyun return -EINVAL;
791*4882a593Smuzhiyun }
792*4882a593Smuzhiyun part = i;
793*4882a593Smuzhiyun }
794*4882a593Smuzhiyun
795*4882a593Smuzhiyun if (partnumber != abx80x_caps[part].pn) {
796*4882a593Smuzhiyun dev_err(&client->dev, "partnumber mismatch %04x != %04x\n",
797*4882a593Smuzhiyun partnumber, abx80x_caps[part].pn);
798*4882a593Smuzhiyun return -EINVAL;
799*4882a593Smuzhiyun }
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun if (np && abx80x_caps[part].has_tc)
802*4882a593Smuzhiyun trickle_cfg = abx80x_dt_trickle_cfg(client);
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun if (trickle_cfg > 0) {
805*4882a593Smuzhiyun dev_info(&client->dev, "Enabling trickle charger: %02x\n",
806*4882a593Smuzhiyun trickle_cfg);
807*4882a593Smuzhiyun abx80x_enable_trickle_charger(client, trickle_cfg);
808*4882a593Smuzhiyun }
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun err = i2c_smbus_write_byte_data(client, ABX8XX_REG_CD_TIMER_CTL,
811*4882a593Smuzhiyun BIT(2));
812*4882a593Smuzhiyun if (err)
813*4882a593Smuzhiyun return err;
814*4882a593Smuzhiyun
815*4882a593Smuzhiyun priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
816*4882a593Smuzhiyun if (priv == NULL)
817*4882a593Smuzhiyun return -ENOMEM;
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun priv->rtc = devm_rtc_allocate_device(&client->dev);
820*4882a593Smuzhiyun if (IS_ERR(priv->rtc))
821*4882a593Smuzhiyun return PTR_ERR(priv->rtc);
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun priv->rtc->ops = &abx80x_rtc_ops;
824*4882a593Smuzhiyun priv->client = client;
825*4882a593Smuzhiyun
826*4882a593Smuzhiyun i2c_set_clientdata(client, priv);
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun if (abx80x_caps[part].has_wdog) {
829*4882a593Smuzhiyun err = abx80x_setup_watchdog(priv);
830*4882a593Smuzhiyun if (err)
831*4882a593Smuzhiyun return err;
832*4882a593Smuzhiyun }
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun if (client->irq > 0) {
835*4882a593Smuzhiyun dev_info(&client->dev, "IRQ %d supplied\n", client->irq);
836*4882a593Smuzhiyun err = devm_request_threaded_irq(&client->dev, client->irq, NULL,
837*4882a593Smuzhiyun abx80x_handle_irq,
838*4882a593Smuzhiyun IRQF_SHARED | IRQF_ONESHOT,
839*4882a593Smuzhiyun "abx8xx",
840*4882a593Smuzhiyun client);
841*4882a593Smuzhiyun if (err) {
842*4882a593Smuzhiyun dev_err(&client->dev, "unable to request IRQ, alarms disabled\n");
843*4882a593Smuzhiyun client->irq = 0;
844*4882a593Smuzhiyun }
845*4882a593Smuzhiyun }
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun err = rtc_add_group(priv->rtc, &rtc_calib_attr_group);
848*4882a593Smuzhiyun if (err) {
849*4882a593Smuzhiyun dev_err(&client->dev, "Failed to create sysfs group: %d\n",
850*4882a593Smuzhiyun err);
851*4882a593Smuzhiyun return err;
852*4882a593Smuzhiyun }
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun return rtc_register_device(priv->rtc);
855*4882a593Smuzhiyun }
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun static const struct i2c_device_id abx80x_id[] = {
858*4882a593Smuzhiyun { "abx80x", ABX80X },
859*4882a593Smuzhiyun { "ab0801", AB0801 },
860*4882a593Smuzhiyun { "ab0803", AB0803 },
861*4882a593Smuzhiyun { "ab0804", AB0804 },
862*4882a593Smuzhiyun { "ab0805", AB0805 },
863*4882a593Smuzhiyun { "ab1801", AB1801 },
864*4882a593Smuzhiyun { "ab1803", AB1803 },
865*4882a593Smuzhiyun { "ab1804", AB1804 },
866*4882a593Smuzhiyun { "ab1805", AB1805 },
867*4882a593Smuzhiyun { "rv1805", RV1805 },
868*4882a593Smuzhiyun { }
869*4882a593Smuzhiyun };
870*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, abx80x_id);
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun #ifdef CONFIG_OF
873*4882a593Smuzhiyun static const struct of_device_id abx80x_of_match[] = {
874*4882a593Smuzhiyun {
875*4882a593Smuzhiyun .compatible = "abracon,abx80x",
876*4882a593Smuzhiyun .data = (void *)ABX80X
877*4882a593Smuzhiyun },
878*4882a593Smuzhiyun {
879*4882a593Smuzhiyun .compatible = "abracon,ab0801",
880*4882a593Smuzhiyun .data = (void *)AB0801
881*4882a593Smuzhiyun },
882*4882a593Smuzhiyun {
883*4882a593Smuzhiyun .compatible = "abracon,ab0803",
884*4882a593Smuzhiyun .data = (void *)AB0803
885*4882a593Smuzhiyun },
886*4882a593Smuzhiyun {
887*4882a593Smuzhiyun .compatible = "abracon,ab0804",
888*4882a593Smuzhiyun .data = (void *)AB0804
889*4882a593Smuzhiyun },
890*4882a593Smuzhiyun {
891*4882a593Smuzhiyun .compatible = "abracon,ab0805",
892*4882a593Smuzhiyun .data = (void *)AB0805
893*4882a593Smuzhiyun },
894*4882a593Smuzhiyun {
895*4882a593Smuzhiyun .compatible = "abracon,ab1801",
896*4882a593Smuzhiyun .data = (void *)AB1801
897*4882a593Smuzhiyun },
898*4882a593Smuzhiyun {
899*4882a593Smuzhiyun .compatible = "abracon,ab1803",
900*4882a593Smuzhiyun .data = (void *)AB1803
901*4882a593Smuzhiyun },
902*4882a593Smuzhiyun {
903*4882a593Smuzhiyun .compatible = "abracon,ab1804",
904*4882a593Smuzhiyun .data = (void *)AB1804
905*4882a593Smuzhiyun },
906*4882a593Smuzhiyun {
907*4882a593Smuzhiyun .compatible = "abracon,ab1805",
908*4882a593Smuzhiyun .data = (void *)AB1805
909*4882a593Smuzhiyun },
910*4882a593Smuzhiyun {
911*4882a593Smuzhiyun .compatible = "microcrystal,rv1805",
912*4882a593Smuzhiyun .data = (void *)RV1805
913*4882a593Smuzhiyun },
914*4882a593Smuzhiyun { }
915*4882a593Smuzhiyun };
916*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, abx80x_of_match);
917*4882a593Smuzhiyun #endif
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun static struct i2c_driver abx80x_driver = {
920*4882a593Smuzhiyun .driver = {
921*4882a593Smuzhiyun .name = "rtc-abx80x",
922*4882a593Smuzhiyun .of_match_table = of_match_ptr(abx80x_of_match),
923*4882a593Smuzhiyun },
924*4882a593Smuzhiyun .probe = abx80x_probe,
925*4882a593Smuzhiyun .id_table = abx80x_id,
926*4882a593Smuzhiyun };
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun module_i2c_driver(abx80x_driver);
929*4882a593Smuzhiyun
930*4882a593Smuzhiyun MODULE_AUTHOR("Philippe De Muyter <phdm@macqel.be>");
931*4882a593Smuzhiyun MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
932*4882a593Smuzhiyun MODULE_DESCRIPTION("Abracon ABX80X RTC driver");
933*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
934