1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) Rockchip Electronics Co.Ltd
4*4882a593Smuzhiyun * Author: Felix Zeng <felix.zeng@rock-chips.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/delay.h>
8*4882a593Smuzhiyun #include <linux/iommu.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "rknpu_reset.h"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
rknpu_reset_control_get(struct device * dev,const char * name)13*4882a593Smuzhiyun static inline struct reset_control *rknpu_reset_control_get(struct device *dev,
14*4882a593Smuzhiyun const char *name)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun struct reset_control *rst = NULL;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun rst = devm_reset_control_get(dev, name);
19*4882a593Smuzhiyun if (IS_ERR(rst))
20*4882a593Smuzhiyun LOG_DEV_ERROR(dev,
21*4882a593Smuzhiyun "failed to get rknpu reset control: %s, %ld\n",
22*4882a593Smuzhiyun name, PTR_ERR(rst));
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun return rst;
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun #endif
27*4882a593Smuzhiyun
rknpu_reset_get(struct rknpu_device * rknpu_dev)28*4882a593Smuzhiyun int rknpu_reset_get(struct rknpu_device *rknpu_dev)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
31*4882a593Smuzhiyun struct reset_control *srst_a = NULL;
32*4882a593Smuzhiyun struct reset_control *srst_h = NULL;
33*4882a593Smuzhiyun int i = 0;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun for (i = 0; i < rknpu_dev->config->num_resets; i++) {
36*4882a593Smuzhiyun srst_a = rknpu_reset_control_get(
37*4882a593Smuzhiyun rknpu_dev->dev,
38*4882a593Smuzhiyun rknpu_dev->config->resets[i].srst_a_name);
39*4882a593Smuzhiyun if (IS_ERR(srst_a))
40*4882a593Smuzhiyun return PTR_ERR(srst_a);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun rknpu_dev->srst_a[i] = srst_a;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun srst_h = rknpu_reset_control_get(
45*4882a593Smuzhiyun rknpu_dev->dev,
46*4882a593Smuzhiyun rknpu_dev->config->resets[i].srst_h_name);
47*4882a593Smuzhiyun if (IS_ERR(srst_h))
48*4882a593Smuzhiyun return PTR_ERR(srst_h);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun rknpu_dev->srst_h[i] = srst_h;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun #endif
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun return 0;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
rknpu_reset_assert(struct reset_control * rst)58*4882a593Smuzhiyun static int rknpu_reset_assert(struct reset_control *rst)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun int ret = -EINVAL;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun if (!rst)
63*4882a593Smuzhiyun return -EINVAL;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun ret = reset_control_assert(rst);
66*4882a593Smuzhiyun if (ret < 0) {
67*4882a593Smuzhiyun LOG_ERROR("failed to assert rknpu reset: %d\n", ret);
68*4882a593Smuzhiyun return ret;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun return 0;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
rknpu_reset_deassert(struct reset_control * rst)74*4882a593Smuzhiyun static int rknpu_reset_deassert(struct reset_control *rst)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun int ret = -EINVAL;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun if (!rst)
79*4882a593Smuzhiyun return -EINVAL;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun ret = reset_control_deassert(rst);
82*4882a593Smuzhiyun if (ret < 0) {
83*4882a593Smuzhiyun LOG_ERROR("failed to deassert rknpu reset: %d\n", ret);
84*4882a593Smuzhiyun return ret;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun return 0;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun #endif
90*4882a593Smuzhiyun
rknpu_soft_reset(struct rknpu_device * rknpu_dev)91*4882a593Smuzhiyun int rknpu_soft_reset(struct rknpu_device *rknpu_dev)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
94*4882a593Smuzhiyun struct iommu_domain *domain = NULL;
95*4882a593Smuzhiyun struct rknpu_subcore_data *subcore_data = NULL;
96*4882a593Smuzhiyun int ret = -EINVAL, i = 0;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun if (rknpu_dev->bypass_soft_reset) {
99*4882a593Smuzhiyun LOG_WARN("bypass soft reset\n");
100*4882a593Smuzhiyun return 0;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun if (!mutex_trylock(&rknpu_dev->reset_lock))
104*4882a593Smuzhiyun return 0;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun rknpu_dev->soft_reseting = true;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun msleep(100);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun for (i = 0; i < rknpu_dev->config->num_irqs; ++i) {
111*4882a593Smuzhiyun subcore_data = &rknpu_dev->subcore_datas[i];
112*4882a593Smuzhiyun wake_up(&subcore_data->job_done_wq);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun LOG_INFO("soft reset\n");
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun for (i = 0; i < rknpu_dev->config->num_resets; i++) {
118*4882a593Smuzhiyun ret = rknpu_reset_assert(rknpu_dev->srst_a[i]);
119*4882a593Smuzhiyun ret |= rknpu_reset_assert(rknpu_dev->srst_h[i]);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun udelay(10);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun ret |= rknpu_reset_deassert(rknpu_dev->srst_a[i]);
124*4882a593Smuzhiyun ret |= rknpu_reset_deassert(rknpu_dev->srst_h[i]);
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun if (ret) {
128*4882a593Smuzhiyun LOG_DEV_ERROR(rknpu_dev->dev,
129*4882a593Smuzhiyun "failed to soft reset for rknpu: %d\n", ret);
130*4882a593Smuzhiyun mutex_unlock(&rknpu_dev->reset_lock);
131*4882a593Smuzhiyun return ret;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun if (rknpu_dev->iommu_en)
135*4882a593Smuzhiyun domain = iommu_get_domain_for_dev(rknpu_dev->dev);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun if (domain) {
138*4882a593Smuzhiyun iommu_detach_device(domain, rknpu_dev->dev);
139*4882a593Smuzhiyun iommu_attach_device(domain, rknpu_dev->dev);
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun rknpu_dev->soft_reseting = false;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun mutex_unlock(&rknpu_dev->reset_lock);
145*4882a593Smuzhiyun #endif
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun return 0;
148*4882a593Smuzhiyun }
149