xref: /OK3568_Linux_fs/kernel/drivers/rknpu/rknpu_drv.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) Rockchip Electronics Co.Ltd
4*4882a593Smuzhiyun  * Author: Felix Zeng <felix.zeng@rock-chips.com>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/dma-buf.h>
8*4882a593Smuzhiyun #include <linux/dma-mapping.h>
9*4882a593Smuzhiyun #include <linux/fs.h>
10*4882a593Smuzhiyun #include <linux/interrupt.h>
11*4882a593Smuzhiyun #include <linux/irq.h>
12*4882a593Smuzhiyun #include <linux/irqdomain.h>
13*4882a593Smuzhiyun #include <linux/iopoll.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/of.h>
16*4882a593Smuzhiyun #include <linux/of_device.h>
17*4882a593Smuzhiyun #include <linux/of_irq.h>
18*4882a593Smuzhiyun #include <linux/of_platform.h>
19*4882a593Smuzhiyun #include <linux/of_reserved_mem.h>
20*4882a593Smuzhiyun #include <linux/platform_device.h>
21*4882a593Smuzhiyun #include <linux/printk.h>
22*4882a593Smuzhiyun #include <linux/slab.h>
23*4882a593Smuzhiyun #include <linux/spinlock.h>
24*4882a593Smuzhiyun #include <linux/time.h>
25*4882a593Smuzhiyun #include <linux/uaccess.h>
26*4882a593Smuzhiyun #include <linux/ktime.h>
27*4882a593Smuzhiyun #include <linux/delay.h>
28*4882a593Smuzhiyun #include <linux/wait.h>
29*4882a593Smuzhiyun #include <linux/sched.h>
30*4882a593Smuzhiyun #include <linux/clk.h>
31*4882a593Smuzhiyun #include <linux/clk-provider.h>
32*4882a593Smuzhiyun #include <linux/pm_domain.h>
33*4882a593Smuzhiyun #include <linux/pm_runtime.h>
34*4882a593Smuzhiyun #include <linux/devfreq_cooling.h>
35*4882a593Smuzhiyun #include <linux/regmap.h>
36*4882a593Smuzhiyun #include <linux/of_address.h>
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
39*4882a593Smuzhiyun #include <soc/rockchip/rockchip_iommu.h>
40*4882a593Smuzhiyun #include <soc/rockchip/rockchip_opp_select.h>
41*4882a593Smuzhiyun #include <soc/rockchip/rockchip_system_monitor.h>
42*4882a593Smuzhiyun #include <soc/rockchip/rockchip_ipa.h>
43*4882a593Smuzhiyun #ifdef CONFIG_PM_DEVFREQ
44*4882a593Smuzhiyun #include <../drivers/devfreq/governor.h>
45*4882a593Smuzhiyun #endif
46*4882a593Smuzhiyun #endif
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #include "rknpu_ioctl.h"
49*4882a593Smuzhiyun #include "rknpu_reset.h"
50*4882a593Smuzhiyun #include "rknpu_fence.h"
51*4882a593Smuzhiyun #include "rknpu_drv.h"
52*4882a593Smuzhiyun #include "rknpu_gem.h"
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #ifdef CONFIG_ROCKCHIP_RKNPU_DRM_GEM
55*4882a593Smuzhiyun #include <drm/drm_device.h>
56*4882a593Smuzhiyun #include <drm/drm_ioctl.h>
57*4882a593Smuzhiyun #include <drm/drm_file.h>
58*4882a593Smuzhiyun #include <drm/drm_drv.h>
59*4882a593Smuzhiyun #include "rknpu_gem.h"
60*4882a593Smuzhiyun #endif
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun #ifdef CONFIG_ROCKCHIP_RKNPU_DMA_HEAP
63*4882a593Smuzhiyun #include <linux/rk-dma-heap.h>
64*4882a593Smuzhiyun #include "rknpu_mem.h"
65*4882a593Smuzhiyun #endif
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun #define POWER_DOWN_FREQ 200000000
68*4882a593Smuzhiyun #define NPU_MMU_DISABLED_POLL_PERIOD_US 1000
69*4882a593Smuzhiyun #define NPU_MMU_DISABLED_POLL_TIMEOUT_US 20000
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun static int bypass_irq_handler;
72*4882a593Smuzhiyun module_param(bypass_irq_handler, int, 0644);
73*4882a593Smuzhiyun MODULE_PARM_DESC(bypass_irq_handler,
74*4882a593Smuzhiyun 		 "bypass RKNPU irq handler if set it to 1, disabled by default");
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun static int bypass_soft_reset;
77*4882a593Smuzhiyun module_param(bypass_soft_reset, int, 0644);
78*4882a593Smuzhiyun MODULE_PARM_DESC(bypass_soft_reset,
79*4882a593Smuzhiyun 		 "bypass RKNPU soft reset if set it to 1, disabled by default");
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun struct rknpu_irqs_data {
82*4882a593Smuzhiyun 	const char *name;
83*4882a593Smuzhiyun 	irqreturn_t (*irq_hdl)(int irq, void *ctx);
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun static const struct rknpu_irqs_data rknpu_irqs[] = {
87*4882a593Smuzhiyun 	{ "npu_irq", rknpu_core0_irq_handler }
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun static const struct rknpu_irqs_data rk3588_npu_irqs[] = {
91*4882a593Smuzhiyun 	{ "npu0_irq", rknpu_core0_irq_handler },
92*4882a593Smuzhiyun 	{ "npu1_irq", rknpu_core1_irq_handler },
93*4882a593Smuzhiyun 	{ "npu2_irq", rknpu_core2_irq_handler }
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun static const struct rknpu_reset_data rknpu_resets[] = { { "srst_a",
97*4882a593Smuzhiyun 							  "srst_h" } };
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun static const struct rknpu_reset_data rk3588_npu_resets[] = {
100*4882a593Smuzhiyun 	{ "srst_a0", "srst_h0" },
101*4882a593Smuzhiyun 	{ "srst_a1", "srst_h1" },
102*4882a593Smuzhiyun 	{ "srst_a2", "srst_h2" }
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun static const struct rknpu_config rk356x_rknpu_config = {
106*4882a593Smuzhiyun 	.bw_priority_addr = 0xfe180008,
107*4882a593Smuzhiyun 	.bw_priority_length = 0x10,
108*4882a593Smuzhiyun 	.dma_mask = DMA_BIT_MASK(32),
109*4882a593Smuzhiyun 	.pc_data_amount_scale = 1,
110*4882a593Smuzhiyun 	.pc_task_number_bits = 12,
111*4882a593Smuzhiyun 	.pc_task_number_mask = 0xfff,
112*4882a593Smuzhiyun 	.pc_task_status_offset = 0x3c,
113*4882a593Smuzhiyun 	.pc_dma_ctrl = 0,
114*4882a593Smuzhiyun 	.bw_enable = 1,
115*4882a593Smuzhiyun 	.irqs = rknpu_irqs,
116*4882a593Smuzhiyun 	.resets = rknpu_resets,
117*4882a593Smuzhiyun 	.num_irqs = ARRAY_SIZE(rknpu_irqs),
118*4882a593Smuzhiyun 	.num_resets = ARRAY_SIZE(rknpu_resets),
119*4882a593Smuzhiyun 	.nbuf_phyaddr = 0,
120*4882a593Smuzhiyun 	.nbuf_size = 0
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun static const struct rknpu_config rk3588_rknpu_config = {
124*4882a593Smuzhiyun 	.bw_priority_addr = 0x0,
125*4882a593Smuzhiyun 	.bw_priority_length = 0x0,
126*4882a593Smuzhiyun 	.dma_mask = DMA_BIT_MASK(40),
127*4882a593Smuzhiyun 	.pc_data_amount_scale = 2,
128*4882a593Smuzhiyun 	.pc_task_number_bits = 12,
129*4882a593Smuzhiyun 	.pc_task_number_mask = 0xfff,
130*4882a593Smuzhiyun 	.pc_task_status_offset = 0x3c,
131*4882a593Smuzhiyun 	.pc_dma_ctrl = 0,
132*4882a593Smuzhiyun 	.bw_enable = 0,
133*4882a593Smuzhiyun 	.irqs = rk3588_npu_irqs,
134*4882a593Smuzhiyun 	.resets = rk3588_npu_resets,
135*4882a593Smuzhiyun 	.num_irqs = ARRAY_SIZE(rk3588_npu_irqs),
136*4882a593Smuzhiyun 	.num_resets = ARRAY_SIZE(rk3588_npu_resets),
137*4882a593Smuzhiyun 	.nbuf_phyaddr = 0,
138*4882a593Smuzhiyun 	.nbuf_size = 0
139*4882a593Smuzhiyun };
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun static const struct rknpu_config rv1106_rknpu_config = {
142*4882a593Smuzhiyun 	.bw_priority_addr = 0x0,
143*4882a593Smuzhiyun 	.bw_priority_length = 0x0,
144*4882a593Smuzhiyun 	.dma_mask = DMA_BIT_MASK(32),
145*4882a593Smuzhiyun 	.pc_data_amount_scale = 2,
146*4882a593Smuzhiyun 	.pc_task_number_bits = 16,
147*4882a593Smuzhiyun 	.pc_task_number_mask = 0xffff,
148*4882a593Smuzhiyun 	.pc_task_status_offset = 0x3c,
149*4882a593Smuzhiyun 	.pc_dma_ctrl = 0,
150*4882a593Smuzhiyun 	.bw_enable = 1,
151*4882a593Smuzhiyun 	.irqs = rknpu_irqs,
152*4882a593Smuzhiyun 	.resets = rknpu_resets,
153*4882a593Smuzhiyun 	.num_irqs = ARRAY_SIZE(rknpu_irqs),
154*4882a593Smuzhiyun 	.num_resets = ARRAY_SIZE(rknpu_resets),
155*4882a593Smuzhiyun 	.nbuf_phyaddr = 0,
156*4882a593Smuzhiyun 	.nbuf_size = 0
157*4882a593Smuzhiyun };
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun static const struct rknpu_config rk3562_rknpu_config = {
160*4882a593Smuzhiyun 	.bw_priority_addr = 0x0,
161*4882a593Smuzhiyun 	.bw_priority_length = 0x0,
162*4882a593Smuzhiyun 	.dma_mask = DMA_BIT_MASK(40),
163*4882a593Smuzhiyun 	.pc_data_amount_scale = 2,
164*4882a593Smuzhiyun 	.pc_task_number_bits = 16,
165*4882a593Smuzhiyun 	.pc_task_number_mask = 0xffff,
166*4882a593Smuzhiyun 	.pc_task_status_offset = 0x48,
167*4882a593Smuzhiyun 	.pc_dma_ctrl = 1,
168*4882a593Smuzhiyun 	.bw_enable = 1,
169*4882a593Smuzhiyun 	.irqs = rknpu_irqs,
170*4882a593Smuzhiyun 	.resets = rknpu_resets,
171*4882a593Smuzhiyun 	.num_irqs = ARRAY_SIZE(rknpu_irqs),
172*4882a593Smuzhiyun 	.num_resets = ARRAY_SIZE(rknpu_resets),
173*4882a593Smuzhiyun 	.nbuf_phyaddr = 0xfe400000,
174*4882a593Smuzhiyun 	.nbuf_size = 256 * 1024
175*4882a593Smuzhiyun };
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun /* driver probe and init */
178*4882a593Smuzhiyun static const struct of_device_id rknpu_of_match[] = {
179*4882a593Smuzhiyun 	{
180*4882a593Smuzhiyun 		.compatible = "rockchip,rknpu",
181*4882a593Smuzhiyun 		.data = &rk356x_rknpu_config,
182*4882a593Smuzhiyun 	},
183*4882a593Smuzhiyun 	{
184*4882a593Smuzhiyun 		.compatible = "rockchip,rk3568-rknpu",
185*4882a593Smuzhiyun 		.data = &rk356x_rknpu_config,
186*4882a593Smuzhiyun 	},
187*4882a593Smuzhiyun 	{
188*4882a593Smuzhiyun 		.compatible = "rockchip,rk3588-rknpu",
189*4882a593Smuzhiyun 		.data = &rk3588_rknpu_config,
190*4882a593Smuzhiyun 	},
191*4882a593Smuzhiyun 	{
192*4882a593Smuzhiyun 		.compatible = "rockchip,rv1106-rknpu",
193*4882a593Smuzhiyun 		.data = &rv1106_rknpu_config,
194*4882a593Smuzhiyun 	},
195*4882a593Smuzhiyun 	{
196*4882a593Smuzhiyun 		.compatible = "rockchip,rk3562-rknpu",
197*4882a593Smuzhiyun 		.data = &rk3562_rknpu_config,
198*4882a593Smuzhiyun 	},
199*4882a593Smuzhiyun 	{},
200*4882a593Smuzhiyun };
201*4882a593Smuzhiyun 
rknpu_get_drv_version(uint32_t * version)202*4882a593Smuzhiyun static int rknpu_get_drv_version(uint32_t *version)
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun 	*version = RKNPU_GET_DRV_VERSION_CODE(DRIVER_MAJOR, DRIVER_MINOR,
205*4882a593Smuzhiyun 					      DRIVER_PATCHLEVEL);
206*4882a593Smuzhiyun 	return 0;
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun static int rknpu_power_on(struct rknpu_device *rknpu_dev);
210*4882a593Smuzhiyun static int rknpu_power_off(struct rknpu_device *rknpu_dev);
211*4882a593Smuzhiyun 
rknpu_power_off_delay_work(struct work_struct * power_off_work)212*4882a593Smuzhiyun static void rknpu_power_off_delay_work(struct work_struct *power_off_work)
213*4882a593Smuzhiyun {
214*4882a593Smuzhiyun 	struct rknpu_device *rknpu_dev =
215*4882a593Smuzhiyun 		container_of(to_delayed_work(power_off_work),
216*4882a593Smuzhiyun 			     struct rknpu_device, power_off_work);
217*4882a593Smuzhiyun 	mutex_lock(&rknpu_dev->power_lock);
218*4882a593Smuzhiyun 	if (atomic_dec_if_positive(&rknpu_dev->power_refcount) == 0)
219*4882a593Smuzhiyun 		rknpu_power_off(rknpu_dev);
220*4882a593Smuzhiyun 	mutex_unlock(&rknpu_dev->power_lock);
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun 
rknpu_power_get(struct rknpu_device * rknpu_dev)223*4882a593Smuzhiyun int rknpu_power_get(struct rknpu_device *rknpu_dev)
224*4882a593Smuzhiyun {
225*4882a593Smuzhiyun 	int ret = 0;
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	mutex_lock(&rknpu_dev->power_lock);
228*4882a593Smuzhiyun 	if (atomic_inc_return(&rknpu_dev->power_refcount) == 1)
229*4882a593Smuzhiyun 		ret = rknpu_power_on(rknpu_dev);
230*4882a593Smuzhiyun 	mutex_unlock(&rknpu_dev->power_lock);
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	return ret;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun 
rknpu_power_put(struct rknpu_device * rknpu_dev)235*4882a593Smuzhiyun int rknpu_power_put(struct rknpu_device *rknpu_dev)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun 	int ret = 0;
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	mutex_lock(&rknpu_dev->power_lock);
240*4882a593Smuzhiyun 	if (atomic_dec_if_positive(&rknpu_dev->power_refcount) == 0)
241*4882a593Smuzhiyun 		ret = rknpu_power_off(rknpu_dev);
242*4882a593Smuzhiyun 	mutex_unlock(&rknpu_dev->power_lock);
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	return ret;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun 
rknpu_power_put_delay(struct rknpu_device * rknpu_dev)247*4882a593Smuzhiyun static int rknpu_power_put_delay(struct rknpu_device *rknpu_dev)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun 	if (rknpu_dev->power_put_delay == 0)
250*4882a593Smuzhiyun 		return rknpu_power_put(rknpu_dev);
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	mutex_lock(&rknpu_dev->power_lock);
253*4882a593Smuzhiyun 	if (atomic_read(&rknpu_dev->power_refcount) == 1)
254*4882a593Smuzhiyun 		queue_delayed_work(
255*4882a593Smuzhiyun 			rknpu_dev->power_off_wq, &rknpu_dev->power_off_work,
256*4882a593Smuzhiyun 			msecs_to_jiffies(rknpu_dev->power_put_delay));
257*4882a593Smuzhiyun 	else
258*4882a593Smuzhiyun 		atomic_dec_if_positive(&rknpu_dev->power_refcount);
259*4882a593Smuzhiyun 	mutex_unlock(&rknpu_dev->power_lock);
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	return 0;
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun 
rknpu_action(struct rknpu_device * rknpu_dev,struct rknpu_action * args)264*4882a593Smuzhiyun static int rknpu_action(struct rknpu_device *rknpu_dev,
265*4882a593Smuzhiyun 			struct rknpu_action *args)
266*4882a593Smuzhiyun {
267*4882a593Smuzhiyun 	int ret = -EINVAL;
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	switch (args->flags) {
270*4882a593Smuzhiyun 	case RKNPU_GET_HW_VERSION:
271*4882a593Smuzhiyun 		ret = rknpu_get_hw_version(rknpu_dev, &args->value);
272*4882a593Smuzhiyun 		break;
273*4882a593Smuzhiyun 	case RKNPU_GET_DRV_VERSION:
274*4882a593Smuzhiyun 		ret = rknpu_get_drv_version(&args->value);
275*4882a593Smuzhiyun 		break;
276*4882a593Smuzhiyun 	case RKNPU_GET_FREQ:
277*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
278*4882a593Smuzhiyun 		args->value = clk_get_rate(rknpu_dev->clks[0].clk);
279*4882a593Smuzhiyun #endif
280*4882a593Smuzhiyun 		ret = 0;
281*4882a593Smuzhiyun 		break;
282*4882a593Smuzhiyun 	case RKNPU_SET_FREQ:
283*4882a593Smuzhiyun 		break;
284*4882a593Smuzhiyun 	case RKNPU_GET_VOLT:
285*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
286*4882a593Smuzhiyun 		args->value = regulator_get_voltage(rknpu_dev->vdd);
287*4882a593Smuzhiyun #endif
288*4882a593Smuzhiyun 		ret = 0;
289*4882a593Smuzhiyun 		break;
290*4882a593Smuzhiyun 	case RKNPU_SET_VOLT:
291*4882a593Smuzhiyun 		break;
292*4882a593Smuzhiyun 	case RKNPU_ACT_RESET:
293*4882a593Smuzhiyun 		ret = rknpu_soft_reset(rknpu_dev);
294*4882a593Smuzhiyun 		break;
295*4882a593Smuzhiyun 	case RKNPU_GET_BW_PRIORITY:
296*4882a593Smuzhiyun 		ret = rknpu_get_bw_priority(rknpu_dev, &args->value, NULL,
297*4882a593Smuzhiyun 					    NULL);
298*4882a593Smuzhiyun 		break;
299*4882a593Smuzhiyun 	case RKNPU_SET_BW_PRIORITY:
300*4882a593Smuzhiyun 		ret = rknpu_set_bw_priority(rknpu_dev, args->value, 0, 0);
301*4882a593Smuzhiyun 		break;
302*4882a593Smuzhiyun 	case RKNPU_GET_BW_EXPECT:
303*4882a593Smuzhiyun 		ret = rknpu_get_bw_priority(rknpu_dev, NULL, &args->value,
304*4882a593Smuzhiyun 					    NULL);
305*4882a593Smuzhiyun 		break;
306*4882a593Smuzhiyun 	case RKNPU_SET_BW_EXPECT:
307*4882a593Smuzhiyun 		ret = rknpu_set_bw_priority(rknpu_dev, 0, args->value, 0);
308*4882a593Smuzhiyun 		break;
309*4882a593Smuzhiyun 	case RKNPU_GET_BW_TW:
310*4882a593Smuzhiyun 		ret = rknpu_get_bw_priority(rknpu_dev, NULL, NULL,
311*4882a593Smuzhiyun 					    &args->value);
312*4882a593Smuzhiyun 		break;
313*4882a593Smuzhiyun 	case RKNPU_SET_BW_TW:
314*4882a593Smuzhiyun 		ret = rknpu_set_bw_priority(rknpu_dev, 0, 0, args->value);
315*4882a593Smuzhiyun 		break;
316*4882a593Smuzhiyun 	case RKNPU_ACT_CLR_TOTAL_RW_AMOUNT:
317*4882a593Smuzhiyun 		ret = rknpu_clear_rw_amount(rknpu_dev);
318*4882a593Smuzhiyun 		break;
319*4882a593Smuzhiyun 	case RKNPU_GET_DT_WR_AMOUNT:
320*4882a593Smuzhiyun 		ret = rknpu_get_rw_amount(rknpu_dev, &args->value, NULL, NULL);
321*4882a593Smuzhiyun 		break;
322*4882a593Smuzhiyun 	case RKNPU_GET_DT_RD_AMOUNT:
323*4882a593Smuzhiyun 		ret = rknpu_get_rw_amount(rknpu_dev, NULL, &args->value, NULL);
324*4882a593Smuzhiyun 		break;
325*4882a593Smuzhiyun 	case RKNPU_GET_WT_RD_AMOUNT:
326*4882a593Smuzhiyun 		ret = rknpu_get_rw_amount(rknpu_dev, NULL, NULL, &args->value);
327*4882a593Smuzhiyun 		break;
328*4882a593Smuzhiyun 	case RKNPU_GET_TOTAL_RW_AMOUNT:
329*4882a593Smuzhiyun 		ret = rknpu_get_total_rw_amount(rknpu_dev, &args->value);
330*4882a593Smuzhiyun 		break;
331*4882a593Smuzhiyun 	case RKNPU_GET_IOMMU_EN:
332*4882a593Smuzhiyun 		args->value = rknpu_dev->iommu_en;
333*4882a593Smuzhiyun 		ret = 0;
334*4882a593Smuzhiyun 		break;
335*4882a593Smuzhiyun 	case RKNPU_SET_PROC_NICE:
336*4882a593Smuzhiyun 		set_user_nice(current, *(int32_t *)&args->value);
337*4882a593Smuzhiyun 		ret = 0;
338*4882a593Smuzhiyun 		break;
339*4882a593Smuzhiyun 	case RKNPU_GET_TOTAL_SRAM_SIZE:
340*4882a593Smuzhiyun 		if (rknpu_dev->sram_mm)
341*4882a593Smuzhiyun 			args->value = rknpu_dev->sram_mm->total_chunks *
342*4882a593Smuzhiyun 				      rknpu_dev->sram_mm->chunk_size;
343*4882a593Smuzhiyun 		else
344*4882a593Smuzhiyun 			args->value = 0;
345*4882a593Smuzhiyun 		ret = 0;
346*4882a593Smuzhiyun 		break;
347*4882a593Smuzhiyun 	case RKNPU_GET_FREE_SRAM_SIZE:
348*4882a593Smuzhiyun 		if (rknpu_dev->sram_mm)
349*4882a593Smuzhiyun 			args->value = rknpu_dev->sram_mm->free_chunks *
350*4882a593Smuzhiyun 				      rknpu_dev->sram_mm->chunk_size;
351*4882a593Smuzhiyun 		else
352*4882a593Smuzhiyun 			args->value = 0;
353*4882a593Smuzhiyun 		ret = 0;
354*4882a593Smuzhiyun 		break;
355*4882a593Smuzhiyun 	default:
356*4882a593Smuzhiyun 		ret = -EINVAL;
357*4882a593Smuzhiyun 		break;
358*4882a593Smuzhiyun 	}
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 	return ret;
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun #ifdef CONFIG_ROCKCHIP_RKNPU_DMA_HEAP
rknpu_open(struct inode * inode,struct file * file)364*4882a593Smuzhiyun static int rknpu_open(struct inode *inode, struct file *file)
365*4882a593Smuzhiyun {
366*4882a593Smuzhiyun 	struct rknpu_device *rknpu_dev =
367*4882a593Smuzhiyun 		container_of(file->private_data, struct rknpu_device, miscdev);
368*4882a593Smuzhiyun 	struct rknpu_session *session = NULL;
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun 	session = kzalloc(sizeof(*session), GFP_KERNEL);
371*4882a593Smuzhiyun 	if (!session) {
372*4882a593Smuzhiyun 		LOG_ERROR("rknpu session alloc failed\n");
373*4882a593Smuzhiyun 		return -ENOMEM;
374*4882a593Smuzhiyun 	}
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun 	session->rknpu_dev = rknpu_dev;
377*4882a593Smuzhiyun 	INIT_LIST_HEAD(&session->list);
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun 	file->private_data = (void *)session;
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	return nonseekable_open(inode, file);
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun 
rknpu_release(struct inode * inode,struct file * file)384*4882a593Smuzhiyun static int rknpu_release(struct inode *inode, struct file *file)
385*4882a593Smuzhiyun {
386*4882a593Smuzhiyun 	struct rknpu_mem_object *entry;
387*4882a593Smuzhiyun 	struct rknpu_session *session = file->private_data;
388*4882a593Smuzhiyun 	struct rknpu_device *rknpu_dev = session->rknpu_dev;
389*4882a593Smuzhiyun 	LIST_HEAD(local_list);
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 	spin_lock(&rknpu_dev->lock);
392*4882a593Smuzhiyun 	list_replace_init(&session->list, &local_list);
393*4882a593Smuzhiyun 	file->private_data = NULL;
394*4882a593Smuzhiyun 	spin_unlock(&rknpu_dev->lock);
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	while (!list_empty(&local_list)) {
397*4882a593Smuzhiyun 		entry = list_first_entry(&local_list, struct rknpu_mem_object,
398*4882a593Smuzhiyun 					 head);
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 		LOG_DEBUG(
401*4882a593Smuzhiyun 			"Fd close free rknpu_obj: %#llx, rknpu_obj->dma_addr: %#llx\n",
402*4882a593Smuzhiyun 			(__u64)(uintptr_t)entry, (__u64)entry->dma_addr);
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 		vunmap(entry->kv_addr);
405*4882a593Smuzhiyun 		entry->kv_addr = NULL;
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 		if (!entry->owner)
408*4882a593Smuzhiyun 			dma_buf_put(entry->dmabuf);
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 		list_del(&entry->head);
411*4882a593Smuzhiyun 		kfree(entry);
412*4882a593Smuzhiyun 	}
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	kfree(session);
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 	return 0;
417*4882a593Smuzhiyun }
418*4882a593Smuzhiyun 
rknpu_action_ioctl(struct rknpu_device * rknpu_dev,unsigned long data)419*4882a593Smuzhiyun static int rknpu_action_ioctl(struct rknpu_device *rknpu_dev,
420*4882a593Smuzhiyun 			      unsigned long data)
421*4882a593Smuzhiyun {
422*4882a593Smuzhiyun 	struct rknpu_action args;
423*4882a593Smuzhiyun 	int ret = -EINVAL;
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun 	if (unlikely(copy_from_user(&args, (struct rknpu_action *)data,
426*4882a593Smuzhiyun 				    sizeof(struct rknpu_action)))) {
427*4882a593Smuzhiyun 		LOG_ERROR("%s: copy_from_user failed\n", __func__);
428*4882a593Smuzhiyun 		ret = -EFAULT;
429*4882a593Smuzhiyun 		return ret;
430*4882a593Smuzhiyun 	}
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	ret = rknpu_action(rknpu_dev, &args);
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	if (unlikely(copy_to_user((struct rknpu_action *)data, &args,
435*4882a593Smuzhiyun 				  sizeof(struct rknpu_action)))) {
436*4882a593Smuzhiyun 		LOG_ERROR("%s: copy_to_user failed\n", __func__);
437*4882a593Smuzhiyun 		ret = -EFAULT;
438*4882a593Smuzhiyun 		return ret;
439*4882a593Smuzhiyun 	}
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun 	return ret;
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun 
rknpu_ioctl(struct file * file,uint32_t cmd,unsigned long arg)444*4882a593Smuzhiyun static long rknpu_ioctl(struct file *file, uint32_t cmd, unsigned long arg)
445*4882a593Smuzhiyun {
446*4882a593Smuzhiyun 	long ret = -EINVAL;
447*4882a593Smuzhiyun 	struct rknpu_device *rknpu_dev = NULL;
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun 	if (!file->private_data)
450*4882a593Smuzhiyun 		return -EINVAL;
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun 	rknpu_dev = ((struct rknpu_session *)file->private_data)->rknpu_dev;
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun 	rknpu_power_get(rknpu_dev);
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 	switch (cmd) {
457*4882a593Smuzhiyun 	case IOCTL_RKNPU_ACTION:
458*4882a593Smuzhiyun 		ret = rknpu_action_ioctl(rknpu_dev, arg);
459*4882a593Smuzhiyun 		break;
460*4882a593Smuzhiyun 	case IOCTL_RKNPU_SUBMIT:
461*4882a593Smuzhiyun 		ret = rknpu_submit_ioctl(rknpu_dev, arg);
462*4882a593Smuzhiyun 		break;
463*4882a593Smuzhiyun 	case IOCTL_RKNPU_MEM_CREATE:
464*4882a593Smuzhiyun 		ret = rknpu_mem_create_ioctl(rknpu_dev, arg, file);
465*4882a593Smuzhiyun 		break;
466*4882a593Smuzhiyun 	case RKNPU_MEM_MAP:
467*4882a593Smuzhiyun 		break;
468*4882a593Smuzhiyun 	case IOCTL_RKNPU_MEM_DESTROY:
469*4882a593Smuzhiyun 		ret = rknpu_mem_destroy_ioctl(rknpu_dev, arg, file);
470*4882a593Smuzhiyun 		break;
471*4882a593Smuzhiyun 	case IOCTL_RKNPU_MEM_SYNC:
472*4882a593Smuzhiyun 		ret = rknpu_mem_sync_ioctl(rknpu_dev, arg);
473*4882a593Smuzhiyun 		break;
474*4882a593Smuzhiyun 	default:
475*4882a593Smuzhiyun 		break;
476*4882a593Smuzhiyun 	}
477*4882a593Smuzhiyun 
478*4882a593Smuzhiyun 	rknpu_power_put_delay(rknpu_dev);
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 	return ret;
481*4882a593Smuzhiyun }
482*4882a593Smuzhiyun const struct file_operations rknpu_fops = {
483*4882a593Smuzhiyun 	.owner = THIS_MODULE,
484*4882a593Smuzhiyun 	.open = rknpu_open,
485*4882a593Smuzhiyun 	.release = rknpu_release,
486*4882a593Smuzhiyun 	.unlocked_ioctl = rknpu_ioctl,
487*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
488*4882a593Smuzhiyun 	.compat_ioctl = rknpu_ioctl,
489*4882a593Smuzhiyun #endif
490*4882a593Smuzhiyun };
491*4882a593Smuzhiyun #endif
492*4882a593Smuzhiyun 
493*4882a593Smuzhiyun #ifdef CONFIG_ROCKCHIP_RKNPU_DRM_GEM
494*4882a593Smuzhiyun #if KERNEL_VERSION(6, 1, 0) > LINUX_VERSION_CODE
495*4882a593Smuzhiyun static const struct vm_operations_struct rknpu_gem_vm_ops = {
496*4882a593Smuzhiyun 	.fault = rknpu_gem_fault,
497*4882a593Smuzhiyun 	.open = drm_gem_vm_open,
498*4882a593Smuzhiyun 	.close = drm_gem_vm_close,
499*4882a593Smuzhiyun };
500*4882a593Smuzhiyun #endif
501*4882a593Smuzhiyun 
rknpu_action_ioctl(struct drm_device * dev,void * data,struct drm_file * file_priv)502*4882a593Smuzhiyun static int rknpu_action_ioctl(struct drm_device *dev, void *data,
503*4882a593Smuzhiyun 			      struct drm_file *file_priv)
504*4882a593Smuzhiyun {
505*4882a593Smuzhiyun 	struct rknpu_device *rknpu_dev = dev_get_drvdata(dev->dev);
506*4882a593Smuzhiyun 
507*4882a593Smuzhiyun 	return rknpu_action(rknpu_dev, (struct rknpu_action *)data);
508*4882a593Smuzhiyun }
509*4882a593Smuzhiyun 
510*4882a593Smuzhiyun #define RKNPU_IOCTL(func)                                                      \
511*4882a593Smuzhiyun 	static int __##func(struct drm_device *dev, void *data,                \
512*4882a593Smuzhiyun 			    struct drm_file *file_priv)                        \
513*4882a593Smuzhiyun 	{                                                                      \
514*4882a593Smuzhiyun 		struct rknpu_device *rknpu_dev = dev_get_drvdata(dev->dev);    \
515*4882a593Smuzhiyun 		int ret = -EINVAL;                                             \
516*4882a593Smuzhiyun 		rknpu_power_get(rknpu_dev);                                    \
517*4882a593Smuzhiyun 		ret = func(dev, data, file_priv);                              \
518*4882a593Smuzhiyun 		rknpu_power_put_delay(rknpu_dev);                              \
519*4882a593Smuzhiyun 		return ret;                                                    \
520*4882a593Smuzhiyun 	}
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun RKNPU_IOCTL(rknpu_action_ioctl);
523*4882a593Smuzhiyun RKNPU_IOCTL(rknpu_submit_ioctl);
524*4882a593Smuzhiyun RKNPU_IOCTL(rknpu_gem_create_ioctl);
525*4882a593Smuzhiyun RKNPU_IOCTL(rknpu_gem_map_ioctl);
526*4882a593Smuzhiyun RKNPU_IOCTL(rknpu_gem_destroy_ioctl);
527*4882a593Smuzhiyun RKNPU_IOCTL(rknpu_gem_sync_ioctl);
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun static const struct drm_ioctl_desc rknpu_ioctls[] = {
530*4882a593Smuzhiyun 	DRM_IOCTL_DEF_DRV(RKNPU_ACTION, __rknpu_action_ioctl, DRM_RENDER_ALLOW),
531*4882a593Smuzhiyun 	DRM_IOCTL_DEF_DRV(RKNPU_SUBMIT, __rknpu_submit_ioctl, DRM_RENDER_ALLOW),
532*4882a593Smuzhiyun 	DRM_IOCTL_DEF_DRV(RKNPU_MEM_CREATE, __rknpu_gem_create_ioctl,
533*4882a593Smuzhiyun 			  DRM_RENDER_ALLOW),
534*4882a593Smuzhiyun 	DRM_IOCTL_DEF_DRV(RKNPU_MEM_MAP, __rknpu_gem_map_ioctl,
535*4882a593Smuzhiyun 			  DRM_RENDER_ALLOW),
536*4882a593Smuzhiyun 	DRM_IOCTL_DEF_DRV(RKNPU_MEM_DESTROY, __rknpu_gem_destroy_ioctl,
537*4882a593Smuzhiyun 			  DRM_RENDER_ALLOW),
538*4882a593Smuzhiyun 	DRM_IOCTL_DEF_DRV(RKNPU_MEM_SYNC, __rknpu_gem_sync_ioctl,
539*4882a593Smuzhiyun 			  DRM_RENDER_ALLOW),
540*4882a593Smuzhiyun };
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun static const struct file_operations rknpu_drm_driver_fops = {
543*4882a593Smuzhiyun 	.owner = THIS_MODULE,
544*4882a593Smuzhiyun 	.open = drm_open,
545*4882a593Smuzhiyun 	.mmap = rknpu_gem_mmap,
546*4882a593Smuzhiyun 	.poll = drm_poll,
547*4882a593Smuzhiyun 	.read = drm_read,
548*4882a593Smuzhiyun 	.unlocked_ioctl = drm_ioctl,
549*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
550*4882a593Smuzhiyun 	.compat_ioctl = drm_compat_ioctl,
551*4882a593Smuzhiyun #endif
552*4882a593Smuzhiyun 	.release = drm_release,
553*4882a593Smuzhiyun 	.llseek = noop_llseek,
554*4882a593Smuzhiyun };
555*4882a593Smuzhiyun 
556*4882a593Smuzhiyun static struct drm_driver rknpu_drm_driver = {
557*4882a593Smuzhiyun #if KERNEL_VERSION(5, 4, 0) <= LINUX_VERSION_CODE
558*4882a593Smuzhiyun 	.driver_features = DRIVER_GEM | DRIVER_RENDER,
559*4882a593Smuzhiyun #else
560*4882a593Smuzhiyun 	.driver_features = DRIVER_GEM | DRIVER_PRIME | DRIVER_RENDER,
561*4882a593Smuzhiyun #endif
562*4882a593Smuzhiyun #if KERNEL_VERSION(6, 1, 0) > LINUX_VERSION_CODE
563*4882a593Smuzhiyun 	.gem_free_object_unlocked = rknpu_gem_free_object,
564*4882a593Smuzhiyun 	.gem_vm_ops = &rknpu_gem_vm_ops,
565*4882a593Smuzhiyun 	.dumb_destroy = drm_gem_dumb_destroy,
566*4882a593Smuzhiyun 	.gem_prime_export = drm_gem_prime_export,
567*4882a593Smuzhiyun 	.gem_prime_get_sg_table = rknpu_gem_prime_get_sg_table,
568*4882a593Smuzhiyun 	.gem_prime_vmap = rknpu_gem_prime_vmap,
569*4882a593Smuzhiyun 	.gem_prime_vunmap = rknpu_gem_prime_vunmap,
570*4882a593Smuzhiyun #endif
571*4882a593Smuzhiyun 	.dumb_create = rknpu_gem_dumb_create,
572*4882a593Smuzhiyun #if KERNEL_VERSION(4, 19, 0) > LINUX_VERSION_CODE
573*4882a593Smuzhiyun 	.dumb_map_offset = rknpu_gem_dumb_map_offset,
574*4882a593Smuzhiyun #else
575*4882a593Smuzhiyun 	.dumb_map_offset = drm_gem_dumb_map_offset,
576*4882a593Smuzhiyun #endif
577*4882a593Smuzhiyun 	.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
578*4882a593Smuzhiyun 	.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
579*4882a593Smuzhiyun #if KERNEL_VERSION(4, 13, 0) <= LINUX_VERSION_CODE
580*4882a593Smuzhiyun 	.gem_prime_import = rknpu_gem_prime_import,
581*4882a593Smuzhiyun #else
582*4882a593Smuzhiyun 	.gem_prime_import = drm_gem_prime_import,
583*4882a593Smuzhiyun #endif
584*4882a593Smuzhiyun 	.gem_prime_import_sg_table = rknpu_gem_prime_import_sg_table,
585*4882a593Smuzhiyun 	.gem_prime_mmap = rknpu_gem_prime_mmap,
586*4882a593Smuzhiyun 	.ioctls = rknpu_ioctls,
587*4882a593Smuzhiyun 	.num_ioctls = ARRAY_SIZE(rknpu_ioctls),
588*4882a593Smuzhiyun 	.fops = &rknpu_drm_driver_fops,
589*4882a593Smuzhiyun 	.name = DRIVER_NAME,
590*4882a593Smuzhiyun 	.desc = DRIVER_DESC,
591*4882a593Smuzhiyun 	.date = DRIVER_DATE,
592*4882a593Smuzhiyun 	.major = DRIVER_MAJOR,
593*4882a593Smuzhiyun 	.minor = DRIVER_MINOR,
594*4882a593Smuzhiyun 	.patchlevel = DRIVER_PATCHLEVEL,
595*4882a593Smuzhiyun };
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun #endif
598*4882a593Smuzhiyun 
hrtimer_handler(struct hrtimer * timer)599*4882a593Smuzhiyun static enum hrtimer_restart hrtimer_handler(struct hrtimer *timer)
600*4882a593Smuzhiyun {
601*4882a593Smuzhiyun 	struct rknpu_device *rknpu_dev =
602*4882a593Smuzhiyun 		container_of(timer, struct rknpu_device, timer);
603*4882a593Smuzhiyun 	struct rknpu_subcore_data *subcore_data = NULL;
604*4882a593Smuzhiyun 	struct rknpu_job *job = NULL;
605*4882a593Smuzhiyun 	ktime_t now = ktime_get();
606*4882a593Smuzhiyun 	unsigned long flags;
607*4882a593Smuzhiyun 	int i;
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	for (i = 0; i < rknpu_dev->config->num_irqs; i++) {
610*4882a593Smuzhiyun 		subcore_data = &rknpu_dev->subcore_datas[i];
611*4882a593Smuzhiyun 
612*4882a593Smuzhiyun 		spin_lock_irqsave(&rknpu_dev->irq_lock, flags);
613*4882a593Smuzhiyun 
614*4882a593Smuzhiyun 		job = subcore_data->job;
615*4882a593Smuzhiyun 		if (job) {
616*4882a593Smuzhiyun 			subcore_data->timer.busy_time +=
617*4882a593Smuzhiyun 				ktime_us_delta(now, job->hw_recoder_time);
618*4882a593Smuzhiyun 			job->hw_recoder_time = ktime_get();
619*4882a593Smuzhiyun 		}
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 		subcore_data->timer.busy_time_record =
622*4882a593Smuzhiyun 			subcore_data->timer.busy_time;
623*4882a593Smuzhiyun 		subcore_data->timer.busy_time = 0;
624*4882a593Smuzhiyun 		spin_unlock_irqrestore(&rknpu_dev->irq_lock, flags);
625*4882a593Smuzhiyun 	}
626*4882a593Smuzhiyun 
627*4882a593Smuzhiyun 	hrtimer_forward_now(timer, rknpu_dev->kt);
628*4882a593Smuzhiyun 	return HRTIMER_RESTART;
629*4882a593Smuzhiyun }
630*4882a593Smuzhiyun 
rknpu_init_timer(struct rknpu_device * rknpu_dev)631*4882a593Smuzhiyun static void rknpu_init_timer(struct rknpu_device *rknpu_dev)
632*4882a593Smuzhiyun {
633*4882a593Smuzhiyun 	rknpu_dev->kt = ktime_set(0, RKNPU_LOAD_INTERVAL);
634*4882a593Smuzhiyun 	hrtimer_init(&rknpu_dev->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
635*4882a593Smuzhiyun 	rknpu_dev->timer.function = hrtimer_handler;
636*4882a593Smuzhiyun 	hrtimer_start(&rknpu_dev->timer, rknpu_dev->kt, HRTIMER_MODE_REL);
637*4882a593Smuzhiyun }
638*4882a593Smuzhiyun 
rknpu_cancel_timer(struct rknpu_device * rknpu_dev)639*4882a593Smuzhiyun static void rknpu_cancel_timer(struct rknpu_device *rknpu_dev)
640*4882a593Smuzhiyun {
641*4882a593Smuzhiyun 	hrtimer_cancel(&rknpu_dev->timer);
642*4882a593Smuzhiyun }
643*4882a593Smuzhiyun 
rknpu_is_iommu_enable(struct device * dev)644*4882a593Smuzhiyun static bool rknpu_is_iommu_enable(struct device *dev)
645*4882a593Smuzhiyun {
646*4882a593Smuzhiyun 	struct device_node *iommu = NULL;
647*4882a593Smuzhiyun 
648*4882a593Smuzhiyun 	iommu = of_parse_phandle(dev->of_node, "iommus", 0);
649*4882a593Smuzhiyun 	if (!iommu) {
650*4882a593Smuzhiyun 		LOG_DEV_INFO(
651*4882a593Smuzhiyun 			dev,
652*4882a593Smuzhiyun 			"rknpu iommu device-tree entry not found!, using non-iommu mode\n");
653*4882a593Smuzhiyun 		return false;
654*4882a593Smuzhiyun 	}
655*4882a593Smuzhiyun 
656*4882a593Smuzhiyun 	if (!of_device_is_available(iommu)) {
657*4882a593Smuzhiyun 		LOG_DEV_INFO(dev,
658*4882a593Smuzhiyun 			     "rknpu iommu is disabled, using non-iommu mode\n");
659*4882a593Smuzhiyun 		of_node_put(iommu);
660*4882a593Smuzhiyun 		return false;
661*4882a593Smuzhiyun 	}
662*4882a593Smuzhiyun 	of_node_put(iommu);
663*4882a593Smuzhiyun 
664*4882a593Smuzhiyun 	LOG_DEV_INFO(dev, "rknpu iommu is enabled, using iommu mode\n");
665*4882a593Smuzhiyun 
666*4882a593Smuzhiyun 	return true;
667*4882a593Smuzhiyun }
668*4882a593Smuzhiyun 
669*4882a593Smuzhiyun #ifdef CONFIG_ROCKCHIP_RKNPU_DRM_GEM
rknpu_drm_probe(struct rknpu_device * rknpu_dev)670*4882a593Smuzhiyun static int rknpu_drm_probe(struct rknpu_device *rknpu_dev)
671*4882a593Smuzhiyun {
672*4882a593Smuzhiyun 	struct device *dev = rknpu_dev->dev;
673*4882a593Smuzhiyun 	struct drm_device *drm_dev = NULL;
674*4882a593Smuzhiyun 	int ret = -EINVAL;
675*4882a593Smuzhiyun 
676*4882a593Smuzhiyun 	drm_dev = drm_dev_alloc(&rknpu_drm_driver, dev);
677*4882a593Smuzhiyun 	if (IS_ERR(drm_dev))
678*4882a593Smuzhiyun 		return PTR_ERR(drm_dev);
679*4882a593Smuzhiyun 
680*4882a593Smuzhiyun 	/* register the DRM device */
681*4882a593Smuzhiyun 	ret = drm_dev_register(drm_dev, 0);
682*4882a593Smuzhiyun 	if (ret < 0)
683*4882a593Smuzhiyun 		goto err_free_drm;
684*4882a593Smuzhiyun 
685*4882a593Smuzhiyun 	drm_dev->dev_private = rknpu_dev;
686*4882a593Smuzhiyun 	rknpu_dev->drm_dev = drm_dev;
687*4882a593Smuzhiyun 
688*4882a593Smuzhiyun 	return 0;
689*4882a593Smuzhiyun 
690*4882a593Smuzhiyun err_free_drm:
691*4882a593Smuzhiyun #if KERNEL_VERSION(4, 15, 0) <= LINUX_VERSION_CODE
692*4882a593Smuzhiyun 	drm_dev_put(drm_dev);
693*4882a593Smuzhiyun #else
694*4882a593Smuzhiyun 	drm_dev_unref(drm_dev);
695*4882a593Smuzhiyun #endif
696*4882a593Smuzhiyun 
697*4882a593Smuzhiyun 	return ret;
698*4882a593Smuzhiyun }
699*4882a593Smuzhiyun 
rknpu_drm_remove(struct rknpu_device * rknpu_dev)700*4882a593Smuzhiyun static void rknpu_drm_remove(struct rknpu_device *rknpu_dev)
701*4882a593Smuzhiyun {
702*4882a593Smuzhiyun 	struct drm_device *drm_dev = rknpu_dev->drm_dev;
703*4882a593Smuzhiyun 
704*4882a593Smuzhiyun 	drm_dev_unregister(drm_dev);
705*4882a593Smuzhiyun 
706*4882a593Smuzhiyun #if KERNEL_VERSION(4, 15, 0) <= LINUX_VERSION_CODE
707*4882a593Smuzhiyun 	drm_dev_put(drm_dev);
708*4882a593Smuzhiyun #else
709*4882a593Smuzhiyun 	drm_dev_unref(drm_dev);
710*4882a593Smuzhiyun #endif
711*4882a593Smuzhiyun }
712*4882a593Smuzhiyun #endif
713*4882a593Smuzhiyun 
rknpu_power_on(struct rknpu_device * rknpu_dev)714*4882a593Smuzhiyun static int rknpu_power_on(struct rknpu_device *rknpu_dev)
715*4882a593Smuzhiyun {
716*4882a593Smuzhiyun 	struct device *dev = rknpu_dev->dev;
717*4882a593Smuzhiyun 	int ret = -EINVAL;
718*4882a593Smuzhiyun 
719*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
720*4882a593Smuzhiyun 	if (rknpu_dev->vdd) {
721*4882a593Smuzhiyun 		ret = regulator_enable(rknpu_dev->vdd);
722*4882a593Smuzhiyun 		if (ret) {
723*4882a593Smuzhiyun 			LOG_DEV_ERROR(
724*4882a593Smuzhiyun 				dev,
725*4882a593Smuzhiyun 				"failed to enable vdd reg for rknpu, ret: %d\n",
726*4882a593Smuzhiyun 				ret);
727*4882a593Smuzhiyun 			return ret;
728*4882a593Smuzhiyun 		}
729*4882a593Smuzhiyun 	}
730*4882a593Smuzhiyun 
731*4882a593Smuzhiyun 	if (rknpu_dev->mem) {
732*4882a593Smuzhiyun 		ret = regulator_enable(rknpu_dev->mem);
733*4882a593Smuzhiyun 		if (ret) {
734*4882a593Smuzhiyun 			LOG_DEV_ERROR(
735*4882a593Smuzhiyun 				dev,
736*4882a593Smuzhiyun 				"failed to enable mem reg for rknpu, ret: %d\n",
737*4882a593Smuzhiyun 				ret);
738*4882a593Smuzhiyun 			return ret;
739*4882a593Smuzhiyun 		}
740*4882a593Smuzhiyun 	}
741*4882a593Smuzhiyun #endif
742*4882a593Smuzhiyun 
743*4882a593Smuzhiyun 	ret = clk_bulk_prepare_enable(rknpu_dev->num_clks, rknpu_dev->clks);
744*4882a593Smuzhiyun 	if (ret) {
745*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to enable clk for rknpu, ret: %d\n",
746*4882a593Smuzhiyun 			      ret);
747*4882a593Smuzhiyun 		return ret;
748*4882a593Smuzhiyun 	}
749*4882a593Smuzhiyun 
750*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
751*4882a593Smuzhiyun #if KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE &&                          \
752*4882a593Smuzhiyun 	KERNEL_VERSION(6, 1, 0) > LINUX_VERSION_CODE
753*4882a593Smuzhiyun 	rockchip_monitor_volt_adjust_lock(rknpu_dev->mdev_info);
754*4882a593Smuzhiyun #endif
755*4882a593Smuzhiyun #endif
756*4882a593Smuzhiyun 
757*4882a593Smuzhiyun 	if (rknpu_dev->multiple_domains) {
758*4882a593Smuzhiyun 		if (rknpu_dev->genpd_dev_npu0) {
759*4882a593Smuzhiyun #if KERNEL_VERSION(5, 5, 0) < LINUX_VERSION_CODE
760*4882a593Smuzhiyun 			ret = pm_runtime_resume_and_get(
761*4882a593Smuzhiyun 				rknpu_dev->genpd_dev_npu0);
762*4882a593Smuzhiyun #else
763*4882a593Smuzhiyun 			ret = pm_runtime_get_sync(rknpu_dev->genpd_dev_npu0);
764*4882a593Smuzhiyun #endif
765*4882a593Smuzhiyun 			if (ret < 0) {
766*4882a593Smuzhiyun 				LOG_DEV_ERROR(
767*4882a593Smuzhiyun 					dev,
768*4882a593Smuzhiyun 					"failed to get pm runtime for npu0, ret: %d\n",
769*4882a593Smuzhiyun 					ret);
770*4882a593Smuzhiyun 				goto out;
771*4882a593Smuzhiyun 			}
772*4882a593Smuzhiyun 		}
773*4882a593Smuzhiyun 		if (rknpu_dev->genpd_dev_npu1) {
774*4882a593Smuzhiyun #if KERNEL_VERSION(5, 5, 0) < LINUX_VERSION_CODE
775*4882a593Smuzhiyun 			ret = pm_runtime_resume_and_get(
776*4882a593Smuzhiyun 				rknpu_dev->genpd_dev_npu1);
777*4882a593Smuzhiyun #else
778*4882a593Smuzhiyun 			ret = pm_runtime_get_sync(rknpu_dev->genpd_dev_npu1);
779*4882a593Smuzhiyun #endif
780*4882a593Smuzhiyun 			if (ret < 0) {
781*4882a593Smuzhiyun 				LOG_DEV_ERROR(
782*4882a593Smuzhiyun 					dev,
783*4882a593Smuzhiyun 					"failed to get pm runtime for npu1, ret: %d\n",
784*4882a593Smuzhiyun 					ret);
785*4882a593Smuzhiyun 				goto out;
786*4882a593Smuzhiyun 			}
787*4882a593Smuzhiyun 		}
788*4882a593Smuzhiyun 		if (rknpu_dev->genpd_dev_npu2) {
789*4882a593Smuzhiyun #if KERNEL_VERSION(5, 5, 0) < LINUX_VERSION_CODE
790*4882a593Smuzhiyun 			ret = pm_runtime_resume_and_get(
791*4882a593Smuzhiyun 				rknpu_dev->genpd_dev_npu2);
792*4882a593Smuzhiyun #else
793*4882a593Smuzhiyun 			ret = pm_runtime_get_sync(rknpu_dev->genpd_dev_npu2);
794*4882a593Smuzhiyun #endif
795*4882a593Smuzhiyun 			if (ret < 0) {
796*4882a593Smuzhiyun 				LOG_DEV_ERROR(
797*4882a593Smuzhiyun 					dev,
798*4882a593Smuzhiyun 					"failed to get pm runtime for npu2, ret: %d\n",
799*4882a593Smuzhiyun 					ret);
800*4882a593Smuzhiyun 				goto out;
801*4882a593Smuzhiyun 			}
802*4882a593Smuzhiyun 		}
803*4882a593Smuzhiyun 	}
804*4882a593Smuzhiyun 	ret = pm_runtime_get_sync(dev);
805*4882a593Smuzhiyun 	if (ret < 0) {
806*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev,
807*4882a593Smuzhiyun 			      "failed to get pm runtime for rknpu, ret: %d\n",
808*4882a593Smuzhiyun 			      ret);
809*4882a593Smuzhiyun 	}
810*4882a593Smuzhiyun 
811*4882a593Smuzhiyun out:
812*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
813*4882a593Smuzhiyun #if KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE &&                          \
814*4882a593Smuzhiyun 	KERNEL_VERSION(6, 1, 0) > LINUX_VERSION_CODE
815*4882a593Smuzhiyun 	rockchip_monitor_volt_adjust_unlock(rknpu_dev->mdev_info);
816*4882a593Smuzhiyun #endif
817*4882a593Smuzhiyun #endif
818*4882a593Smuzhiyun 
819*4882a593Smuzhiyun 	return ret;
820*4882a593Smuzhiyun }
821*4882a593Smuzhiyun 
rknpu_power_off(struct rknpu_device * rknpu_dev)822*4882a593Smuzhiyun static int rknpu_power_off(struct rknpu_device *rknpu_dev)
823*4882a593Smuzhiyun {
824*4882a593Smuzhiyun 	struct device *dev = rknpu_dev->dev;
825*4882a593Smuzhiyun 
826*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
827*4882a593Smuzhiyun 	int ret;
828*4882a593Smuzhiyun 	bool val;
829*4882a593Smuzhiyun 
830*4882a593Smuzhiyun #if KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE &&                          \
831*4882a593Smuzhiyun 	KERNEL_VERSION(6, 1, 0) > LINUX_VERSION_CODE
832*4882a593Smuzhiyun 	rockchip_monitor_volt_adjust_lock(rknpu_dev->mdev_info);
833*4882a593Smuzhiyun #endif
834*4882a593Smuzhiyun #endif
835*4882a593Smuzhiyun 
836*4882a593Smuzhiyun 	pm_runtime_put_sync(dev);
837*4882a593Smuzhiyun 
838*4882a593Smuzhiyun 	if (rknpu_dev->multiple_domains) {
839*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
840*4882a593Smuzhiyun 		/*
841*4882a593Smuzhiyun 		 * Because IOMMU's runtime suspend callback is asynchronous,
842*4882a593Smuzhiyun 		 * So it may be executed after the NPU is turned off after PD/CLK/VD,
843*4882a593Smuzhiyun 		 * and the runtime suspend callback has a register access.
844*4882a593Smuzhiyun 		 * If the PD/VD/CLK is closed, the register access will crash.
845*4882a593Smuzhiyun 		 * As a workaround, it's safe to close pd stuff until iommu disabled.
846*4882a593Smuzhiyun 		 * If pm runtime framework can handle this issue in the future, remove
847*4882a593Smuzhiyun 		 * this.
848*4882a593Smuzhiyun 		 */
849*4882a593Smuzhiyun 		ret = readx_poll_timeout(rockchip_iommu_is_enabled, dev, val,
850*4882a593Smuzhiyun 					 !val, NPU_MMU_DISABLED_POLL_PERIOD_US,
851*4882a593Smuzhiyun 					 NPU_MMU_DISABLED_POLL_TIMEOUT_US);
852*4882a593Smuzhiyun 		if (ret) {
853*4882a593Smuzhiyun 			LOG_DEV_ERROR(dev, "iommu still enabled\n");
854*4882a593Smuzhiyun 			pm_runtime_get_sync(dev);
855*4882a593Smuzhiyun #if KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE &&                          \
856*4882a593Smuzhiyun 	KERNEL_VERSION(6, 1, 0) > LINUX_VERSION_CODE
857*4882a593Smuzhiyun 			rockchip_monitor_volt_adjust_unlock(
858*4882a593Smuzhiyun 				rknpu_dev->mdev_info);
859*4882a593Smuzhiyun #endif
860*4882a593Smuzhiyun 			return ret;
861*4882a593Smuzhiyun 		}
862*4882a593Smuzhiyun #else
863*4882a593Smuzhiyun 		if (rknpu_dev->iommu_en)
864*4882a593Smuzhiyun 			msleep(20);
865*4882a593Smuzhiyun #endif
866*4882a593Smuzhiyun 		if (rknpu_dev->genpd_dev_npu2)
867*4882a593Smuzhiyun 			pm_runtime_put_sync(rknpu_dev->genpd_dev_npu2);
868*4882a593Smuzhiyun 		if (rknpu_dev->genpd_dev_npu1)
869*4882a593Smuzhiyun 			pm_runtime_put_sync(rknpu_dev->genpd_dev_npu1);
870*4882a593Smuzhiyun 		if (rknpu_dev->genpd_dev_npu0)
871*4882a593Smuzhiyun 			pm_runtime_put_sync(rknpu_dev->genpd_dev_npu0);
872*4882a593Smuzhiyun 	}
873*4882a593Smuzhiyun 
874*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
875*4882a593Smuzhiyun #if KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE &&                          \
876*4882a593Smuzhiyun 	KERNEL_VERSION(6, 1, 0) > LINUX_VERSION_CODE
877*4882a593Smuzhiyun 	rockchip_monitor_volt_adjust_unlock(rknpu_dev->mdev_info);
878*4882a593Smuzhiyun #endif
879*4882a593Smuzhiyun #endif
880*4882a593Smuzhiyun 
881*4882a593Smuzhiyun 	clk_bulk_disable_unprepare(rknpu_dev->num_clks, rknpu_dev->clks);
882*4882a593Smuzhiyun 
883*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
884*4882a593Smuzhiyun 	if (rknpu_dev->vdd)
885*4882a593Smuzhiyun 		regulator_disable(rknpu_dev->vdd);
886*4882a593Smuzhiyun 
887*4882a593Smuzhiyun 	if (rknpu_dev->mem)
888*4882a593Smuzhiyun 		regulator_disable(rknpu_dev->mem);
889*4882a593Smuzhiyun #endif
890*4882a593Smuzhiyun 
891*4882a593Smuzhiyun 	return 0;
892*4882a593Smuzhiyun }
893*4882a593Smuzhiyun 
894*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
895*4882a593Smuzhiyun #if KERNEL_VERSION(6, 1, 0) > LINUX_VERSION_CODE
896*4882a593Smuzhiyun static struct monitor_dev_profile npu_mdevp = {
897*4882a593Smuzhiyun 	.type = MONITOR_TYPE_DEV,
898*4882a593Smuzhiyun 	.low_temp_adjust = rockchip_monitor_dev_low_temp_adjust,
899*4882a593Smuzhiyun 	.high_temp_adjust = rockchip_monitor_dev_high_temp_adjust,
900*4882a593Smuzhiyun #if KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE
901*4882a593Smuzhiyun 	.update_volt = rockchip_monitor_check_rate_volt,
902*4882a593Smuzhiyun #endif
903*4882a593Smuzhiyun };
904*4882a593Smuzhiyun 
905*4882a593Smuzhiyun #if KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE
npu_opp_helper(struct dev_pm_set_opp_data * data)906*4882a593Smuzhiyun static int npu_opp_helper(struct dev_pm_set_opp_data *data)
907*4882a593Smuzhiyun {
908*4882a593Smuzhiyun 	struct device *dev = data->dev;
909*4882a593Smuzhiyun 	struct dev_pm_opp_supply *old_supply_vdd = &data->old_opp.supplies[0];
910*4882a593Smuzhiyun 	struct dev_pm_opp_supply *old_supply_mem = &data->old_opp.supplies[1];
911*4882a593Smuzhiyun 	struct dev_pm_opp_supply *new_supply_vdd = &data->new_opp.supplies[0];
912*4882a593Smuzhiyun 	struct dev_pm_opp_supply *new_supply_mem = &data->new_opp.supplies[1];
913*4882a593Smuzhiyun 	struct regulator *vdd_reg = data->regulators[0];
914*4882a593Smuzhiyun 	struct regulator *mem_reg = data->regulators[1];
915*4882a593Smuzhiyun 	struct clk *clk = data->clk;
916*4882a593Smuzhiyun 	struct rknpu_device *rknpu_dev = dev_get_drvdata(dev);
917*4882a593Smuzhiyun 	struct rockchip_opp_info *opp_info = &rknpu_dev->opp_info;
918*4882a593Smuzhiyun 	unsigned long old_freq = data->old_opp.rate;
919*4882a593Smuzhiyun 	unsigned long new_freq = data->new_opp.rate;
920*4882a593Smuzhiyun 	bool is_set_rm = true;
921*4882a593Smuzhiyun 	bool is_set_clk = true;
922*4882a593Smuzhiyun 	u32 target_rm = UINT_MAX;
923*4882a593Smuzhiyun 	int ret = 0;
924*4882a593Smuzhiyun 
925*4882a593Smuzhiyun 	if (!pm_runtime_active(dev)) {
926*4882a593Smuzhiyun 		is_set_rm = false;
927*4882a593Smuzhiyun 		if (opp_info->scmi_clk)
928*4882a593Smuzhiyun 			is_set_clk = false;
929*4882a593Smuzhiyun 	}
930*4882a593Smuzhiyun 
931*4882a593Smuzhiyun 	ret = clk_bulk_prepare_enable(opp_info->num_clks, opp_info->clks);
932*4882a593Smuzhiyun 	if (ret < 0) {
933*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to enable opp clks\n");
934*4882a593Smuzhiyun 		return ret;
935*4882a593Smuzhiyun 	}
936*4882a593Smuzhiyun 	rockchip_get_read_margin(dev, opp_info, new_supply_vdd->u_volt,
937*4882a593Smuzhiyun 				 &target_rm);
938*4882a593Smuzhiyun 
939*4882a593Smuzhiyun 	/* Change frequency */
940*4882a593Smuzhiyun 	LOG_DEV_DEBUG(dev, "switching OPP: %lu Hz --> %lu Hz\n", old_freq,
941*4882a593Smuzhiyun 		      new_freq);
942*4882a593Smuzhiyun 	/* Scaling up? Scale voltage before frequency */
943*4882a593Smuzhiyun 	if (new_freq >= old_freq) {
944*4882a593Smuzhiyun 		rockchip_set_intermediate_rate(dev, opp_info, clk, old_freq,
945*4882a593Smuzhiyun 					       new_freq, true, is_set_clk);
946*4882a593Smuzhiyun 		ret = regulator_set_voltage(mem_reg, new_supply_mem->u_volt,
947*4882a593Smuzhiyun 					    INT_MAX);
948*4882a593Smuzhiyun 		if (ret) {
949*4882a593Smuzhiyun 			LOG_DEV_ERROR(dev,
950*4882a593Smuzhiyun 				      "failed to set volt %lu uV for mem reg\n",
951*4882a593Smuzhiyun 				      new_supply_mem->u_volt);
952*4882a593Smuzhiyun 			goto restore_voltage;
953*4882a593Smuzhiyun 		}
954*4882a593Smuzhiyun 		ret = regulator_set_voltage(vdd_reg, new_supply_vdd->u_volt,
955*4882a593Smuzhiyun 					    INT_MAX);
956*4882a593Smuzhiyun 		if (ret) {
957*4882a593Smuzhiyun 			LOG_DEV_ERROR(dev,
958*4882a593Smuzhiyun 				      "failed to set volt %lu uV for vdd reg\n",
959*4882a593Smuzhiyun 				      new_supply_vdd->u_volt);
960*4882a593Smuzhiyun 			goto restore_voltage;
961*4882a593Smuzhiyun 		}
962*4882a593Smuzhiyun 		rockchip_set_read_margin(dev, opp_info, target_rm, is_set_rm);
963*4882a593Smuzhiyun 		if (is_set_clk && clk_set_rate(clk, new_freq)) {
964*4882a593Smuzhiyun 			ret = -EINVAL;
965*4882a593Smuzhiyun 			LOG_DEV_ERROR(dev, "failed to set clk rate: %d\n", ret);
966*4882a593Smuzhiyun 			goto restore_rm;
967*4882a593Smuzhiyun 		}
968*4882a593Smuzhiyun 		/* Scaling down? Scale voltage after frequency */
969*4882a593Smuzhiyun 	} else {
970*4882a593Smuzhiyun 		rockchip_set_intermediate_rate(dev, opp_info, clk, old_freq,
971*4882a593Smuzhiyun 					       new_freq, false, is_set_clk);
972*4882a593Smuzhiyun 		rockchip_set_read_margin(dev, opp_info, target_rm, is_set_rm);
973*4882a593Smuzhiyun 		if (is_set_clk && clk_set_rate(clk, new_freq)) {
974*4882a593Smuzhiyun 			ret = -EINVAL;
975*4882a593Smuzhiyun 			LOG_DEV_ERROR(dev, "failed to set clk rate: %d\n", ret);
976*4882a593Smuzhiyun 			goto restore_rm;
977*4882a593Smuzhiyun 		}
978*4882a593Smuzhiyun 		ret = regulator_set_voltage(vdd_reg, new_supply_vdd->u_volt,
979*4882a593Smuzhiyun 					    INT_MAX);
980*4882a593Smuzhiyun 		if (ret) {
981*4882a593Smuzhiyun 			LOG_DEV_ERROR(dev,
982*4882a593Smuzhiyun 				      "failed to set volt %lu uV for vdd reg\n",
983*4882a593Smuzhiyun 				      new_supply_vdd->u_volt);
984*4882a593Smuzhiyun 			goto restore_freq;
985*4882a593Smuzhiyun 		}
986*4882a593Smuzhiyun 		ret = regulator_set_voltage(mem_reg, new_supply_mem->u_volt,
987*4882a593Smuzhiyun 					    INT_MAX);
988*4882a593Smuzhiyun 		if (ret) {
989*4882a593Smuzhiyun 			LOG_DEV_ERROR(dev,
990*4882a593Smuzhiyun 				      "failed to set volt %lu uV for mem reg\n",
991*4882a593Smuzhiyun 				      new_supply_mem->u_volt);
992*4882a593Smuzhiyun 			goto restore_freq;
993*4882a593Smuzhiyun 		}
994*4882a593Smuzhiyun 	}
995*4882a593Smuzhiyun 
996*4882a593Smuzhiyun 	clk_bulk_disable_unprepare(opp_info->num_clks, opp_info->clks);
997*4882a593Smuzhiyun 
998*4882a593Smuzhiyun 	return 0;
999*4882a593Smuzhiyun 
1000*4882a593Smuzhiyun restore_freq:
1001*4882a593Smuzhiyun 	if (is_set_clk && clk_set_rate(clk, old_freq))
1002*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to restore old-freq %lu Hz\n",
1003*4882a593Smuzhiyun 			      old_freq);
1004*4882a593Smuzhiyun restore_rm:
1005*4882a593Smuzhiyun 	rockchip_get_read_margin(dev, opp_info, old_supply_vdd->u_volt,
1006*4882a593Smuzhiyun 				 &target_rm);
1007*4882a593Smuzhiyun 	rockchip_set_read_margin(dev, opp_info, opp_info->current_rm,
1008*4882a593Smuzhiyun 				 is_set_rm);
1009*4882a593Smuzhiyun restore_voltage:
1010*4882a593Smuzhiyun 	regulator_set_voltage(mem_reg, old_supply_mem->u_volt, INT_MAX);
1011*4882a593Smuzhiyun 	regulator_set_voltage(vdd_reg, old_supply_vdd->u_volt, INT_MAX);
1012*4882a593Smuzhiyun 	clk_bulk_disable_unprepare(opp_info->num_clks, opp_info->clks);
1013*4882a593Smuzhiyun 
1014*4882a593Smuzhiyun 	return ret;
1015*4882a593Smuzhiyun }
1016*4882a593Smuzhiyun 
npu_devfreq_target(struct device * dev,unsigned long * freq,u32 flags)1017*4882a593Smuzhiyun static int npu_devfreq_target(struct device *dev, unsigned long *freq,
1018*4882a593Smuzhiyun 			      u32 flags)
1019*4882a593Smuzhiyun {
1020*4882a593Smuzhiyun 	struct rknpu_device *rknpu_dev = dev_get_drvdata(dev);
1021*4882a593Smuzhiyun 	struct dev_pm_opp *opp;
1022*4882a593Smuzhiyun 	unsigned long opp_volt;
1023*4882a593Smuzhiyun 	int ret = 0;
1024*4882a593Smuzhiyun 
1025*4882a593Smuzhiyun 	if (!npu_mdevp.is_checked)
1026*4882a593Smuzhiyun 		return -EINVAL;
1027*4882a593Smuzhiyun 
1028*4882a593Smuzhiyun 	opp = devfreq_recommended_opp(dev, freq, flags);
1029*4882a593Smuzhiyun 	if (IS_ERR(opp))
1030*4882a593Smuzhiyun 		return PTR_ERR(opp);
1031*4882a593Smuzhiyun 	opp_volt = dev_pm_opp_get_voltage(opp);
1032*4882a593Smuzhiyun 	dev_pm_opp_put(opp);
1033*4882a593Smuzhiyun 
1034*4882a593Smuzhiyun #if KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE
1035*4882a593Smuzhiyun 	rockchip_monitor_volt_adjust_lock(rknpu_dev->mdev_info);
1036*4882a593Smuzhiyun #endif
1037*4882a593Smuzhiyun 	ret = dev_pm_opp_set_rate(dev, *freq);
1038*4882a593Smuzhiyun 	if (!ret) {
1039*4882a593Smuzhiyun 		rknpu_dev->current_freq = *freq;
1040*4882a593Smuzhiyun 		if (rknpu_dev->devfreq)
1041*4882a593Smuzhiyun 			rknpu_dev->devfreq->last_status.current_frequency =
1042*4882a593Smuzhiyun 				*freq;
1043*4882a593Smuzhiyun 		rknpu_dev->current_volt = opp_volt;
1044*4882a593Smuzhiyun 		LOG_DEV_INFO(dev, "set rknpu freq: %lu, volt: %lu\n",
1045*4882a593Smuzhiyun 			     rknpu_dev->current_freq, rknpu_dev->current_volt);
1046*4882a593Smuzhiyun 	}
1047*4882a593Smuzhiyun #if KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE
1048*4882a593Smuzhiyun 	rockchip_monitor_volt_adjust_unlock(rknpu_dev->mdev_info);
1049*4882a593Smuzhiyun #endif
1050*4882a593Smuzhiyun 
1051*4882a593Smuzhiyun 	return ret;
1052*4882a593Smuzhiyun }
1053*4882a593Smuzhiyun 
1054*4882a593Smuzhiyun #else
1055*4882a593Smuzhiyun 
npu_devfreq_target(struct device * dev,unsigned long * target_freq,u32 flags)1056*4882a593Smuzhiyun static int npu_devfreq_target(struct device *dev, unsigned long *target_freq,
1057*4882a593Smuzhiyun 			      u32 flags)
1058*4882a593Smuzhiyun {
1059*4882a593Smuzhiyun 	struct rknpu_device *rknpu_dev = dev_get_drvdata(dev);
1060*4882a593Smuzhiyun 	struct dev_pm_opp *opp = NULL;
1061*4882a593Smuzhiyun 	unsigned long freq = *target_freq;
1062*4882a593Smuzhiyun 	unsigned long old_freq = rknpu_dev->current_freq;
1063*4882a593Smuzhiyun 	unsigned long volt, old_volt = rknpu_dev->current_volt;
1064*4882a593Smuzhiyun 	int ret = -EINVAL;
1065*4882a593Smuzhiyun 
1066*4882a593Smuzhiyun #if KERNEL_VERSION(4, 11, 0) > LINUX_VERSION_CODE
1067*4882a593Smuzhiyun 	rcu_read_lock();
1068*4882a593Smuzhiyun #endif
1069*4882a593Smuzhiyun 
1070*4882a593Smuzhiyun 	opp = devfreq_recommended_opp(dev, &freq, flags);
1071*4882a593Smuzhiyun 	if (IS_ERR(opp)) {
1072*4882a593Smuzhiyun #if KERNEL_VERSION(4, 11, 0) > LINUX_VERSION_CODE
1073*4882a593Smuzhiyun 		rcu_read_unlock();
1074*4882a593Smuzhiyun #endif
1075*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to get opp (%ld)\n", PTR_ERR(opp));
1076*4882a593Smuzhiyun 		return PTR_ERR(opp);
1077*4882a593Smuzhiyun 	}
1078*4882a593Smuzhiyun 	volt = dev_pm_opp_get_voltage(opp);
1079*4882a593Smuzhiyun #if KERNEL_VERSION(4, 11, 0) > LINUX_VERSION_CODE
1080*4882a593Smuzhiyun 	rcu_read_unlock();
1081*4882a593Smuzhiyun #endif
1082*4882a593Smuzhiyun 
1083*4882a593Smuzhiyun 	/*
1084*4882a593Smuzhiyun 	 * Only update if there is a change of frequency
1085*4882a593Smuzhiyun 	 */
1086*4882a593Smuzhiyun 	if (old_freq == freq) {
1087*4882a593Smuzhiyun 		*target_freq = freq;
1088*4882a593Smuzhiyun 		if (old_volt == volt)
1089*4882a593Smuzhiyun 			return 0;
1090*4882a593Smuzhiyun 		ret = regulator_set_voltage(rknpu_dev->vdd, volt, INT_MAX);
1091*4882a593Smuzhiyun 		if (ret) {
1092*4882a593Smuzhiyun 			LOG_DEV_ERROR(dev, "failed to set volt %lu\n", volt);
1093*4882a593Smuzhiyun 			return ret;
1094*4882a593Smuzhiyun 		}
1095*4882a593Smuzhiyun 		rknpu_dev->current_volt = volt;
1096*4882a593Smuzhiyun 		return 0;
1097*4882a593Smuzhiyun 	}
1098*4882a593Smuzhiyun 
1099*4882a593Smuzhiyun 	if (rknpu_dev->vdd && old_volt != volt && old_freq < freq) {
1100*4882a593Smuzhiyun 		ret = regulator_set_voltage(rknpu_dev->vdd, volt, INT_MAX);
1101*4882a593Smuzhiyun 		if (ret) {
1102*4882a593Smuzhiyun 			LOG_DEV_ERROR(dev, "failed to increase volt %lu\n",
1103*4882a593Smuzhiyun 				      volt);
1104*4882a593Smuzhiyun 			return ret;
1105*4882a593Smuzhiyun 		}
1106*4882a593Smuzhiyun 	}
1107*4882a593Smuzhiyun 	LOG_DEV_DEBUG(dev, "%luHz %luuV -> %luHz %luuV\n", old_freq, old_volt,
1108*4882a593Smuzhiyun 		      freq, volt);
1109*4882a593Smuzhiyun 	ret = clk_set_rate(rknpu_dev->clks[0].clk, freq);
1110*4882a593Smuzhiyun 	if (ret) {
1111*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to set clock %lu\n", freq);
1112*4882a593Smuzhiyun 		return ret;
1113*4882a593Smuzhiyun 	}
1114*4882a593Smuzhiyun 	*target_freq = freq;
1115*4882a593Smuzhiyun 	rknpu_dev->current_freq = freq;
1116*4882a593Smuzhiyun 
1117*4882a593Smuzhiyun 	if (rknpu_dev->devfreq)
1118*4882a593Smuzhiyun 		rknpu_dev->devfreq->last_status.current_frequency = freq;
1119*4882a593Smuzhiyun 
1120*4882a593Smuzhiyun 	if (rknpu_dev->vdd && old_volt != volt && old_freq > freq) {
1121*4882a593Smuzhiyun 		ret = regulator_set_voltage(rknpu_dev->vdd, volt, INT_MAX);
1122*4882a593Smuzhiyun 		if (ret) {
1123*4882a593Smuzhiyun 			LOG_DEV_ERROR(dev, "failed to decrease volt %lu\n",
1124*4882a593Smuzhiyun 				      volt);
1125*4882a593Smuzhiyun 			return ret;
1126*4882a593Smuzhiyun 		}
1127*4882a593Smuzhiyun 	}
1128*4882a593Smuzhiyun 	rknpu_dev->current_volt = volt;
1129*4882a593Smuzhiyun 
1130*4882a593Smuzhiyun 	LOG_DEV_INFO(dev, "set rknpu freq: %lu, volt: %lu\n",
1131*4882a593Smuzhiyun 		     rknpu_dev->current_freq, rknpu_dev->current_volt);
1132*4882a593Smuzhiyun 
1133*4882a593Smuzhiyun 	return ret;
1134*4882a593Smuzhiyun }
1135*4882a593Smuzhiyun #endif
1136*4882a593Smuzhiyun 
npu_devfreq_get_dev_status(struct device * dev,struct devfreq_dev_status * stat)1137*4882a593Smuzhiyun static int npu_devfreq_get_dev_status(struct device *dev,
1138*4882a593Smuzhiyun 				      struct devfreq_dev_status *stat)
1139*4882a593Smuzhiyun {
1140*4882a593Smuzhiyun 	return 0;
1141*4882a593Smuzhiyun }
1142*4882a593Smuzhiyun 
npu_devfreq_get_cur_freq(struct device * dev,unsigned long * freq)1143*4882a593Smuzhiyun static int npu_devfreq_get_cur_freq(struct device *dev, unsigned long *freq)
1144*4882a593Smuzhiyun {
1145*4882a593Smuzhiyun 	struct rknpu_device *rknpu_dev = dev_get_drvdata(dev);
1146*4882a593Smuzhiyun 
1147*4882a593Smuzhiyun 	*freq = rknpu_dev->current_freq;
1148*4882a593Smuzhiyun 
1149*4882a593Smuzhiyun 	return 0;
1150*4882a593Smuzhiyun }
1151*4882a593Smuzhiyun 
1152*4882a593Smuzhiyun static struct devfreq_dev_profile npu_devfreq_profile = {
1153*4882a593Smuzhiyun 	.polling_ms = 50,
1154*4882a593Smuzhiyun 	.target = npu_devfreq_target,
1155*4882a593Smuzhiyun 	.get_dev_status = npu_devfreq_get_dev_status,
1156*4882a593Smuzhiyun 	.get_cur_freq = npu_devfreq_get_cur_freq,
1157*4882a593Smuzhiyun };
1158*4882a593Smuzhiyun #endif
1159*4882a593Smuzhiyun 
1160*4882a593Smuzhiyun #ifdef CONFIG_PM_DEVFREQ
devfreq_rknpu_ondemand_func(struct devfreq * df,unsigned long * freq)1161*4882a593Smuzhiyun static int devfreq_rknpu_ondemand_func(struct devfreq *df, unsigned long *freq)
1162*4882a593Smuzhiyun {
1163*4882a593Smuzhiyun 	struct rknpu_device *rknpu_dev = df->data;
1164*4882a593Smuzhiyun 
1165*4882a593Smuzhiyun 	if (rknpu_dev)
1166*4882a593Smuzhiyun 		*freq = rknpu_dev->ondemand_freq;
1167*4882a593Smuzhiyun 	else
1168*4882a593Smuzhiyun 		*freq = df->previous_freq;
1169*4882a593Smuzhiyun 
1170*4882a593Smuzhiyun 	return 0;
1171*4882a593Smuzhiyun }
1172*4882a593Smuzhiyun 
devfreq_rknpu_ondemand_handler(struct devfreq * devfreq,unsigned int event,void * data)1173*4882a593Smuzhiyun static int devfreq_rknpu_ondemand_handler(struct devfreq *devfreq,
1174*4882a593Smuzhiyun 					  unsigned int event, void *data)
1175*4882a593Smuzhiyun {
1176*4882a593Smuzhiyun 	return 0;
1177*4882a593Smuzhiyun }
1178*4882a593Smuzhiyun 
1179*4882a593Smuzhiyun static struct devfreq_governor devfreq_rknpu_ondemand = {
1180*4882a593Smuzhiyun 	.name = "rknpu_ondemand",
1181*4882a593Smuzhiyun 	.get_target_freq = devfreq_rknpu_ondemand_func,
1182*4882a593Smuzhiyun 	.event_handler = devfreq_rknpu_ondemand_handler,
1183*4882a593Smuzhiyun };
1184*4882a593Smuzhiyun #endif
1185*4882a593Smuzhiyun 
1186*4882a593Smuzhiyun #if KERNEL_VERSION(6, 1, 0) > LINUX_VERSION_CODE
npu_get_static_power(struct devfreq * devfreq,unsigned long voltage)1187*4882a593Smuzhiyun static unsigned long npu_get_static_power(struct devfreq *devfreq,
1188*4882a593Smuzhiyun 					  unsigned long voltage)
1189*4882a593Smuzhiyun {
1190*4882a593Smuzhiyun 	struct device *dev = devfreq->dev.parent;
1191*4882a593Smuzhiyun 	struct rknpu_device *rknpu_dev = dev_get_drvdata(dev);
1192*4882a593Smuzhiyun 
1193*4882a593Smuzhiyun 	if (!rknpu_dev->model_data)
1194*4882a593Smuzhiyun 		return 0;
1195*4882a593Smuzhiyun 
1196*4882a593Smuzhiyun 	return rockchip_ipa_get_static_power(rknpu_dev->model_data, voltage);
1197*4882a593Smuzhiyun }
1198*4882a593Smuzhiyun 
1199*4882a593Smuzhiyun static struct devfreq_cooling_power npu_cooling_power = {
1200*4882a593Smuzhiyun 	.get_static_power = &npu_get_static_power,
1201*4882a593Smuzhiyun };
1202*4882a593Smuzhiyun 
1203*4882a593Smuzhiyun #if KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE
rk3588_npu_get_soc_info(struct device * dev,struct device_node * np,int * bin,int * process)1204*4882a593Smuzhiyun static int rk3588_npu_get_soc_info(struct device *dev, struct device_node *np,
1205*4882a593Smuzhiyun 				   int *bin, int *process)
1206*4882a593Smuzhiyun {
1207*4882a593Smuzhiyun 	int ret = 0;
1208*4882a593Smuzhiyun 	u8 value = 0;
1209*4882a593Smuzhiyun 
1210*4882a593Smuzhiyun 	if (!bin)
1211*4882a593Smuzhiyun 		return 0;
1212*4882a593Smuzhiyun 
1213*4882a593Smuzhiyun 	if (of_property_match_string(np, "nvmem-cell-names",
1214*4882a593Smuzhiyun 				     "specification_serial_number") >= 0) {
1215*4882a593Smuzhiyun 		ret = rockchip_nvmem_cell_read_u8(
1216*4882a593Smuzhiyun 			np, "specification_serial_number", &value);
1217*4882a593Smuzhiyun 		if (ret) {
1218*4882a593Smuzhiyun 			LOG_DEV_ERROR(
1219*4882a593Smuzhiyun 				dev,
1220*4882a593Smuzhiyun 				"Failed to get specification_serial_number\n");
1221*4882a593Smuzhiyun 			return ret;
1222*4882a593Smuzhiyun 		}
1223*4882a593Smuzhiyun 		/* RK3588M */
1224*4882a593Smuzhiyun 		if (value == 0xd)
1225*4882a593Smuzhiyun 			*bin = 1;
1226*4882a593Smuzhiyun 		/* RK3588J */
1227*4882a593Smuzhiyun 		else if (value == 0xa)
1228*4882a593Smuzhiyun 			*bin = 2;
1229*4882a593Smuzhiyun 	}
1230*4882a593Smuzhiyun 	if (*bin < 0)
1231*4882a593Smuzhiyun 		*bin = 0;
1232*4882a593Smuzhiyun 	LOG_DEV_INFO(dev, "bin=%d\n", *bin);
1233*4882a593Smuzhiyun 
1234*4882a593Smuzhiyun 	return ret;
1235*4882a593Smuzhiyun }
1236*4882a593Smuzhiyun 
rk3588_npu_set_soc_info(struct device * dev,struct device_node * np,int bin,int process,int volt_sel)1237*4882a593Smuzhiyun static int rk3588_npu_set_soc_info(struct device *dev, struct device_node *np,
1238*4882a593Smuzhiyun 				   int bin, int process, int volt_sel)
1239*4882a593Smuzhiyun {
1240*4882a593Smuzhiyun 	struct opp_table *opp_table;
1241*4882a593Smuzhiyun 	u32 supported_hw[2];
1242*4882a593Smuzhiyun 
1243*4882a593Smuzhiyun 	if (volt_sel < 0)
1244*4882a593Smuzhiyun 		return 0;
1245*4882a593Smuzhiyun 	if (bin < 0)
1246*4882a593Smuzhiyun 		bin = 0;
1247*4882a593Smuzhiyun 
1248*4882a593Smuzhiyun 	if (!of_property_read_bool(np, "rockchip,supported-hw"))
1249*4882a593Smuzhiyun 		return 0;
1250*4882a593Smuzhiyun 
1251*4882a593Smuzhiyun 	/* SoC Version */
1252*4882a593Smuzhiyun 	supported_hw[0] = BIT(bin);
1253*4882a593Smuzhiyun 	/* Speed Grade */
1254*4882a593Smuzhiyun 	supported_hw[1] = BIT(volt_sel);
1255*4882a593Smuzhiyun 	opp_table = dev_pm_opp_set_supported_hw(dev, supported_hw, 2);
1256*4882a593Smuzhiyun 	if (IS_ERR(opp_table)) {
1257*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to set supported opp\n");
1258*4882a593Smuzhiyun 		return PTR_ERR(opp_table);
1259*4882a593Smuzhiyun 	}
1260*4882a593Smuzhiyun 
1261*4882a593Smuzhiyun 	return 0;
1262*4882a593Smuzhiyun }
1263*4882a593Smuzhiyun 
rk3588_npu_set_read_margin(struct device * dev,struct rockchip_opp_info * opp_info,u32 rm)1264*4882a593Smuzhiyun static int rk3588_npu_set_read_margin(struct device *dev,
1265*4882a593Smuzhiyun 				      struct rockchip_opp_info *opp_info,
1266*4882a593Smuzhiyun 				      u32 rm)
1267*4882a593Smuzhiyun {
1268*4882a593Smuzhiyun 	u32 offset = 0, val = 0;
1269*4882a593Smuzhiyun 	int i, ret = 0;
1270*4882a593Smuzhiyun 
1271*4882a593Smuzhiyun 	if (!opp_info->grf || !opp_info->volt_rm_tbl)
1272*4882a593Smuzhiyun 		return 0;
1273*4882a593Smuzhiyun 
1274*4882a593Smuzhiyun 	if (rm == opp_info->current_rm || rm == UINT_MAX)
1275*4882a593Smuzhiyun 		return 0;
1276*4882a593Smuzhiyun 
1277*4882a593Smuzhiyun 	LOG_DEV_DEBUG(dev, "set rm to %d\n", rm);
1278*4882a593Smuzhiyun 
1279*4882a593Smuzhiyun 	for (i = 0; i < 3; i++) {
1280*4882a593Smuzhiyun 		ret = regmap_read(opp_info->grf, offset, &val);
1281*4882a593Smuzhiyun 		if (ret < 0) {
1282*4882a593Smuzhiyun 			LOG_DEV_ERROR(dev, "failed to get rm from 0x%x\n",
1283*4882a593Smuzhiyun 				      offset);
1284*4882a593Smuzhiyun 			return ret;
1285*4882a593Smuzhiyun 		}
1286*4882a593Smuzhiyun 		val &= ~0x1c;
1287*4882a593Smuzhiyun 		regmap_write(opp_info->grf, offset, val | (rm << 2));
1288*4882a593Smuzhiyun 		offset += 4;
1289*4882a593Smuzhiyun 	}
1290*4882a593Smuzhiyun 	opp_info->current_rm = rm;
1291*4882a593Smuzhiyun 
1292*4882a593Smuzhiyun 	return 0;
1293*4882a593Smuzhiyun }
1294*4882a593Smuzhiyun 
1295*4882a593Smuzhiyun static const struct rockchip_opp_data rk3588_npu_opp_data = {
1296*4882a593Smuzhiyun 	.get_soc_info = rk3588_npu_get_soc_info,
1297*4882a593Smuzhiyun 	.set_soc_info = rk3588_npu_set_soc_info,
1298*4882a593Smuzhiyun 	.set_read_margin = rk3588_npu_set_read_margin,
1299*4882a593Smuzhiyun };
1300*4882a593Smuzhiyun 
1301*4882a593Smuzhiyun static const struct of_device_id rockchip_npu_of_match[] = {
1302*4882a593Smuzhiyun 	{
1303*4882a593Smuzhiyun 		.compatible = "rockchip,rk3588",
1304*4882a593Smuzhiyun 		.data = (void *)&rk3588_npu_opp_data,
1305*4882a593Smuzhiyun 	},
1306*4882a593Smuzhiyun 	{},
1307*4882a593Smuzhiyun };
1308*4882a593Smuzhiyun 
rknpu_devfreq_init(struct rknpu_device * rknpu_dev)1309*4882a593Smuzhiyun static int rknpu_devfreq_init(struct rknpu_device *rknpu_dev)
1310*4882a593Smuzhiyun {
1311*4882a593Smuzhiyun 	struct device *dev = rknpu_dev->dev;
1312*4882a593Smuzhiyun 	struct devfreq_dev_profile *dp = &npu_devfreq_profile;
1313*4882a593Smuzhiyun 	struct dev_pm_opp *opp;
1314*4882a593Smuzhiyun 	struct opp_table *reg_table = NULL;
1315*4882a593Smuzhiyun 	struct opp_table *opp_table = NULL;
1316*4882a593Smuzhiyun 	const char *const reg_names[] = { "rknpu", "mem" };
1317*4882a593Smuzhiyun 	int ret = -EINVAL;
1318*4882a593Smuzhiyun 
1319*4882a593Smuzhiyun 	if (of_find_property(dev->of_node, "rknpu-supply", NULL) &&
1320*4882a593Smuzhiyun 	    of_find_property(dev->of_node, "mem-supply", NULL)) {
1321*4882a593Smuzhiyun 		reg_table = dev_pm_opp_set_regulators(dev, reg_names, 2);
1322*4882a593Smuzhiyun 		if (IS_ERR(reg_table))
1323*4882a593Smuzhiyun 			return PTR_ERR(reg_table);
1324*4882a593Smuzhiyun 		opp_table =
1325*4882a593Smuzhiyun 			dev_pm_opp_register_set_opp_helper(dev, npu_opp_helper);
1326*4882a593Smuzhiyun 		if (IS_ERR(opp_table)) {
1327*4882a593Smuzhiyun 			dev_pm_opp_put_regulators(reg_table);
1328*4882a593Smuzhiyun 			return PTR_ERR(opp_table);
1329*4882a593Smuzhiyun 		}
1330*4882a593Smuzhiyun 	} else {
1331*4882a593Smuzhiyun 		reg_table = dev_pm_opp_set_regulators(dev, reg_names, 1);
1332*4882a593Smuzhiyun 		if (IS_ERR(reg_table))
1333*4882a593Smuzhiyun 			return PTR_ERR(reg_table);
1334*4882a593Smuzhiyun 	}
1335*4882a593Smuzhiyun 
1336*4882a593Smuzhiyun 	rockchip_get_opp_data(rockchip_npu_of_match, &rknpu_dev->opp_info);
1337*4882a593Smuzhiyun 	ret = rockchip_init_opp_table(dev, &rknpu_dev->opp_info, "npu_leakage",
1338*4882a593Smuzhiyun 				      "rknpu");
1339*4882a593Smuzhiyun 	if (ret) {
1340*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to init_opp_table\n");
1341*4882a593Smuzhiyun 		return ret;
1342*4882a593Smuzhiyun 	}
1343*4882a593Smuzhiyun 
1344*4882a593Smuzhiyun 	rknpu_dev->current_freq = clk_get_rate(rknpu_dev->clks[0].clk);
1345*4882a593Smuzhiyun 
1346*4882a593Smuzhiyun 	opp = devfreq_recommended_opp(dev, &rknpu_dev->current_freq, 0);
1347*4882a593Smuzhiyun 	if (IS_ERR(opp)) {
1348*4882a593Smuzhiyun 		ret = PTR_ERR(opp);
1349*4882a593Smuzhiyun 		goto err_remove_table;
1350*4882a593Smuzhiyun 	}
1351*4882a593Smuzhiyun 	dev_pm_opp_put(opp);
1352*4882a593Smuzhiyun 	dp->initial_freq = rknpu_dev->current_freq;
1353*4882a593Smuzhiyun 
1354*4882a593Smuzhiyun #ifdef CONFIG_PM_DEVFREQ
1355*4882a593Smuzhiyun 	ret = devfreq_add_governor(&devfreq_rknpu_ondemand);
1356*4882a593Smuzhiyun 	if (ret) {
1357*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to add rknpu_ondemand governor\n");
1358*4882a593Smuzhiyun 		goto err_remove_table;
1359*4882a593Smuzhiyun 	}
1360*4882a593Smuzhiyun #endif
1361*4882a593Smuzhiyun 
1362*4882a593Smuzhiyun 	rknpu_dev->devfreq = devm_devfreq_add_device(dev, dp, "rknpu_ondemand",
1363*4882a593Smuzhiyun 						     (void *)rknpu_dev);
1364*4882a593Smuzhiyun 	if (IS_ERR(rknpu_dev->devfreq)) {
1365*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to add devfreq\n");
1366*4882a593Smuzhiyun 		ret = PTR_ERR(rknpu_dev->devfreq);
1367*4882a593Smuzhiyun 		goto err_remove_governor;
1368*4882a593Smuzhiyun 	}
1369*4882a593Smuzhiyun 	devm_devfreq_register_opp_notifier(dev, rknpu_dev->devfreq);
1370*4882a593Smuzhiyun 
1371*4882a593Smuzhiyun 	rknpu_dev->devfreq->last_status.current_frequency = dp->initial_freq;
1372*4882a593Smuzhiyun 	rknpu_dev->devfreq->last_status.total_time = 1;
1373*4882a593Smuzhiyun 	rknpu_dev->devfreq->last_status.busy_time = 1;
1374*4882a593Smuzhiyun 
1375*4882a593Smuzhiyun 	npu_mdevp.data = rknpu_dev->devfreq;
1376*4882a593Smuzhiyun 	npu_mdevp.opp_info = &rknpu_dev->opp_info;
1377*4882a593Smuzhiyun 	rknpu_dev->mdev_info =
1378*4882a593Smuzhiyun 		rockchip_system_monitor_register(dev, &npu_mdevp);
1379*4882a593Smuzhiyun 	if (IS_ERR(rknpu_dev->mdev_info)) {
1380*4882a593Smuzhiyun 		LOG_DEV_DEBUG(dev, "without system monitor\n");
1381*4882a593Smuzhiyun 		rknpu_dev->mdev_info = NULL;
1382*4882a593Smuzhiyun 		npu_mdevp.is_checked = true;
1383*4882a593Smuzhiyun 	}
1384*4882a593Smuzhiyun 	rknpu_dev->current_freq = clk_get_rate(rknpu_dev->clks[0].clk);
1385*4882a593Smuzhiyun 	rknpu_dev->current_volt = regulator_get_voltage(rknpu_dev->vdd);
1386*4882a593Smuzhiyun 
1387*4882a593Smuzhiyun 	of_property_read_u32(dev->of_node, "dynamic-power-coefficient",
1388*4882a593Smuzhiyun 			     (u32 *)&npu_cooling_power.dyn_power_coeff);
1389*4882a593Smuzhiyun 	rknpu_dev->model_data =
1390*4882a593Smuzhiyun 		rockchip_ipa_power_model_init(dev, "npu_leakage");
1391*4882a593Smuzhiyun 	if (IS_ERR_OR_NULL(rknpu_dev->model_data)) {
1392*4882a593Smuzhiyun 		rknpu_dev->model_data = NULL;
1393*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to initialize power model\n");
1394*4882a593Smuzhiyun 	} else if (rknpu_dev->model_data->dynamic_coefficient) {
1395*4882a593Smuzhiyun 		npu_cooling_power.dyn_power_coeff =
1396*4882a593Smuzhiyun 			rknpu_dev->model_data->dynamic_coefficient;
1397*4882a593Smuzhiyun 	}
1398*4882a593Smuzhiyun 	if (!npu_cooling_power.dyn_power_coeff) {
1399*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to get dynamic-coefficient\n");
1400*4882a593Smuzhiyun 		goto out;
1401*4882a593Smuzhiyun 	}
1402*4882a593Smuzhiyun 
1403*4882a593Smuzhiyun 	rknpu_dev->devfreq_cooling = of_devfreq_cooling_register_power(
1404*4882a593Smuzhiyun 		dev->of_node, rknpu_dev->devfreq, &npu_cooling_power);
1405*4882a593Smuzhiyun 	if (IS_ERR_OR_NULL(rknpu_dev->devfreq_cooling))
1406*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to register cooling device\n");
1407*4882a593Smuzhiyun 
1408*4882a593Smuzhiyun out:
1409*4882a593Smuzhiyun 	return 0;
1410*4882a593Smuzhiyun 
1411*4882a593Smuzhiyun err_remove_governor:
1412*4882a593Smuzhiyun #ifdef CONFIG_PM_DEVFREQ
1413*4882a593Smuzhiyun 	devfreq_remove_governor(&devfreq_rknpu_ondemand);
1414*4882a593Smuzhiyun #endif
1415*4882a593Smuzhiyun err_remove_table:
1416*4882a593Smuzhiyun 	dev_pm_opp_of_remove_table(dev);
1417*4882a593Smuzhiyun 
1418*4882a593Smuzhiyun 	rknpu_dev->devfreq = NULL;
1419*4882a593Smuzhiyun 
1420*4882a593Smuzhiyun 	return ret;
1421*4882a593Smuzhiyun }
1422*4882a593Smuzhiyun 
1423*4882a593Smuzhiyun #else
1424*4882a593Smuzhiyun 
npu_devfreq_adjust_current_freq_volt(struct device * dev,struct rknpu_device * rknpu_dev)1425*4882a593Smuzhiyun static int npu_devfreq_adjust_current_freq_volt(struct device *dev,
1426*4882a593Smuzhiyun 						struct rknpu_device *rknpu_dev)
1427*4882a593Smuzhiyun {
1428*4882a593Smuzhiyun 	unsigned long volt, old_freq, freq;
1429*4882a593Smuzhiyun 	struct dev_pm_opp *opp = NULL;
1430*4882a593Smuzhiyun 	int ret = -EINVAL;
1431*4882a593Smuzhiyun 
1432*4882a593Smuzhiyun 	old_freq = clk_get_rate(rknpu_dev->clks[0].clk);
1433*4882a593Smuzhiyun 	freq = old_freq;
1434*4882a593Smuzhiyun 
1435*4882a593Smuzhiyun #if KERNEL_VERSION(4, 11, 0) > LINUX_VERSION_CODE
1436*4882a593Smuzhiyun 	rcu_read_lock();
1437*4882a593Smuzhiyun #endif
1438*4882a593Smuzhiyun 
1439*4882a593Smuzhiyun 	opp = devfreq_recommended_opp(dev, &freq, 0);
1440*4882a593Smuzhiyun 	volt = dev_pm_opp_get_voltage(opp);
1441*4882a593Smuzhiyun 
1442*4882a593Smuzhiyun #if KERNEL_VERSION(4, 11, 0) > LINUX_VERSION_CODE
1443*4882a593Smuzhiyun 	rcu_read_unlock();
1444*4882a593Smuzhiyun #endif
1445*4882a593Smuzhiyun 
1446*4882a593Smuzhiyun 	if (freq >= old_freq && rknpu_dev->vdd) {
1447*4882a593Smuzhiyun 		ret = regulator_set_voltage(rknpu_dev->vdd, volt, INT_MAX);
1448*4882a593Smuzhiyun 		if (ret) {
1449*4882a593Smuzhiyun 			LOG_DEV_ERROR(dev, "failed to set volt %lu\n", volt);
1450*4882a593Smuzhiyun 			return ret;
1451*4882a593Smuzhiyun 		}
1452*4882a593Smuzhiyun 	}
1453*4882a593Smuzhiyun 	LOG_DEV_DEBUG(dev, "adjust current freq=%luHz, volt=%luuV\n", freq,
1454*4882a593Smuzhiyun 		      volt);
1455*4882a593Smuzhiyun 	ret = clk_set_rate(rknpu_dev->clks[0].clk, freq);
1456*4882a593Smuzhiyun 	if (ret) {
1457*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to set clock %lu\n", freq);
1458*4882a593Smuzhiyun 		return ret;
1459*4882a593Smuzhiyun 	}
1460*4882a593Smuzhiyun 	if (freq < old_freq && rknpu_dev->vdd) {
1461*4882a593Smuzhiyun 		ret = regulator_set_voltage(rknpu_dev->vdd, volt, INT_MAX);
1462*4882a593Smuzhiyun 		if (ret) {
1463*4882a593Smuzhiyun 			LOG_DEV_ERROR(dev, "failed to set volt %lu\n", volt);
1464*4882a593Smuzhiyun 			return ret;
1465*4882a593Smuzhiyun 		}
1466*4882a593Smuzhiyun 	}
1467*4882a593Smuzhiyun 	rknpu_dev->current_freq = freq;
1468*4882a593Smuzhiyun 	rknpu_dev->current_volt = volt;
1469*4882a593Smuzhiyun 
1470*4882a593Smuzhiyun 	return 0;
1471*4882a593Smuzhiyun }
1472*4882a593Smuzhiyun 
rknpu_devfreq_init(struct rknpu_device * rknpu_dev)1473*4882a593Smuzhiyun static int rknpu_devfreq_init(struct rknpu_device *rknpu_dev)
1474*4882a593Smuzhiyun {
1475*4882a593Smuzhiyun 	struct device *dev = rknpu_dev->dev;
1476*4882a593Smuzhiyun 	struct devfreq_dev_profile *dp = &npu_devfreq_profile;
1477*4882a593Smuzhiyun 	int ret = -EINVAL;
1478*4882a593Smuzhiyun 
1479*4882a593Smuzhiyun 	ret = rockchip_init_opp_table(dev, NULL, "npu_leakage", "rknpu");
1480*4882a593Smuzhiyun 	if (ret) {
1481*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to init_opp_table\n");
1482*4882a593Smuzhiyun 		return ret;
1483*4882a593Smuzhiyun 	}
1484*4882a593Smuzhiyun 
1485*4882a593Smuzhiyun 	ret = npu_devfreq_adjust_current_freq_volt(dev, rknpu_dev);
1486*4882a593Smuzhiyun 	if (ret) {
1487*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to adjust current freq volt\n");
1488*4882a593Smuzhiyun 		goto err_remove_table;
1489*4882a593Smuzhiyun 	}
1490*4882a593Smuzhiyun 	dp->initial_freq = rknpu_dev->current_freq;
1491*4882a593Smuzhiyun 
1492*4882a593Smuzhiyun #ifdef CONFIG_PM_DEVFREQ
1493*4882a593Smuzhiyun 	ret = devfreq_add_governor(&devfreq_rknpu_ondemand);
1494*4882a593Smuzhiyun 	if (ret) {
1495*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to add rknpu_ondemand governor\n");
1496*4882a593Smuzhiyun 		goto err_remove_table;
1497*4882a593Smuzhiyun 	}
1498*4882a593Smuzhiyun #endif
1499*4882a593Smuzhiyun 
1500*4882a593Smuzhiyun 	rknpu_dev->devfreq = devm_devfreq_add_device(dev, dp, "rknpu_ondemand",
1501*4882a593Smuzhiyun 						     (void *)rknpu_dev);
1502*4882a593Smuzhiyun 	if (IS_ERR(rknpu_dev->devfreq)) {
1503*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to add devfreq\n");
1504*4882a593Smuzhiyun 		ret = PTR_ERR(rknpu_dev->devfreq);
1505*4882a593Smuzhiyun 		goto err_remove_governor;
1506*4882a593Smuzhiyun 	}
1507*4882a593Smuzhiyun 	devm_devfreq_register_opp_notifier(dev, rknpu_dev->devfreq);
1508*4882a593Smuzhiyun 
1509*4882a593Smuzhiyun 	rknpu_dev->devfreq->last_status.current_frequency = dp->initial_freq;
1510*4882a593Smuzhiyun 	rknpu_dev->devfreq->last_status.total_time = 1;
1511*4882a593Smuzhiyun 	rknpu_dev->devfreq->last_status.busy_time = 1;
1512*4882a593Smuzhiyun 
1513*4882a593Smuzhiyun 	npu_mdevp.data = rknpu_dev->devfreq;
1514*4882a593Smuzhiyun 	rknpu_dev->mdev_info =
1515*4882a593Smuzhiyun 		rockchip_system_monitor_register(dev, &npu_mdevp);
1516*4882a593Smuzhiyun 	if (IS_ERR(rknpu_dev->mdev_info)) {
1517*4882a593Smuzhiyun 		LOG_DEV_DEBUG(dev, "without system monitor\n");
1518*4882a593Smuzhiyun 		rknpu_dev->mdev_info = NULL;
1519*4882a593Smuzhiyun 	}
1520*4882a593Smuzhiyun 	rknpu_dev->current_freq = clk_get_rate(rknpu_dev->clks[0].clk);
1521*4882a593Smuzhiyun 	rknpu_dev->current_volt = regulator_get_voltage(rknpu_dev->vdd);
1522*4882a593Smuzhiyun 
1523*4882a593Smuzhiyun 	of_property_read_u32(dev->of_node, "dynamic-power-coefficient",
1524*4882a593Smuzhiyun 			     (u32 *)&npu_cooling_power.dyn_power_coeff);
1525*4882a593Smuzhiyun 	rknpu_dev->model_data =
1526*4882a593Smuzhiyun 		rockchip_ipa_power_model_init(dev, "npu_leakage");
1527*4882a593Smuzhiyun 	if (IS_ERR_OR_NULL(rknpu_dev->model_data)) {
1528*4882a593Smuzhiyun 		rknpu_dev->model_data = NULL;
1529*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to initialize power model\n");
1530*4882a593Smuzhiyun 	} else if (rknpu_dev->model_data->dynamic_coefficient) {
1531*4882a593Smuzhiyun 		npu_cooling_power.dyn_power_coeff =
1532*4882a593Smuzhiyun 			rknpu_dev->model_data->dynamic_coefficient;
1533*4882a593Smuzhiyun 	}
1534*4882a593Smuzhiyun 
1535*4882a593Smuzhiyun 	if (!npu_cooling_power.dyn_power_coeff) {
1536*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to get dynamic-coefficient\n");
1537*4882a593Smuzhiyun 		goto out;
1538*4882a593Smuzhiyun 	}
1539*4882a593Smuzhiyun 
1540*4882a593Smuzhiyun 	rknpu_dev->devfreq_cooling = of_devfreq_cooling_register_power(
1541*4882a593Smuzhiyun 		dev->of_node, rknpu_dev->devfreq, &npu_cooling_power);
1542*4882a593Smuzhiyun 	if (IS_ERR_OR_NULL(rknpu_dev->devfreq_cooling))
1543*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to register cooling device\n");
1544*4882a593Smuzhiyun 
1545*4882a593Smuzhiyun out:
1546*4882a593Smuzhiyun 	return 0;
1547*4882a593Smuzhiyun 
1548*4882a593Smuzhiyun err_remove_governor:
1549*4882a593Smuzhiyun #ifdef CONFIG_PM_DEVFREQ
1550*4882a593Smuzhiyun 	devfreq_remove_governor(&devfreq_rknpu_ondemand);
1551*4882a593Smuzhiyun #endif
1552*4882a593Smuzhiyun err_remove_table:
1553*4882a593Smuzhiyun 	dev_pm_opp_of_remove_table(dev);
1554*4882a593Smuzhiyun 
1555*4882a593Smuzhiyun 	rknpu_dev->devfreq = NULL;
1556*4882a593Smuzhiyun 
1557*4882a593Smuzhiyun 	return ret;
1558*4882a593Smuzhiyun }
1559*4882a593Smuzhiyun #endif
1560*4882a593Smuzhiyun #endif
1561*4882a593Smuzhiyun 
rknpu_devfreq_remove(struct rknpu_device * rknpu_dev)1562*4882a593Smuzhiyun static int rknpu_devfreq_remove(struct rknpu_device *rknpu_dev)
1563*4882a593Smuzhiyun {
1564*4882a593Smuzhiyun 	if (rknpu_dev->devfreq) {
1565*4882a593Smuzhiyun 		devfreq_unregister_opp_notifier(rknpu_dev->dev,
1566*4882a593Smuzhiyun 						rknpu_dev->devfreq);
1567*4882a593Smuzhiyun 		dev_pm_opp_of_remove_table(rknpu_dev->dev);
1568*4882a593Smuzhiyun #ifdef CONFIG_PM_DEVFREQ
1569*4882a593Smuzhiyun 		devfreq_remove_governor(&devfreq_rknpu_ondemand);
1570*4882a593Smuzhiyun #endif
1571*4882a593Smuzhiyun 	}
1572*4882a593Smuzhiyun 
1573*4882a593Smuzhiyun 	return 0;
1574*4882a593Smuzhiyun }
1575*4882a593Smuzhiyun 
1576*4882a593Smuzhiyun #endif
1577*4882a593Smuzhiyun 
rknpu_register_irq(struct platform_device * pdev,struct rknpu_device * rknpu_dev)1578*4882a593Smuzhiyun static int rknpu_register_irq(struct platform_device *pdev,
1579*4882a593Smuzhiyun 			      struct rknpu_device *rknpu_dev)
1580*4882a593Smuzhiyun {
1581*4882a593Smuzhiyun 	const struct rknpu_config *config = rknpu_dev->config;
1582*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
1583*4882a593Smuzhiyun #if KERNEL_VERSION(6, 1, 0) > LINUX_VERSION_CODE
1584*4882a593Smuzhiyun 	struct resource *res;
1585*4882a593Smuzhiyun #endif
1586*4882a593Smuzhiyun 	int i, ret, irq;
1587*4882a593Smuzhiyun 
1588*4882a593Smuzhiyun #if KERNEL_VERSION(6, 1, 0) > LINUX_VERSION_CODE
1589*4882a593Smuzhiyun 	res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1590*4882a593Smuzhiyun 					   config->irqs[0].name);
1591*4882a593Smuzhiyun 	if (res) {
1592*4882a593Smuzhiyun 		/* there are irq names in dts */
1593*4882a593Smuzhiyun 		for (i = 0; i < config->num_irqs; i++) {
1594*4882a593Smuzhiyun 			irq = platform_get_irq_byname(pdev,
1595*4882a593Smuzhiyun 						      config->irqs[i].name);
1596*4882a593Smuzhiyun 			if (irq < 0) {
1597*4882a593Smuzhiyun 				LOG_DEV_ERROR(dev, "no npu %s in dts\n",
1598*4882a593Smuzhiyun 					      config->irqs[i].name);
1599*4882a593Smuzhiyun 				return irq;
1600*4882a593Smuzhiyun 			}
1601*4882a593Smuzhiyun 
1602*4882a593Smuzhiyun 			ret = devm_request_irq(dev, irq,
1603*4882a593Smuzhiyun 					       config->irqs[i].irq_hdl,
1604*4882a593Smuzhiyun 					       IRQF_SHARED, dev_name(dev),
1605*4882a593Smuzhiyun 					       rknpu_dev);
1606*4882a593Smuzhiyun 			if (ret < 0) {
1607*4882a593Smuzhiyun 				LOG_DEV_ERROR(dev, "request %s failed: %d\n",
1608*4882a593Smuzhiyun 					      config->irqs[i].name, ret);
1609*4882a593Smuzhiyun 				return ret;
1610*4882a593Smuzhiyun 			}
1611*4882a593Smuzhiyun 		}
1612*4882a593Smuzhiyun 	} else {
1613*4882a593Smuzhiyun 		/* no irq names in dts */
1614*4882a593Smuzhiyun 		irq = platform_get_irq(pdev, 0);
1615*4882a593Smuzhiyun 		if (irq < 0) {
1616*4882a593Smuzhiyun 			LOG_DEV_ERROR(dev, "no npu irq in dts\n");
1617*4882a593Smuzhiyun 			return irq;
1618*4882a593Smuzhiyun 		}
1619*4882a593Smuzhiyun 
1620*4882a593Smuzhiyun 		ret = devm_request_irq(dev, irq, rknpu_core0_irq_handler,
1621*4882a593Smuzhiyun 				       IRQF_SHARED, dev_name(dev), rknpu_dev);
1622*4882a593Smuzhiyun 		if (ret < 0) {
1623*4882a593Smuzhiyun 			LOG_DEV_ERROR(dev, "request irq failed: %d\n", ret);
1624*4882a593Smuzhiyun 			return ret;
1625*4882a593Smuzhiyun 		}
1626*4882a593Smuzhiyun 	}
1627*4882a593Smuzhiyun #else
1628*4882a593Smuzhiyun 	/* there are irq names in dts */
1629*4882a593Smuzhiyun 	for (i = 0; i < config->num_irqs; i++) {
1630*4882a593Smuzhiyun 		irq = platform_get_irq_byname(pdev, config->irqs[i].name);
1631*4882a593Smuzhiyun 		if (irq < 0) {
1632*4882a593Smuzhiyun 			LOG_DEV_ERROR(dev, "no npu %s in dts\n",
1633*4882a593Smuzhiyun 				      config->irqs[i].name);
1634*4882a593Smuzhiyun 			return irq;
1635*4882a593Smuzhiyun 		}
1636*4882a593Smuzhiyun 
1637*4882a593Smuzhiyun 		ret = devm_request_irq(dev, irq, config->irqs[i].irq_hdl,
1638*4882a593Smuzhiyun 				       IRQF_SHARED, dev_name(dev), rknpu_dev);
1639*4882a593Smuzhiyun 		if (ret < 0) {
1640*4882a593Smuzhiyun 			LOG_DEV_ERROR(dev, "request %s failed: %d\n",
1641*4882a593Smuzhiyun 				      config->irqs[i].name, ret);
1642*4882a593Smuzhiyun 			return ret;
1643*4882a593Smuzhiyun 		}
1644*4882a593Smuzhiyun 	}
1645*4882a593Smuzhiyun #endif
1646*4882a593Smuzhiyun 
1647*4882a593Smuzhiyun 	return 0;
1648*4882a593Smuzhiyun }
1649*4882a593Smuzhiyun 
rknpu_find_sram_resource(struct rknpu_device * rknpu_dev)1650*4882a593Smuzhiyun static int rknpu_find_sram_resource(struct rknpu_device *rknpu_dev)
1651*4882a593Smuzhiyun {
1652*4882a593Smuzhiyun 	struct device *dev = rknpu_dev->dev;
1653*4882a593Smuzhiyun 	struct device_node *sram_node = NULL;
1654*4882a593Smuzhiyun 	struct resource sram_res;
1655*4882a593Smuzhiyun 	uint32_t sram_size = 0;
1656*4882a593Smuzhiyun 	int ret = -EINVAL;
1657*4882a593Smuzhiyun 
1658*4882a593Smuzhiyun 	/* get sram device node */
1659*4882a593Smuzhiyun 	sram_node = of_parse_phandle(dev->of_node, "rockchip,sram", 0);
1660*4882a593Smuzhiyun 	rknpu_dev->sram_size = 0;
1661*4882a593Smuzhiyun 	if (!sram_node)
1662*4882a593Smuzhiyun 		return -EINVAL;
1663*4882a593Smuzhiyun 
1664*4882a593Smuzhiyun 	/* get sram start and size */
1665*4882a593Smuzhiyun 	ret = of_address_to_resource(sram_node, 0, &sram_res);
1666*4882a593Smuzhiyun 	of_node_put(sram_node);
1667*4882a593Smuzhiyun 	if (ret)
1668*4882a593Smuzhiyun 		return ret;
1669*4882a593Smuzhiyun 
1670*4882a593Smuzhiyun 	/* check sram start and size is PAGE_SIZE align */
1671*4882a593Smuzhiyun 	rknpu_dev->sram_start = round_up(sram_res.start, PAGE_SIZE);
1672*4882a593Smuzhiyun 	rknpu_dev->sram_end = round_down(
1673*4882a593Smuzhiyun 		sram_res.start + resource_size(&sram_res), PAGE_SIZE);
1674*4882a593Smuzhiyun 	if (rknpu_dev->sram_end <= rknpu_dev->sram_start) {
1675*4882a593Smuzhiyun 		LOG_DEV_WARN(
1676*4882a593Smuzhiyun 			dev,
1677*4882a593Smuzhiyun 			"invalid sram resource, sram start %pa, sram end %pa\n",
1678*4882a593Smuzhiyun 			&rknpu_dev->sram_start, &rknpu_dev->sram_end);
1679*4882a593Smuzhiyun 		return -EINVAL;
1680*4882a593Smuzhiyun 	}
1681*4882a593Smuzhiyun 
1682*4882a593Smuzhiyun 	sram_size = rknpu_dev->sram_end - rknpu_dev->sram_start;
1683*4882a593Smuzhiyun 
1684*4882a593Smuzhiyun 	rknpu_dev->sram_base_io =
1685*4882a593Smuzhiyun 		devm_ioremap(dev, rknpu_dev->sram_start, sram_size);
1686*4882a593Smuzhiyun 	if (IS_ERR(rknpu_dev->sram_base_io)) {
1687*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to remap sram base io!\n");
1688*4882a593Smuzhiyun 		rknpu_dev->sram_base_io = NULL;
1689*4882a593Smuzhiyun 	}
1690*4882a593Smuzhiyun 
1691*4882a593Smuzhiyun 	rknpu_dev->sram_size = sram_size;
1692*4882a593Smuzhiyun 
1693*4882a593Smuzhiyun 	LOG_DEV_INFO(dev, "sram region: [%pa, %pa), sram size: %#x\n",
1694*4882a593Smuzhiyun 		     &rknpu_dev->sram_start, &rknpu_dev->sram_end,
1695*4882a593Smuzhiyun 		     rknpu_dev->sram_size);
1696*4882a593Smuzhiyun 
1697*4882a593Smuzhiyun 	return 0;
1698*4882a593Smuzhiyun }
1699*4882a593Smuzhiyun 
rknpu_find_nbuf_resource(struct rknpu_device * rknpu_dev)1700*4882a593Smuzhiyun static int rknpu_find_nbuf_resource(struct rknpu_device *rknpu_dev)
1701*4882a593Smuzhiyun {
1702*4882a593Smuzhiyun 	struct device *dev = rknpu_dev->dev;
1703*4882a593Smuzhiyun 
1704*4882a593Smuzhiyun 	if (rknpu_dev->config->nbuf_size == 0)
1705*4882a593Smuzhiyun 		return -EINVAL;
1706*4882a593Smuzhiyun 
1707*4882a593Smuzhiyun 	rknpu_dev->nbuf_start = rknpu_dev->config->nbuf_phyaddr;
1708*4882a593Smuzhiyun 	rknpu_dev->nbuf_size = rknpu_dev->config->nbuf_size;
1709*4882a593Smuzhiyun 	rknpu_dev->nbuf_base_io =
1710*4882a593Smuzhiyun 		devm_ioremap(dev, rknpu_dev->nbuf_start, rknpu_dev->nbuf_size);
1711*4882a593Smuzhiyun 	if (IS_ERR(rknpu_dev->nbuf_base_io)) {
1712*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to remap nbuf base io!\n");
1713*4882a593Smuzhiyun 		rknpu_dev->nbuf_base_io = NULL;
1714*4882a593Smuzhiyun 	}
1715*4882a593Smuzhiyun 
1716*4882a593Smuzhiyun 	rknpu_dev->nbuf_end = rknpu_dev->nbuf_start + rknpu_dev->nbuf_size;
1717*4882a593Smuzhiyun 
1718*4882a593Smuzhiyun 	LOG_DEV_INFO(dev, "nbuf region: [%pa, %pa), nbuf size: %#x\n",
1719*4882a593Smuzhiyun 		     &rknpu_dev->nbuf_start, &rknpu_dev->nbuf_end,
1720*4882a593Smuzhiyun 		     rknpu_dev->nbuf_size);
1721*4882a593Smuzhiyun 
1722*4882a593Smuzhiyun 	return 0;
1723*4882a593Smuzhiyun }
1724*4882a593Smuzhiyun 
rknpu_probe(struct platform_device * pdev)1725*4882a593Smuzhiyun static int rknpu_probe(struct platform_device *pdev)
1726*4882a593Smuzhiyun {
1727*4882a593Smuzhiyun 	struct resource *res = NULL;
1728*4882a593Smuzhiyun 	struct rknpu_device *rknpu_dev = NULL;
1729*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
1730*4882a593Smuzhiyun 	struct device *virt_dev = NULL;
1731*4882a593Smuzhiyun 	const struct of_device_id *match = NULL;
1732*4882a593Smuzhiyun 	const struct rknpu_config *config = NULL;
1733*4882a593Smuzhiyun 	int ret = -EINVAL, i = 0;
1734*4882a593Smuzhiyun 
1735*4882a593Smuzhiyun 	if (!pdev->dev.of_node) {
1736*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "rknpu device-tree data is missing!\n");
1737*4882a593Smuzhiyun 		return -ENODEV;
1738*4882a593Smuzhiyun 	}
1739*4882a593Smuzhiyun 
1740*4882a593Smuzhiyun 	match = of_match_device(rknpu_of_match, dev);
1741*4882a593Smuzhiyun 	if (!match) {
1742*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "rknpu device-tree entry is missing!\n");
1743*4882a593Smuzhiyun 		return -ENODEV;
1744*4882a593Smuzhiyun 	}
1745*4882a593Smuzhiyun 
1746*4882a593Smuzhiyun 	rknpu_dev = devm_kzalloc(dev, sizeof(*rknpu_dev), GFP_KERNEL);
1747*4882a593Smuzhiyun 	if (!rknpu_dev) {
1748*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to allocate rknpu device!\n");
1749*4882a593Smuzhiyun 		return -ENOMEM;
1750*4882a593Smuzhiyun 	}
1751*4882a593Smuzhiyun 
1752*4882a593Smuzhiyun 	config = of_device_get_match_data(dev);
1753*4882a593Smuzhiyun 	if (!config)
1754*4882a593Smuzhiyun 		return -EINVAL;
1755*4882a593Smuzhiyun 
1756*4882a593Smuzhiyun 	rknpu_dev->config = config;
1757*4882a593Smuzhiyun 	rknpu_dev->dev = dev;
1758*4882a593Smuzhiyun 
1759*4882a593Smuzhiyun 	rknpu_dev->iommu_en = rknpu_is_iommu_enable(dev);
1760*4882a593Smuzhiyun 	if (!rknpu_dev->iommu_en) {
1761*4882a593Smuzhiyun 		/* Initialize reserved memory resources */
1762*4882a593Smuzhiyun 		ret = of_reserved_mem_device_init(dev);
1763*4882a593Smuzhiyun 		if (!ret) {
1764*4882a593Smuzhiyun 			LOG_DEV_INFO(
1765*4882a593Smuzhiyun 				dev,
1766*4882a593Smuzhiyun 				"initialize reserved memory for rknpu device!\n");
1767*4882a593Smuzhiyun 		}
1768*4882a593Smuzhiyun 	}
1769*4882a593Smuzhiyun 
1770*4882a593Smuzhiyun 	rknpu_dev->bypass_irq_handler = bypass_irq_handler;
1771*4882a593Smuzhiyun 	rknpu_dev->bypass_soft_reset = bypass_soft_reset;
1772*4882a593Smuzhiyun 
1773*4882a593Smuzhiyun 	rknpu_reset_get(rknpu_dev);
1774*4882a593Smuzhiyun 
1775*4882a593Smuzhiyun 	rknpu_dev->num_clks = devm_clk_bulk_get_all(dev, &rknpu_dev->clks);
1776*4882a593Smuzhiyun 	if (rknpu_dev->num_clks < 1) {
1777*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to get clk source for rknpu\n");
1778*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
1779*4882a593Smuzhiyun 		return -ENODEV;
1780*4882a593Smuzhiyun #endif
1781*4882a593Smuzhiyun 	}
1782*4882a593Smuzhiyun 
1783*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
1784*4882a593Smuzhiyun #if KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE &&                          \
1785*4882a593Smuzhiyun 	KERNEL_VERSION(6, 1, 0) > LINUX_VERSION_CODE
1786*4882a593Smuzhiyun 	if (strstr(__clk_get_name(rknpu_dev->clks[0].clk), "scmi"))
1787*4882a593Smuzhiyun 		rknpu_dev->opp_info.scmi_clk = rknpu_dev->clks[0].clk;
1788*4882a593Smuzhiyun #endif
1789*4882a593Smuzhiyun 
1790*4882a593Smuzhiyun 	rknpu_dev->vdd = devm_regulator_get_optional(dev, "rknpu");
1791*4882a593Smuzhiyun 	if (IS_ERR(rknpu_dev->vdd)) {
1792*4882a593Smuzhiyun 		if (PTR_ERR(rknpu_dev->vdd) != -ENODEV) {
1793*4882a593Smuzhiyun 			ret = PTR_ERR(rknpu_dev->vdd);
1794*4882a593Smuzhiyun 			LOG_DEV_ERROR(
1795*4882a593Smuzhiyun 				dev,
1796*4882a593Smuzhiyun 				"failed to get vdd regulator for rknpu: %d\n",
1797*4882a593Smuzhiyun 				ret);
1798*4882a593Smuzhiyun 			return ret;
1799*4882a593Smuzhiyun 		}
1800*4882a593Smuzhiyun 		rknpu_dev->vdd = NULL;
1801*4882a593Smuzhiyun 	}
1802*4882a593Smuzhiyun 
1803*4882a593Smuzhiyun 	rknpu_dev->mem = devm_regulator_get_optional(dev, "mem");
1804*4882a593Smuzhiyun 	if (IS_ERR(rknpu_dev->mem)) {
1805*4882a593Smuzhiyun 		if (PTR_ERR(rknpu_dev->mem) != -ENODEV) {
1806*4882a593Smuzhiyun 			ret = PTR_ERR(rknpu_dev->mem);
1807*4882a593Smuzhiyun 			LOG_DEV_ERROR(
1808*4882a593Smuzhiyun 				dev,
1809*4882a593Smuzhiyun 				"failed to get mem regulator for rknpu: %d\n",
1810*4882a593Smuzhiyun 				ret);
1811*4882a593Smuzhiyun 			return ret;
1812*4882a593Smuzhiyun 		}
1813*4882a593Smuzhiyun 		rknpu_dev->mem = NULL;
1814*4882a593Smuzhiyun 	}
1815*4882a593Smuzhiyun #endif
1816*4882a593Smuzhiyun 
1817*4882a593Smuzhiyun 	spin_lock_init(&rknpu_dev->lock);
1818*4882a593Smuzhiyun 	spin_lock_init(&rknpu_dev->irq_lock);
1819*4882a593Smuzhiyun 	mutex_init(&rknpu_dev->power_lock);
1820*4882a593Smuzhiyun 	mutex_init(&rknpu_dev->reset_lock);
1821*4882a593Smuzhiyun 	for (i = 0; i < config->num_irqs; i++) {
1822*4882a593Smuzhiyun 		INIT_LIST_HEAD(&rknpu_dev->subcore_datas[i].todo_list);
1823*4882a593Smuzhiyun 		init_waitqueue_head(&rknpu_dev->subcore_datas[i].job_done_wq);
1824*4882a593Smuzhiyun 		rknpu_dev->subcore_datas[i].task_num = 0;
1825*4882a593Smuzhiyun 		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1826*4882a593Smuzhiyun 		if (!res) {
1827*4882a593Smuzhiyun 			LOG_DEV_ERROR(
1828*4882a593Smuzhiyun 				dev,
1829*4882a593Smuzhiyun 				"failed to get memory resource for rknpu\n");
1830*4882a593Smuzhiyun 			return -ENXIO;
1831*4882a593Smuzhiyun 		}
1832*4882a593Smuzhiyun 
1833*4882a593Smuzhiyun 		rknpu_dev->base[i] = devm_ioremap_resource(dev, res);
1834*4882a593Smuzhiyun 		if (PTR_ERR(rknpu_dev->base[i]) == -EBUSY) {
1835*4882a593Smuzhiyun 			rknpu_dev->base[i] = devm_ioremap(dev, res->start,
1836*4882a593Smuzhiyun 							  resource_size(res));
1837*4882a593Smuzhiyun 		}
1838*4882a593Smuzhiyun 
1839*4882a593Smuzhiyun 		if (IS_ERR(rknpu_dev->base[i])) {
1840*4882a593Smuzhiyun 			LOG_DEV_ERROR(dev,
1841*4882a593Smuzhiyun 				      "failed to remap register for rknpu\n");
1842*4882a593Smuzhiyun 			return PTR_ERR(rknpu_dev->base[i]);
1843*4882a593Smuzhiyun 		}
1844*4882a593Smuzhiyun 	}
1845*4882a593Smuzhiyun 
1846*4882a593Smuzhiyun 	if (config->bw_priority_length > 0) {
1847*4882a593Smuzhiyun 		rknpu_dev->bw_priority_base =
1848*4882a593Smuzhiyun 			devm_ioremap(dev, config->bw_priority_addr,
1849*4882a593Smuzhiyun 				     config->bw_priority_length);
1850*4882a593Smuzhiyun 		if (IS_ERR(rknpu_dev->bw_priority_base)) {
1851*4882a593Smuzhiyun 			LOG_DEV_ERROR(
1852*4882a593Smuzhiyun 				rknpu_dev->dev,
1853*4882a593Smuzhiyun 				"failed to remap bw priority register for rknpu\n");
1854*4882a593Smuzhiyun 			rknpu_dev->bw_priority_base = NULL;
1855*4882a593Smuzhiyun 		}
1856*4882a593Smuzhiyun 	}
1857*4882a593Smuzhiyun 
1858*4882a593Smuzhiyun 	if (!rknpu_dev->bypass_irq_handler) {
1859*4882a593Smuzhiyun 		ret = rknpu_register_irq(pdev, rknpu_dev);
1860*4882a593Smuzhiyun 		if (ret)
1861*4882a593Smuzhiyun 			return ret;
1862*4882a593Smuzhiyun 	} else {
1863*4882a593Smuzhiyun 		LOG_DEV_WARN(dev, "bypass irq handler!\n");
1864*4882a593Smuzhiyun 	}
1865*4882a593Smuzhiyun 
1866*4882a593Smuzhiyun #ifdef CONFIG_ROCKCHIP_RKNPU_DRM_GEM
1867*4882a593Smuzhiyun 	ret = rknpu_drm_probe(rknpu_dev);
1868*4882a593Smuzhiyun 	if (ret) {
1869*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to probe device for rknpu\n");
1870*4882a593Smuzhiyun 		return ret;
1871*4882a593Smuzhiyun 	}
1872*4882a593Smuzhiyun #endif
1873*4882a593Smuzhiyun #ifdef CONFIG_ROCKCHIP_RKNPU_DMA_HEAP
1874*4882a593Smuzhiyun 	rknpu_dev->miscdev.minor = MISC_DYNAMIC_MINOR;
1875*4882a593Smuzhiyun 	rknpu_dev->miscdev.name = "rknpu";
1876*4882a593Smuzhiyun 	rknpu_dev->miscdev.fops = &rknpu_fops;
1877*4882a593Smuzhiyun 
1878*4882a593Smuzhiyun 	ret = misc_register(&rknpu_dev->miscdev);
1879*4882a593Smuzhiyun 	if (ret) {
1880*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "cannot register miscdev (%d)\n", ret);
1881*4882a593Smuzhiyun 		return ret;
1882*4882a593Smuzhiyun 	}
1883*4882a593Smuzhiyun 
1884*4882a593Smuzhiyun 	rknpu_dev->heap = rk_dma_heap_find("rk-dma-heap-cma");
1885*4882a593Smuzhiyun 	if (!rknpu_dev->heap) {
1886*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to find cma heap\n");
1887*4882a593Smuzhiyun 		return -ENOMEM;
1888*4882a593Smuzhiyun 	}
1889*4882a593Smuzhiyun 	rk_dma_heap_set_dev(dev);
1890*4882a593Smuzhiyun 	LOG_DEV_INFO(dev, "Initialized %s: v%d.%d.%d for %s\n", DRIVER_DESC,
1891*4882a593Smuzhiyun 		     DRIVER_MAJOR, DRIVER_MINOR, DRIVER_PATCHLEVEL,
1892*4882a593Smuzhiyun 		     DRIVER_DATE);
1893*4882a593Smuzhiyun #endif
1894*4882a593Smuzhiyun 
1895*4882a593Smuzhiyun #ifdef CONFIG_ROCKCHIP_RKNPU_FENCE
1896*4882a593Smuzhiyun 	ret = rknpu_fence_context_alloc(rknpu_dev);
1897*4882a593Smuzhiyun 	if (ret) {
1898*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev,
1899*4882a593Smuzhiyun 			      "failed to allocate fence context for rknpu\n");
1900*4882a593Smuzhiyun 		goto err_remove_drv;
1901*4882a593Smuzhiyun 	}
1902*4882a593Smuzhiyun #endif
1903*4882a593Smuzhiyun 
1904*4882a593Smuzhiyun 	platform_set_drvdata(pdev, rknpu_dev);
1905*4882a593Smuzhiyun 
1906*4882a593Smuzhiyun 	pm_runtime_enable(dev);
1907*4882a593Smuzhiyun 
1908*4882a593Smuzhiyun 	if (of_count_phandle_with_args(dev->of_node, "power-domains",
1909*4882a593Smuzhiyun 				       "#power-domain-cells") > 1) {
1910*4882a593Smuzhiyun 		virt_dev = dev_pm_domain_attach_by_name(dev, "npu0");
1911*4882a593Smuzhiyun 		if (!IS_ERR(virt_dev))
1912*4882a593Smuzhiyun 			rknpu_dev->genpd_dev_npu0 = virt_dev;
1913*4882a593Smuzhiyun 		virt_dev = dev_pm_domain_attach_by_name(dev, "npu1");
1914*4882a593Smuzhiyun 		if (!IS_ERR(virt_dev))
1915*4882a593Smuzhiyun 			rknpu_dev->genpd_dev_npu1 = virt_dev;
1916*4882a593Smuzhiyun 		virt_dev = dev_pm_domain_attach_by_name(dev, "npu2");
1917*4882a593Smuzhiyun 		if (!IS_ERR(virt_dev))
1918*4882a593Smuzhiyun 			rknpu_dev->genpd_dev_npu2 = virt_dev;
1919*4882a593Smuzhiyun 		rknpu_dev->multiple_domains = true;
1920*4882a593Smuzhiyun 	}
1921*4882a593Smuzhiyun 
1922*4882a593Smuzhiyun 	ret = rknpu_power_on(rknpu_dev);
1923*4882a593Smuzhiyun 	if (ret)
1924*4882a593Smuzhiyun 		goto err_remove_drv;
1925*4882a593Smuzhiyun 
1926*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
1927*4882a593Smuzhiyun #if KERNEL_VERSION(6, 1, 0) > LINUX_VERSION_CODE
1928*4882a593Smuzhiyun 	rknpu_devfreq_init(rknpu_dev);
1929*4882a593Smuzhiyun #endif
1930*4882a593Smuzhiyun #endif
1931*4882a593Smuzhiyun 
1932*4882a593Smuzhiyun 	// set default power put delay to 3s
1933*4882a593Smuzhiyun 	rknpu_dev->power_put_delay = 3000;
1934*4882a593Smuzhiyun 	rknpu_dev->power_off_wq =
1935*4882a593Smuzhiyun 		create_freezable_workqueue("rknpu_power_off_wq");
1936*4882a593Smuzhiyun 	if (!rknpu_dev->power_off_wq) {
1937*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "rknpu couldn't create power_off workqueue");
1938*4882a593Smuzhiyun 		ret = -ENOMEM;
1939*4882a593Smuzhiyun 		goto err_devfreq_remove;
1940*4882a593Smuzhiyun 	}
1941*4882a593Smuzhiyun 	INIT_DEFERRABLE_WORK(&rknpu_dev->power_off_work,
1942*4882a593Smuzhiyun 			     rknpu_power_off_delay_work);
1943*4882a593Smuzhiyun 
1944*4882a593Smuzhiyun 	if (IS_ENABLED(CONFIG_NO_GKI) &&
1945*4882a593Smuzhiyun 	    IS_ENABLED(CONFIG_ROCKCHIP_RKNPU_SRAM) && rknpu_dev->iommu_en) {
1946*4882a593Smuzhiyun 		if (!rknpu_find_sram_resource(rknpu_dev)) {
1947*4882a593Smuzhiyun 			ret = rknpu_mm_create(rknpu_dev->sram_size, PAGE_SIZE,
1948*4882a593Smuzhiyun 					      &rknpu_dev->sram_mm);
1949*4882a593Smuzhiyun 			if (ret != 0)
1950*4882a593Smuzhiyun 				goto err_remove_wq;
1951*4882a593Smuzhiyun 		} else {
1952*4882a593Smuzhiyun 			LOG_DEV_WARN(dev, "could not find sram resource!\n");
1953*4882a593Smuzhiyun 		}
1954*4882a593Smuzhiyun 	}
1955*4882a593Smuzhiyun 
1956*4882a593Smuzhiyun 	if (IS_ENABLED(CONFIG_NO_GKI) && rknpu_dev->iommu_en &&
1957*4882a593Smuzhiyun 	    rknpu_dev->config->nbuf_size > 0)
1958*4882a593Smuzhiyun 		rknpu_find_nbuf_resource(rknpu_dev);
1959*4882a593Smuzhiyun 
1960*4882a593Smuzhiyun 	rknpu_power_off(rknpu_dev);
1961*4882a593Smuzhiyun 	atomic_set(&rknpu_dev->power_refcount, 0);
1962*4882a593Smuzhiyun 	atomic_set(&rknpu_dev->cmdline_power_refcount, 0);
1963*4882a593Smuzhiyun 
1964*4882a593Smuzhiyun 	rknpu_debugger_init(rknpu_dev);
1965*4882a593Smuzhiyun 	rknpu_init_timer(rknpu_dev);
1966*4882a593Smuzhiyun 
1967*4882a593Smuzhiyun 	return 0;
1968*4882a593Smuzhiyun 
1969*4882a593Smuzhiyun err_remove_wq:
1970*4882a593Smuzhiyun 	destroy_workqueue(rknpu_dev->power_off_wq);
1971*4882a593Smuzhiyun 
1972*4882a593Smuzhiyun err_devfreq_remove:
1973*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
1974*4882a593Smuzhiyun 	rknpu_devfreq_remove(rknpu_dev);
1975*4882a593Smuzhiyun #endif
1976*4882a593Smuzhiyun 
1977*4882a593Smuzhiyun err_remove_drv:
1978*4882a593Smuzhiyun #ifdef CONFIG_ROCKCHIP_RKNPU_DRM_GEM
1979*4882a593Smuzhiyun 	rknpu_drm_remove(rknpu_dev);
1980*4882a593Smuzhiyun #endif
1981*4882a593Smuzhiyun #ifdef CONFIG_ROCKCHIP_RKNPU_DMA_HEAP
1982*4882a593Smuzhiyun 	misc_deregister(&(rknpu_dev->miscdev));
1983*4882a593Smuzhiyun #endif
1984*4882a593Smuzhiyun 
1985*4882a593Smuzhiyun 	return ret;
1986*4882a593Smuzhiyun }
1987*4882a593Smuzhiyun 
rknpu_remove(struct platform_device * pdev)1988*4882a593Smuzhiyun static int rknpu_remove(struct platform_device *pdev)
1989*4882a593Smuzhiyun {
1990*4882a593Smuzhiyun 	struct rknpu_device *rknpu_dev = platform_get_drvdata(pdev);
1991*4882a593Smuzhiyun 	int i = 0;
1992*4882a593Smuzhiyun 
1993*4882a593Smuzhiyun 	cancel_delayed_work_sync(&rknpu_dev->power_off_work);
1994*4882a593Smuzhiyun 	destroy_workqueue(rknpu_dev->power_off_wq);
1995*4882a593Smuzhiyun 
1996*4882a593Smuzhiyun 	if (IS_ENABLED(CONFIG_ROCKCHIP_RKNPU_SRAM) && rknpu_dev->sram_mm)
1997*4882a593Smuzhiyun 		rknpu_mm_destroy(rknpu_dev->sram_mm);
1998*4882a593Smuzhiyun 
1999*4882a593Smuzhiyun 	rknpu_debugger_remove(rknpu_dev);
2000*4882a593Smuzhiyun 	rknpu_cancel_timer(rknpu_dev);
2001*4882a593Smuzhiyun 
2002*4882a593Smuzhiyun 	for (i = 0; i < rknpu_dev->config->num_irqs; i++) {
2003*4882a593Smuzhiyun 		WARN_ON(rknpu_dev->subcore_datas[i].job);
2004*4882a593Smuzhiyun 		WARN_ON(!list_empty(&rknpu_dev->subcore_datas[i].todo_list));
2005*4882a593Smuzhiyun 	}
2006*4882a593Smuzhiyun 
2007*4882a593Smuzhiyun #ifdef CONFIG_ROCKCHIP_RKNPU_DRM_GEM
2008*4882a593Smuzhiyun 	rknpu_drm_remove(rknpu_dev);
2009*4882a593Smuzhiyun #endif
2010*4882a593Smuzhiyun #ifdef CONFIG_ROCKCHIP_RKNPU_DMA_HEAP
2011*4882a593Smuzhiyun 	misc_deregister(&(rknpu_dev->miscdev));
2012*4882a593Smuzhiyun #endif
2013*4882a593Smuzhiyun 
2014*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
2015*4882a593Smuzhiyun 	rknpu_devfreq_remove(rknpu_dev);
2016*4882a593Smuzhiyun #endif
2017*4882a593Smuzhiyun 
2018*4882a593Smuzhiyun 	mutex_lock(&rknpu_dev->power_lock);
2019*4882a593Smuzhiyun 	if (atomic_read(&rknpu_dev->power_refcount) > 0)
2020*4882a593Smuzhiyun 		rknpu_power_off(rknpu_dev);
2021*4882a593Smuzhiyun 	mutex_unlock(&rknpu_dev->power_lock);
2022*4882a593Smuzhiyun 
2023*4882a593Smuzhiyun 	if (rknpu_dev->multiple_domains) {
2024*4882a593Smuzhiyun 		if (rknpu_dev->genpd_dev_npu0)
2025*4882a593Smuzhiyun 			dev_pm_domain_detach(rknpu_dev->genpd_dev_npu0, true);
2026*4882a593Smuzhiyun 		if (rknpu_dev->genpd_dev_npu1)
2027*4882a593Smuzhiyun 			dev_pm_domain_detach(rknpu_dev->genpd_dev_npu1, true);
2028*4882a593Smuzhiyun 		if (rknpu_dev->genpd_dev_npu2)
2029*4882a593Smuzhiyun 			dev_pm_domain_detach(rknpu_dev->genpd_dev_npu2, true);
2030*4882a593Smuzhiyun 	}
2031*4882a593Smuzhiyun 
2032*4882a593Smuzhiyun 	pm_runtime_disable(&pdev->dev);
2033*4882a593Smuzhiyun 
2034*4882a593Smuzhiyun 	return 0;
2035*4882a593Smuzhiyun }
2036*4882a593Smuzhiyun 
2037*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
2038*4882a593Smuzhiyun #if KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE &&                          \
2039*4882a593Smuzhiyun 	KERNEL_VERSION(6, 1, 0) > LINUX_VERSION_CODE
rknpu_runtime_suspend(struct device * dev)2040*4882a593Smuzhiyun static int rknpu_runtime_suspend(struct device *dev)
2041*4882a593Smuzhiyun {
2042*4882a593Smuzhiyun 	struct rknpu_device *rknpu_dev = dev_get_drvdata(dev);
2043*4882a593Smuzhiyun 	struct rockchip_opp_info *opp_info = &rknpu_dev->opp_info;
2044*4882a593Smuzhiyun 
2045*4882a593Smuzhiyun 	if (opp_info->scmi_clk) {
2046*4882a593Smuzhiyun 		if (clk_set_rate(opp_info->scmi_clk, POWER_DOWN_FREQ))
2047*4882a593Smuzhiyun 			LOG_DEV_ERROR(dev, "failed to restore clk rate\n");
2048*4882a593Smuzhiyun 	}
2049*4882a593Smuzhiyun 	opp_info->current_rm = UINT_MAX;
2050*4882a593Smuzhiyun 
2051*4882a593Smuzhiyun 	return 0;
2052*4882a593Smuzhiyun }
2053*4882a593Smuzhiyun 
rknpu_runtime_resume(struct device * dev)2054*4882a593Smuzhiyun static int rknpu_runtime_resume(struct device *dev)
2055*4882a593Smuzhiyun {
2056*4882a593Smuzhiyun 	struct rknpu_device *rknpu_dev = dev_get_drvdata(dev);
2057*4882a593Smuzhiyun 	struct rockchip_opp_info *opp_info = &rknpu_dev->opp_info;
2058*4882a593Smuzhiyun 	int ret = 0;
2059*4882a593Smuzhiyun 
2060*4882a593Smuzhiyun 	if (!rknpu_dev->current_freq || !rknpu_dev->current_volt)
2061*4882a593Smuzhiyun 		return 0;
2062*4882a593Smuzhiyun 
2063*4882a593Smuzhiyun 	ret = clk_bulk_prepare_enable(opp_info->num_clks, opp_info->clks);
2064*4882a593Smuzhiyun 	if (ret) {
2065*4882a593Smuzhiyun 		LOG_DEV_ERROR(dev, "failed to enable opp clks\n");
2066*4882a593Smuzhiyun 		return ret;
2067*4882a593Smuzhiyun 	}
2068*4882a593Smuzhiyun 
2069*4882a593Smuzhiyun 	if (opp_info->data && opp_info->data->set_read_margin)
2070*4882a593Smuzhiyun 		opp_info->data->set_read_margin(dev, opp_info,
2071*4882a593Smuzhiyun 						opp_info->target_rm);
2072*4882a593Smuzhiyun 	if (opp_info->scmi_clk) {
2073*4882a593Smuzhiyun 		if (clk_set_rate(opp_info->scmi_clk, rknpu_dev->current_freq))
2074*4882a593Smuzhiyun 			LOG_DEV_ERROR(dev, "failed to set power down rate\n");
2075*4882a593Smuzhiyun 	}
2076*4882a593Smuzhiyun 
2077*4882a593Smuzhiyun 	clk_bulk_disable_unprepare(opp_info->num_clks, opp_info->clks);
2078*4882a593Smuzhiyun 
2079*4882a593Smuzhiyun 	return ret;
2080*4882a593Smuzhiyun }
2081*4882a593Smuzhiyun 
2082*4882a593Smuzhiyun static const struct dev_pm_ops rknpu_pm_ops = {
2083*4882a593Smuzhiyun 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2084*4882a593Smuzhiyun 				pm_runtime_force_resume)
2085*4882a593Smuzhiyun 		SET_RUNTIME_PM_OPS(rknpu_runtime_suspend, rknpu_runtime_resume,
2086*4882a593Smuzhiyun 				   NULL)
2087*4882a593Smuzhiyun };
2088*4882a593Smuzhiyun #endif
2089*4882a593Smuzhiyun #endif
2090*4882a593Smuzhiyun 
2091*4882a593Smuzhiyun static struct platform_driver rknpu_driver = {
2092*4882a593Smuzhiyun 	.probe = rknpu_probe,
2093*4882a593Smuzhiyun 	.remove = rknpu_remove,
2094*4882a593Smuzhiyun 	.driver = {
2095*4882a593Smuzhiyun 		.owner = THIS_MODULE,
2096*4882a593Smuzhiyun 		.name = "RKNPU",
2097*4882a593Smuzhiyun #ifndef FPGA_PLATFORM
2098*4882a593Smuzhiyun #if KERNEL_VERSION(5, 5, 0) < LINUX_VERSION_CODE &&                            \
2099*4882a593Smuzhiyun 	KERNEL_VERSION(6, 1, 0) > LINUX_VERSION_CODE
2100*4882a593Smuzhiyun 		.pm = &rknpu_pm_ops,
2101*4882a593Smuzhiyun #endif
2102*4882a593Smuzhiyun #endif
2103*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(rknpu_of_match),
2104*4882a593Smuzhiyun 	},
2105*4882a593Smuzhiyun };
2106*4882a593Smuzhiyun 
rknpu_init(void)2107*4882a593Smuzhiyun static int rknpu_init(void)
2108*4882a593Smuzhiyun {
2109*4882a593Smuzhiyun 	return platform_driver_register(&rknpu_driver);
2110*4882a593Smuzhiyun }
2111*4882a593Smuzhiyun 
rknpu_exit(void)2112*4882a593Smuzhiyun static void rknpu_exit(void)
2113*4882a593Smuzhiyun {
2114*4882a593Smuzhiyun 	platform_driver_unregister(&rknpu_driver);
2115*4882a593Smuzhiyun }
2116*4882a593Smuzhiyun 
2117*4882a593Smuzhiyun late_initcall(rknpu_init);
2118*4882a593Smuzhiyun module_exit(rknpu_exit);
2119*4882a593Smuzhiyun 
2120*4882a593Smuzhiyun MODULE_DESCRIPTION("RKNPU driver");
2121*4882a593Smuzhiyun MODULE_AUTHOR("Felix Zeng <felix.zeng@rock-chips.com>");
2122*4882a593Smuzhiyun MODULE_ALIAS("rockchip-rknpu");
2123*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
2124*4882a593Smuzhiyun MODULE_VERSION(RKNPU_GET_DRV_VERSION_STRING(DRIVER_MAJOR, DRIVER_MINOR,
2125*4882a593Smuzhiyun 					    DRIVER_PATCHLEVEL));
2126*4882a593Smuzhiyun #if defined(CONFIG_ROCKCHIP_RKNPU_DMA_HEAP) && KERNEL_VERSION(5, 16, 0) < LINUX_VERSION_CODE
2127*4882a593Smuzhiyun MODULE_IMPORT_NS(DMA_BUF);
2128*4882a593Smuzhiyun #endif
2129