xref: /OK3568_Linux_fs/kernel/drivers/rknpu/include/rknpu_ioctl.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) Rockchip Electronics Co.Ltd
4*4882a593Smuzhiyun  * Author: Felix Zeng <felix.zeng@rock-chips.com>
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef __LINUX_RKNPU_IOCTL_H
8*4882a593Smuzhiyun #define __LINUX_RKNPU_IOCTL_H
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/ioctl.h>
11*4882a593Smuzhiyun #include <linux/types.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #if !defined(__KERNEL__)
14*4882a593Smuzhiyun #define __user
15*4882a593Smuzhiyun #endif
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #ifndef __packed
18*4882a593Smuzhiyun #define __packed __attribute__((packed))
19*4882a593Smuzhiyun #endif
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define RKNPU_OFFSET_VERSION 0x0
22*4882a593Smuzhiyun #define RKNPU_OFFSET_VERSION_NUM 0x4
23*4882a593Smuzhiyun #define RKNPU_OFFSET_PC_OP_EN 0x8
24*4882a593Smuzhiyun #define RKNPU_OFFSET_PC_DATA_ADDR 0x10
25*4882a593Smuzhiyun #define RKNPU_OFFSET_PC_DATA_AMOUNT 0x14
26*4882a593Smuzhiyun #define RKNPU_OFFSET_PC_TASK_CONTROL 0x30
27*4882a593Smuzhiyun #define RKNPU_OFFSET_PC_DMA_BASE_ADDR 0x34
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define RKNPU_OFFSET_INT_MASK 0x20
30*4882a593Smuzhiyun #define RKNPU_OFFSET_INT_CLEAR 0x24
31*4882a593Smuzhiyun #define RKNPU_OFFSET_INT_STATUS 0x28
32*4882a593Smuzhiyun #define RKNPU_OFFSET_INT_RAW_STATUS 0x2c
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define RKNPU_OFFSET_CLR_ALL_RW_AMOUNT 0x8010
35*4882a593Smuzhiyun #define RKNPU_OFFSET_DT_WR_AMOUNT 0x8034
36*4882a593Smuzhiyun #define RKNPU_OFFSET_DT_RD_AMOUNT 0x8038
37*4882a593Smuzhiyun #define RKNPU_OFFSET_WT_RD_AMOUNT 0x803c
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define RKNPU_OFFSET_ENABLE_MASK 0xf008
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define RKNPU_INT_CLEAR 0x1ffff
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #define RKNPU_PC_DATA_EXTRA_AMOUNT 4
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #define RKNPU_STR_HELPER(x) #x
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun #define RKNPU_GET_DRV_VERSION_STRING(MAJOR, MINOR, PATCHLEVEL)                 \
48*4882a593Smuzhiyun 	RKNPU_STR_HELPER(MAJOR)                                                \
49*4882a593Smuzhiyun 	"." RKNPU_STR_HELPER(MINOR) "." RKNPU_STR_HELPER(PATCHLEVEL)
50*4882a593Smuzhiyun #define RKNPU_GET_DRV_VERSION_CODE(MAJOR, MINOR, PATCHLEVEL)                   \
51*4882a593Smuzhiyun 	(MAJOR * 10000 + MINOR * 100 + PATCHLEVEL)
52*4882a593Smuzhiyun #define RKNPU_GET_DRV_VERSION_MAJOR(CODE) (CODE / 10000)
53*4882a593Smuzhiyun #define RKNPU_GET_DRV_VERSION_MINOR(CODE) ((CODE % 10000) / 100)
54*4882a593Smuzhiyun #define RKNPU_GET_DRV_VERSION_PATCHLEVEL(CODE) (CODE % 100)
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun /* memory type definitions. */
57*4882a593Smuzhiyun enum e_rknpu_mem_type {
58*4882a593Smuzhiyun 	/* physically continuous memory and used as default. */
59*4882a593Smuzhiyun 	RKNPU_MEM_CONTIGUOUS = 0 << 0,
60*4882a593Smuzhiyun 	/* physically non-continuous memory. */
61*4882a593Smuzhiyun 	RKNPU_MEM_NON_CONTIGUOUS = 1 << 0,
62*4882a593Smuzhiyun 	/* non-cacheable mapping and used as default. */
63*4882a593Smuzhiyun 	RKNPU_MEM_NON_CACHEABLE = 0 << 1,
64*4882a593Smuzhiyun 	/* cacheable mapping. */
65*4882a593Smuzhiyun 	RKNPU_MEM_CACHEABLE = 1 << 1,
66*4882a593Smuzhiyun 	/* write-combine mapping. */
67*4882a593Smuzhiyun 	RKNPU_MEM_WRITE_COMBINE = 1 << 2,
68*4882a593Smuzhiyun 	/* dma attr kernel mapping */
69*4882a593Smuzhiyun 	RKNPU_MEM_KERNEL_MAPPING = 1 << 3,
70*4882a593Smuzhiyun 	/* iommu mapping */
71*4882a593Smuzhiyun 	RKNPU_MEM_IOMMU = 1 << 4,
72*4882a593Smuzhiyun 	/* zero mapping */
73*4882a593Smuzhiyun 	RKNPU_MEM_ZEROING = 1 << 5,
74*4882a593Smuzhiyun 	/* allocate secure buffer */
75*4882a593Smuzhiyun 	RKNPU_MEM_SECURE = 1 << 6,
76*4882a593Smuzhiyun 	/* allocate from dma32 zone */
77*4882a593Smuzhiyun 	RKNPU_MEM_DMA32 = 1 << 7,
78*4882a593Smuzhiyun 	/* request SRAM */
79*4882a593Smuzhiyun 	RKNPU_MEM_TRY_ALLOC_SRAM = 1 << 8,
80*4882a593Smuzhiyun 	/* request NBUF */
81*4882a593Smuzhiyun 	RKNPU_MEM_TRY_ALLOC_NBUF = 1 << 9,
82*4882a593Smuzhiyun 	RKNPU_MEM_MASK = RKNPU_MEM_NON_CONTIGUOUS | RKNPU_MEM_CACHEABLE |
83*4882a593Smuzhiyun 			 RKNPU_MEM_WRITE_COMBINE | RKNPU_MEM_KERNEL_MAPPING |
84*4882a593Smuzhiyun 			 RKNPU_MEM_IOMMU | RKNPU_MEM_ZEROING |
85*4882a593Smuzhiyun 			 RKNPU_MEM_SECURE | RKNPU_MEM_DMA32 |
86*4882a593Smuzhiyun 			 RKNPU_MEM_TRY_ALLOC_SRAM | RKNPU_MEM_TRY_ALLOC_NBUF
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun /* sync mode definitions. */
90*4882a593Smuzhiyun enum e_rknpu_mem_sync_mode {
91*4882a593Smuzhiyun 	RKNPU_MEM_SYNC_TO_DEVICE = 1 << 0,
92*4882a593Smuzhiyun 	RKNPU_MEM_SYNC_FROM_DEVICE = 1 << 1,
93*4882a593Smuzhiyun 	RKNPU_MEM_SYNC_MASK =
94*4882a593Smuzhiyun 		RKNPU_MEM_SYNC_TO_DEVICE | RKNPU_MEM_SYNC_FROM_DEVICE
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun /* job mode definitions. */
98*4882a593Smuzhiyun enum e_rknpu_job_mode {
99*4882a593Smuzhiyun 	RKNPU_JOB_SLAVE = 0 << 0,
100*4882a593Smuzhiyun 	RKNPU_JOB_PC = 1 << 0,
101*4882a593Smuzhiyun 	RKNPU_JOB_BLOCK = 0 << 1,
102*4882a593Smuzhiyun 	RKNPU_JOB_NONBLOCK = 1 << 1,
103*4882a593Smuzhiyun 	RKNPU_JOB_PINGPONG = 1 << 2,
104*4882a593Smuzhiyun 	RKNPU_JOB_FENCE_IN = 1 << 3,
105*4882a593Smuzhiyun 	RKNPU_JOB_FENCE_OUT = 1 << 4,
106*4882a593Smuzhiyun 	RKNPU_JOB_MASK = RKNPU_JOB_PC | RKNPU_JOB_NONBLOCK |
107*4882a593Smuzhiyun 			 RKNPU_JOB_PINGPONG | RKNPU_JOB_FENCE_IN |
108*4882a593Smuzhiyun 			 RKNPU_JOB_FENCE_OUT
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun /* action definitions */
112*4882a593Smuzhiyun enum e_rknpu_action {
113*4882a593Smuzhiyun 	RKNPU_GET_HW_VERSION = 0,
114*4882a593Smuzhiyun 	RKNPU_GET_DRV_VERSION = 1,
115*4882a593Smuzhiyun 	RKNPU_GET_FREQ = 2,
116*4882a593Smuzhiyun 	RKNPU_SET_FREQ = 3,
117*4882a593Smuzhiyun 	RKNPU_GET_VOLT = 4,
118*4882a593Smuzhiyun 	RKNPU_SET_VOLT = 5,
119*4882a593Smuzhiyun 	RKNPU_ACT_RESET = 6,
120*4882a593Smuzhiyun 	RKNPU_GET_BW_PRIORITY = 7,
121*4882a593Smuzhiyun 	RKNPU_SET_BW_PRIORITY = 8,
122*4882a593Smuzhiyun 	RKNPU_GET_BW_EXPECT = 9,
123*4882a593Smuzhiyun 	RKNPU_SET_BW_EXPECT = 10,
124*4882a593Smuzhiyun 	RKNPU_GET_BW_TW = 11,
125*4882a593Smuzhiyun 	RKNPU_SET_BW_TW = 12,
126*4882a593Smuzhiyun 	RKNPU_ACT_CLR_TOTAL_RW_AMOUNT = 13,
127*4882a593Smuzhiyun 	RKNPU_GET_DT_WR_AMOUNT = 14,
128*4882a593Smuzhiyun 	RKNPU_GET_DT_RD_AMOUNT = 15,
129*4882a593Smuzhiyun 	RKNPU_GET_WT_RD_AMOUNT = 16,
130*4882a593Smuzhiyun 	RKNPU_GET_TOTAL_RW_AMOUNT = 17,
131*4882a593Smuzhiyun 	RKNPU_GET_IOMMU_EN = 18,
132*4882a593Smuzhiyun 	RKNPU_SET_PROC_NICE = 19,
133*4882a593Smuzhiyun 	RKNPU_POWER_ON = 20,
134*4882a593Smuzhiyun 	RKNPU_POWER_OFF = 21,
135*4882a593Smuzhiyun 	RKNPU_GET_TOTAL_SRAM_SIZE = 22,
136*4882a593Smuzhiyun 	RKNPU_GET_FREE_SRAM_SIZE = 23,
137*4882a593Smuzhiyun };
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun /**
140*4882a593Smuzhiyun  * User-desired buffer creation information structure.
141*4882a593Smuzhiyun  *
142*4882a593Smuzhiyun  * @handle: The handle of the created GEM object.
143*4882a593Smuzhiyun  * @flags: user request for setting memory type or cache attributes.
144*4882a593Smuzhiyun  * @size: user-desired memory allocation size.
145*4882a593Smuzhiyun  *	- this size value would be page-aligned internally.
146*4882a593Smuzhiyun  * @obj_addr: address of RKNPU memory object.
147*4882a593Smuzhiyun  * @dma_addr: dma address that access by rknpu.
148*4882a593Smuzhiyun  * @sram_size: user-desired sram memory allocation size.
149*4882a593Smuzhiyun  *  - this size value would be page-aligned internally.
150*4882a593Smuzhiyun  */
151*4882a593Smuzhiyun struct rknpu_mem_create {
152*4882a593Smuzhiyun 	__u32 handle;
153*4882a593Smuzhiyun 	__u32 flags;
154*4882a593Smuzhiyun 	__u64 size;
155*4882a593Smuzhiyun 	__u64 obj_addr;
156*4882a593Smuzhiyun 	__u64 dma_addr;
157*4882a593Smuzhiyun 	__u64 sram_size;
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun /**
161*4882a593Smuzhiyun  * A structure for getting a fake-offset that can be used with mmap.
162*4882a593Smuzhiyun  *
163*4882a593Smuzhiyun  * @handle: handle of gem object.
164*4882a593Smuzhiyun  * @reserved: just padding to be 64-bit aligned.
165*4882a593Smuzhiyun  * @offset: a fake-offset of gem object.
166*4882a593Smuzhiyun  */
167*4882a593Smuzhiyun struct rknpu_mem_map {
168*4882a593Smuzhiyun 	__u32 handle;
169*4882a593Smuzhiyun 	__u32 reserved;
170*4882a593Smuzhiyun 	__u64 offset;
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun /**
174*4882a593Smuzhiyun  * For destroying DMA buffer
175*4882a593Smuzhiyun  *
176*4882a593Smuzhiyun  * @handle:	handle of the buffer.
177*4882a593Smuzhiyun  * @reserved: reserved for padding.
178*4882a593Smuzhiyun  * @obj_addr: rknpu_mem_object addr.
179*4882a593Smuzhiyun  */
180*4882a593Smuzhiyun struct rknpu_mem_destroy {
181*4882a593Smuzhiyun 	__u32 handle;
182*4882a593Smuzhiyun 	__u32 reserved;
183*4882a593Smuzhiyun 	__u64 obj_addr;
184*4882a593Smuzhiyun };
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun /**
187*4882a593Smuzhiyun  * For synchronizing DMA buffer
188*4882a593Smuzhiyun  *
189*4882a593Smuzhiyun  * @flags: user request for setting memory type or cache attributes.
190*4882a593Smuzhiyun  * @reserved: reserved for padding.
191*4882a593Smuzhiyun  * @obj_addr: address of RKNPU memory object.
192*4882a593Smuzhiyun  * @offset: offset in bytes from start address of buffer.
193*4882a593Smuzhiyun  * @size: size of memory region.
194*4882a593Smuzhiyun  *
195*4882a593Smuzhiyun  */
196*4882a593Smuzhiyun struct rknpu_mem_sync {
197*4882a593Smuzhiyun 	__u32 flags;
198*4882a593Smuzhiyun 	__u32 reserved;
199*4882a593Smuzhiyun 	__u64 obj_addr;
200*4882a593Smuzhiyun 	__u64 offset;
201*4882a593Smuzhiyun 	__u64 size;
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun /**
205*4882a593Smuzhiyun  * struct rknpu_task structure for task information
206*4882a593Smuzhiyun  *
207*4882a593Smuzhiyun  * @flags: flags for task
208*4882a593Smuzhiyun  * @op_idx: operator index
209*4882a593Smuzhiyun  * @enable_mask: enable mask
210*4882a593Smuzhiyun  * @int_mask: interrupt mask
211*4882a593Smuzhiyun  * @int_clear: interrupt clear
212*4882a593Smuzhiyun  * @int_status: interrupt status
213*4882a593Smuzhiyun  * @regcfg_amount: register config number
214*4882a593Smuzhiyun  * @regcfg_offset: offset for register config
215*4882a593Smuzhiyun  * @regcmd_addr: address for register command
216*4882a593Smuzhiyun  *
217*4882a593Smuzhiyun  */
218*4882a593Smuzhiyun struct rknpu_task {
219*4882a593Smuzhiyun 	__u32 flags;
220*4882a593Smuzhiyun 	__u32 op_idx;
221*4882a593Smuzhiyun 	__u32 enable_mask;
222*4882a593Smuzhiyun 	__u32 int_mask;
223*4882a593Smuzhiyun 	__u32 int_clear;
224*4882a593Smuzhiyun 	__u32 int_status;
225*4882a593Smuzhiyun 	__u32 regcfg_amount;
226*4882a593Smuzhiyun 	__u32 regcfg_offset;
227*4882a593Smuzhiyun 	__u64 regcmd_addr;
228*4882a593Smuzhiyun } __packed;
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun /**
231*4882a593Smuzhiyun  * struct rknpu_subcore_task structure for subcore task index
232*4882a593Smuzhiyun  *
233*4882a593Smuzhiyun  * @task_start: task start index
234*4882a593Smuzhiyun  * @task_number: task number
235*4882a593Smuzhiyun  *
236*4882a593Smuzhiyun  */
237*4882a593Smuzhiyun struct rknpu_subcore_task {
238*4882a593Smuzhiyun 	__u32 task_start;
239*4882a593Smuzhiyun 	__u32 task_number;
240*4882a593Smuzhiyun };
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun /**
243*4882a593Smuzhiyun  * struct rknpu_submit structure for job submit
244*4882a593Smuzhiyun  *
245*4882a593Smuzhiyun  * @flags: flags for job submit
246*4882a593Smuzhiyun  * @timeout: submit timeout
247*4882a593Smuzhiyun  * @task_start: task start index
248*4882a593Smuzhiyun  * @task_number: task number
249*4882a593Smuzhiyun  * @task_counter: task counter
250*4882a593Smuzhiyun  * @priority: submit priority
251*4882a593Smuzhiyun  * @task_obj_addr: address of task object
252*4882a593Smuzhiyun  * @regcfg_obj_addr: address of register config object
253*4882a593Smuzhiyun  * @task_base_addr: task base address
254*4882a593Smuzhiyun  * @user_data: (optional) user data
255*4882a593Smuzhiyun  * @core_mask: core mask of rknpu
256*4882a593Smuzhiyun  * @fence_fd: dma fence fd
257*4882a593Smuzhiyun  * @subcore_task: subcore task
258*4882a593Smuzhiyun  *
259*4882a593Smuzhiyun  */
260*4882a593Smuzhiyun struct rknpu_submit {
261*4882a593Smuzhiyun 	__u32 flags;
262*4882a593Smuzhiyun 	__u32 timeout;
263*4882a593Smuzhiyun 	__u32 task_start;
264*4882a593Smuzhiyun 	__u32 task_number;
265*4882a593Smuzhiyun 	__u32 task_counter;
266*4882a593Smuzhiyun 	__s32 priority;
267*4882a593Smuzhiyun 	__u64 task_obj_addr;
268*4882a593Smuzhiyun 	__u64 regcfg_obj_addr;
269*4882a593Smuzhiyun 	__u64 task_base_addr;
270*4882a593Smuzhiyun 	__u64 user_data;
271*4882a593Smuzhiyun 	__u32 core_mask;
272*4882a593Smuzhiyun 	__s32 fence_fd;
273*4882a593Smuzhiyun 	struct rknpu_subcore_task subcore_task[5];
274*4882a593Smuzhiyun };
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun /**
277*4882a593Smuzhiyun  * struct rknpu_task structure for action (GET, SET or ACT)
278*4882a593Smuzhiyun  *
279*4882a593Smuzhiyun  * @flags: flags for action
280*4882a593Smuzhiyun  * @value: GET or SET value
281*4882a593Smuzhiyun  *
282*4882a593Smuzhiyun  */
283*4882a593Smuzhiyun struct rknpu_action {
284*4882a593Smuzhiyun 	__u32 flags;
285*4882a593Smuzhiyun 	__u32 value;
286*4882a593Smuzhiyun };
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun #define RKNPU_ACTION 0x00
289*4882a593Smuzhiyun #define RKNPU_SUBMIT 0x01
290*4882a593Smuzhiyun #define RKNPU_MEM_CREATE 0x02
291*4882a593Smuzhiyun #define RKNPU_MEM_MAP 0x03
292*4882a593Smuzhiyun #define RKNPU_MEM_DESTROY 0x04
293*4882a593Smuzhiyun #define RKNPU_MEM_SYNC 0x05
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun #define RKNPU_IOC_MAGIC 'r'
296*4882a593Smuzhiyun #define RKNPU_IOW(nr, type) _IOW(RKNPU_IOC_MAGIC, nr, type)
297*4882a593Smuzhiyun #define RKNPU_IOR(nr, type) _IOR(RKNPU_IOC_MAGIC, nr, type)
298*4882a593Smuzhiyun #define RKNPU_IOWR(nr, type) _IOWR(RKNPU_IOC_MAGIC, nr, type)
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun #include <drm/drm.h>
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun #define DRM_IOCTL_RKNPU_ACTION                                                 \
303*4882a593Smuzhiyun 	DRM_IOWR(DRM_COMMAND_BASE + RKNPU_ACTION, struct rknpu_action)
304*4882a593Smuzhiyun #define DRM_IOCTL_RKNPU_SUBMIT                                                 \
305*4882a593Smuzhiyun 	DRM_IOWR(DRM_COMMAND_BASE + RKNPU_SUBMIT, struct rknpu_submit)
306*4882a593Smuzhiyun #define DRM_IOCTL_RKNPU_MEM_CREATE                                             \
307*4882a593Smuzhiyun 	DRM_IOWR(DRM_COMMAND_BASE + RKNPU_MEM_CREATE, struct rknpu_mem_create)
308*4882a593Smuzhiyun #define DRM_IOCTL_RKNPU_MEM_MAP                                                \
309*4882a593Smuzhiyun 	DRM_IOWR(DRM_COMMAND_BASE + RKNPU_MEM_MAP, struct rknpu_mem_map)
310*4882a593Smuzhiyun #define DRM_IOCTL_RKNPU_MEM_DESTROY                                            \
311*4882a593Smuzhiyun 	DRM_IOWR(DRM_COMMAND_BASE + RKNPU_MEM_DESTROY, struct rknpu_mem_destroy)
312*4882a593Smuzhiyun #define DRM_IOCTL_RKNPU_MEM_SYNC                                               \
313*4882a593Smuzhiyun 	DRM_IOWR(DRM_COMMAND_BASE + RKNPU_MEM_SYNC, struct rknpu_mem_sync)
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun #define IOCTL_RKNPU_ACTION RKNPU_IOWR(RKNPU_ACTION, struct rknpu_action)
316*4882a593Smuzhiyun #define IOCTL_RKNPU_SUBMIT RKNPU_IOWR(RKNPU_SUBMIT, struct rknpu_submit)
317*4882a593Smuzhiyun #define IOCTL_RKNPU_MEM_CREATE                                                 \
318*4882a593Smuzhiyun 	RKNPU_IOWR(RKNPU_MEM_CREATE, struct rknpu_mem_create)
319*4882a593Smuzhiyun #define IOCTL_RKNPU_MEM_MAP RKNPU_IOWR(RKNPU_MEM_MAP, struct rknpu_mem_map)
320*4882a593Smuzhiyun #define IOCTL_RKNPU_MEM_DESTROY                                                \
321*4882a593Smuzhiyun 	RKNPU_IOWR(RKNPU_MEM_DESTROY, struct rknpu_mem_destroy)
322*4882a593Smuzhiyun #define IOCTL_RKNPU_MEM_SYNC RKNPU_IOWR(RKNPU_MEM_SYNC, struct rknpu_mem_sync)
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun #endif
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