1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #include <linux/kernel.h>
6*4882a593Smuzhiyun #include <linux/slab.h>
7*4882a593Smuzhiyun #include <crypto/skcipher.h>
8*4882a593Smuzhiyun #include <linux/scatterlist.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "sfc_nor.h"
11*4882a593Smuzhiyun #include "rkflash_api.h"
12*4882a593Smuzhiyun #include "rkflash_debug.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define VENDOR_PART_NUM 4
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define FLASH_VENDOR_PART_START 8
17*4882a593Smuzhiyun #define FLASH_VENDOR_PART_SIZE 8
18*4882a593Smuzhiyun #define FLASH_VENDOR_ITEM_NUM 62
19*4882a593Smuzhiyun #define FLASH_VENDOR_PART_END \
20*4882a593Smuzhiyun (FLASH_VENDOR_PART_START +\
21*4882a593Smuzhiyun FLASH_VENDOR_PART_SIZE * VENDOR_PART_NUM - 1)
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define IDB_ALIGN_64 128 /* 64 KB */
24*4882a593Smuzhiyun #define IDB_ALIGN_32 64 /* 32 KB */
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun struct SFNOR_DEV *sfnor_dev;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* SFNOR_DEV sfnor_dev is in the sfc_nor.h */
spi_nor_init(void __iomem * reg_addr)29*4882a593Smuzhiyun static int spi_nor_init(void __iomem *reg_addr)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun int ret;
32*4882a593Smuzhiyun struct id_block_tag *idb_tag;
33*4882a593Smuzhiyun struct snor_info_packet *packet;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun if (!sfnor_dev)
36*4882a593Smuzhiyun sfnor_dev = kzalloc(sizeof(*sfnor_dev), GFP_KERNEL);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun if (!sfnor_dev)
39*4882a593Smuzhiyun return -ENOMEM;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun sfc_init(reg_addr);
42*4882a593Smuzhiyun ret = snor_init(sfnor_dev);
43*4882a593Smuzhiyun if (ret == SFC_OK && sfnor_dev->read_lines == DATA_LINES_X1) {
44*4882a593Smuzhiyun struct crypto_sync_skcipher *tfm_arc4;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun tfm_arc4 = crypto_alloc_sync_skcipher("ecb(arc4)", 0, 0);
47*4882a593Smuzhiyun if (IS_ERR(tfm_arc4)) {
48*4882a593Smuzhiyun crypto_free_sync_skcipher(tfm_arc4);
49*4882a593Smuzhiyun return SFC_OK;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun idb_tag = kzalloc(NOR_SECS_PAGE * 512, GFP_KERNEL);
53*4882a593Smuzhiyun if (!idb_tag) {
54*4882a593Smuzhiyun crypto_free_sync_skcipher(tfm_arc4);
55*4882a593Smuzhiyun return SFC_OK;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun if (sfc_get_version() >= SFC_VER_4)
59*4882a593Smuzhiyun snor_read(sfnor_dev, IDB_ALIGN_32, NOR_SECS_PAGE,
60*4882a593Smuzhiyun idb_tag);
61*4882a593Smuzhiyun else
62*4882a593Smuzhiyun snor_read(sfnor_dev, IDB_ALIGN_64, NOR_SECS_PAGE,
63*4882a593Smuzhiyun idb_tag);
64*4882a593Smuzhiyun packet = (struct snor_info_packet *)&idb_tag->dev_param[0];
65*4882a593Smuzhiyun if (idb_tag->id == IDB_BLOCK_TAG_ID) {
66*4882a593Smuzhiyun SYNC_SKCIPHER_REQUEST_ON_STACK(req, tfm_arc4);
67*4882a593Smuzhiyun u8 key[16] = {124, 78, 3, 4, 85, 5, 9, 7,
68*4882a593Smuzhiyun 45, 44, 123, 56, 23, 13, 23, 17};
69*4882a593Smuzhiyun struct scatterlist sg;
70*4882a593Smuzhiyun u32 len = sizeof(struct id_block_tag);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun crypto_sync_skcipher_setkey(tfm_arc4, key, 16);
73*4882a593Smuzhiyun sg_init_one(&sg, idb_tag, len + 4);
74*4882a593Smuzhiyun skcipher_request_set_sync_tfm(req, tfm_arc4);
75*4882a593Smuzhiyun skcipher_request_set_callback(req, 0, NULL, NULL);
76*4882a593Smuzhiyun skcipher_request_set_crypt(req, &sg, &sg, len + 4,
77*4882a593Smuzhiyun NULL);
78*4882a593Smuzhiyun ret = crypto_skcipher_encrypt(req);
79*4882a593Smuzhiyun if (!ret) {
80*4882a593Smuzhiyun snor_reinit_from_table_packet(sfnor_dev,
81*4882a593Smuzhiyun packet);
82*4882a593Smuzhiyun rkflash_print_error("snor reinit, ret= %d\n", ret);
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun crypto_free_sync_skcipher(tfm_arc4);
86*4882a593Smuzhiyun kfree(idb_tag);
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun return ret;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
snor_read_lba(u32 sec,u32 n_sec,void * p_data)92*4882a593Smuzhiyun static int snor_read_lba(u32 sec, u32 n_sec, void *p_data)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun int ret = 0;
95*4882a593Smuzhiyun u32 count, offset;
96*4882a593Smuzhiyun char *buf;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun if (sec + n_sec - 1 < FLASH_VENDOR_PART_START ||
99*4882a593Smuzhiyun sec > FLASH_VENDOR_PART_END) {
100*4882a593Smuzhiyun ret = snor_read(sfnor_dev, sec, n_sec, p_data);
101*4882a593Smuzhiyun } else {
102*4882a593Smuzhiyun memset(p_data, 0, 512 * n_sec);
103*4882a593Smuzhiyun if (sec < FLASH_VENDOR_PART_START) {
104*4882a593Smuzhiyun count = FLASH_VENDOR_PART_START - sec;
105*4882a593Smuzhiyun buf = p_data;
106*4882a593Smuzhiyun ret = snor_read(sfnor_dev, sec, count, buf);
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun if ((sec + n_sec - 1) > FLASH_VENDOR_PART_END) {
109*4882a593Smuzhiyun count = sec + n_sec - 1 - FLASH_VENDOR_PART_END;
110*4882a593Smuzhiyun offset = FLASH_VENDOR_PART_END - sec + 1;
111*4882a593Smuzhiyun buf = p_data + offset * 512;
112*4882a593Smuzhiyun ret = snor_read(sfnor_dev,
113*4882a593Smuzhiyun FLASH_VENDOR_PART_END + 1,
114*4882a593Smuzhiyun count, buf);
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun return (u32)ret == n_sec ? 0 : ret;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
snor_write_lba(u32 sec,u32 n_sec,void * p_data)121*4882a593Smuzhiyun static int snor_write_lba(u32 sec, u32 n_sec, void *p_data)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun int ret = 0;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun ret = snor_write(sfnor_dev, sec, n_sec, p_data);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun return (u32)ret == n_sec ? 0 : ret;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
snor_vendor_read(u32 sec,u32 n_sec,void * p_data)130*4882a593Smuzhiyun static int snor_vendor_read(u32 sec, u32 n_sec, void *p_data)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun int ret = 0;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun ret = snor_read(sfnor_dev, sec, n_sec, p_data);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun return (u32)ret == n_sec ? 0 : ret;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
snor_vendor_write(u32 sec,u32 n_sec,void * p_data)139*4882a593Smuzhiyun static int snor_vendor_write(u32 sec, u32 n_sec, void *p_data)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun int ret = 0;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun ret = snor_write(sfnor_dev, sec, n_sec, p_data);
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun return (u32)ret == n_sec ? 0 : ret;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
snor_gc(void)148*4882a593Smuzhiyun static int snor_gc(void)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun return 0;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
snor_capacity(void)153*4882a593Smuzhiyun static unsigned int snor_capacity(void)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun return snor_get_capacity(sfnor_dev);
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
snor_deinit(void)158*4882a593Smuzhiyun static void snor_deinit(void)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun snor_disable_QE(sfnor_dev);
161*4882a593Smuzhiyun snor_reset_device();
162*4882a593Smuzhiyun kfree(sfnor_dev);
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
snor_resume(void __iomem * reg_addr)165*4882a593Smuzhiyun static int snor_resume(void __iomem *reg_addr)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun return spi_nor_init(reg_addr);
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun const struct flash_boot_ops sfc_nor_ops = {
171*4882a593Smuzhiyun spi_nor_init,
172*4882a593Smuzhiyun snor_read_lba,
173*4882a593Smuzhiyun snor_write_lba,
174*4882a593Smuzhiyun snor_capacity,
175*4882a593Smuzhiyun snor_deinit,
176*4882a593Smuzhiyun snor_resume,
177*4882a593Smuzhiyun snor_vendor_read,
178*4882a593Smuzhiyun snor_vendor_write,
179*4882a593Smuzhiyun snor_gc,
180*4882a593Smuzhiyun NULL,
181*4882a593Smuzhiyun };
182