1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */ 4 5 #ifndef _SFC_H 6 #define _SFC_H 7 8 #define SFC_VER_3 0x3 9 #define SFC_VER_4 0x4 10 #define SFC_VER_5 0x5 11 #define SFC_VER_6 0x6 12 #define SFC_VER_8 0x8 13 14 #define SFC_EN_INT (0) /* enable interrupt */ 15 #define SFC_EN_DMA (1) /* enable dma */ 16 #define SFC_FIFO_DEPTH (0x10) /* 16 words */ 17 18 /* FIFO watermark */ 19 #define SFC_RX_WMARK (SFC_FIFO_DEPTH) /* RX watermark level */ 20 #define SFC_TX_WMARK (SFC_FIFO_DEPTH) /* TX watermark level */ 21 #define SFC_RX_WMARK_SHIFT (8) 22 #define SFC_TX_WMARK_SHIFT (0) 23 24 /* return value */ 25 #define SFC_OK (0) 26 #define SFC_ERROR (-1) 27 #define SFC_PARAM_ERR (-2) 28 #define SFC_TX_TIMEOUT (-3) 29 #define SFC_RX_TIMEOUT (-4) 30 #define SFC_WAIT_TIMEOUT (-5) 31 #define SFC_BUSY_TIMEOUT (-6) 32 #define SFC_ECC_FAIL (-7) 33 #define SFC_PROG_FAIL (-8) 34 #define SFC_ERASE_FAIL (-9) 35 36 /* SFC_CMD Register */ 37 #define SFC_ADDR_0BITS (0) 38 #define SFC_ADDR_24BITS (1) 39 #define SFC_ADDR_32BITS (2) 40 #define SFC_ADDR_XBITS (3) 41 42 #define SFC_WRITE (1) 43 #define SFC_READ (0) 44 45 /* SFC_CTRL Register */ 46 #define SFC_1BITS_LINE (0) 47 #define SFC_2BITS_LINE (1) 48 #define SFC_4BITS_LINE (2) 49 50 #define SFC_ENABLE_DMA BIT(14) 51 #define sfc_delay(us) udelay(us) 52 53 #define DMA_INT BIT(7) /* dma interrupt */ 54 #define NSPIERR_INT BIT(6) /* Nspi error interrupt */ 55 #define AHBERR_INT BIT(5) /* Ahb bus error interrupt */ 56 #define FINISH_INT BIT(4) /* Transfer finish interrupt */ 57 #define TXEMPTY_INT BIT(3) /* Tx fifo empty interrupt */ 58 #define TXOF_INT BIT(2) /* Tx fifo overflow interrupt */ 59 #define RXUF_INT BIT(1) /* Rx fifo underflow interrupt */ 60 #define RXFULL_INT BIT(0) /* Rx fifo full interrupt */ 61 62 /* SFC_FSR Register*/ 63 #define SFC_RXFULL BIT(3) /* rx fifo full */ 64 #define SFC_RXEMPTY BIT(2) /* rx fifo empty */ 65 #define SFC_TXEMPTY BIT(1) /* tx fifo empty */ 66 #define SFC_TXFULL BIT(0) /* tx fifo full */ 67 68 /* SFC_RCVR Register */ 69 #define SFC_RESET BIT(0) /* controller reset */ 70 71 /* SFC_DLL_CTRL Register */ 72 #define SCLK_SMP_SEL_EN BIT(15) /* SCLK Sampling Selection */ 73 #define SCLK_SMP_SEL_MAX_V4 0xFF 74 #define SCLK_SMP_SEL_MAX_V5 0x1FF 75 76 #define SFC_DLL_TRANING_STEP 10 /* Training step */ 77 #define SFC_DLL_TRANING_VALID_WINDOW 80 /* Valid DLL winbow */ 78 79 /* SFC_SR Register */ 80 /* sfc busy flag. When busy, don't try to set the control register */ 81 #define SFC_BUSY BIT(0) 82 83 /* SFC_DMA_TRIGGER Register */ 84 /* Dma start trigger signal. Auto cleared after write */ 85 #define SFC_DMA_START BIT(0) 86 87 #define SFC_CTRL 0x00 88 #define SFC_IMR 0x04 89 #define SFC_ICLR 0x08 90 #define SFC_FTLR 0x0C 91 #define SFC_RCVR 0x10 92 #define SFC_AX 0x14 93 #define SFC_ABIT 0x18 94 #define SFC_MASKISR 0x1C 95 #define SFC_FSR 0x20 96 #define SFC_SR 0x24 97 #define SFC_RAWISR 0x28 98 #define SFC_VER 0x2C 99 #define SFC_QOP 0x30 100 #define SFC_DLL_CTRL0 0x3C 101 #define SFC_DMA_TRIGGER 0x80 102 #define SFC_DMA_ADDR 0x84 103 #define SFC_LEN_CTRL 0x88 104 #define SFC_LEN_EXT 0x8C 105 #define SFC_CMD 0x100 106 #define SFC_ADDR 0x104 107 #define SFC_DATA 0x108 108 109 union SFCFSR_DATA { 110 u32 d32; 111 struct { 112 unsigned txempty : 1; 113 unsigned txfull : 1; 114 unsigned rxempty : 1; 115 unsigned rxfull : 1; 116 unsigned reserved7_4 : 4; 117 unsigned txlevel : 5; 118 unsigned reserved15_13 : 3; 119 unsigned rxlevel : 5; 120 unsigned reserved31_21 : 11; 121 } b; 122 }; 123 124 /* Manufactory ID */ 125 #define MID_WINBOND 0xEF 126 #define MID_GIGADEV 0xC8 127 #define MID_MICRON 0x2C 128 #define MID_MACRONIX 0xC2 129 #define MID_SPANSION 0x01 130 #define MID_EON 0x1C 131 #define MID_ST 0x20 132 #define MID_XTX 0x0B 133 #define MID_PUYA 0x85 134 #define MID_XMC 0x20 135 #define MID_DOSILICON 0xF8 136 #define MID_ZBIT 0x5E 137 138 /*------------------------------ Global Typedefs -----------------------------*/ 139 enum SFC_DATA_LINES { 140 DATA_LINES_X1 = 0, 141 DATA_LINES_X2, 142 DATA_LINES_X4 143 }; 144 145 union SFCCTRL_DATA { 146 /* raw register data */ 147 u32 d32; 148 /* register bits */ 149 struct { 150 /* spi mode select */ 151 unsigned mode : 1; 152 /* 153 * Shift in phase selection 154 * 0: shift in the flash data at posedge sclk_out 155 * 1: shift in the flash data at negedge sclk_out 156 */ 157 unsigned sps : 1; 158 unsigned reserved3_2 : 2; 159 /* sclk_idle_level_cycles */ 160 unsigned scic : 4; 161 /* Cmd bits number */ 162 unsigned cmdlines : 2; 163 /* Address bits number */ 164 unsigned addrlines : 2; 165 /* Data bits number */ 166 unsigned datalines : 2; 167 /* this bit is not exit in regiseter, just use for code param */ 168 unsigned enbledma : 1; 169 unsigned reserved15 : 1; 170 unsigned addrbits : 5; 171 unsigned reserved31_21 : 11; 172 } b; 173 }; 174 175 union SFCCMD_DATA { 176 /* raw register data */ 177 u32 d32; 178 /* register bits */ 179 struct { 180 /* Command that will send to Serial Flash */ 181 unsigned cmd : 8; 182 /* Dummy bits number */ 183 unsigned dummybits : 4; 184 /* 0: read, 1: write */ 185 unsigned rw : 1; 186 /* Continuous read mode */ 187 unsigned readmode : 1; 188 /* Address bits number */ 189 unsigned addrbits : 2; 190 /* Transferred bytes number */ 191 unsigned datasize : 14; 192 /* Chip select */ 193 unsigned cs : 2; 194 } b; 195 }; 196 197 struct rk_sfc_op { 198 union SFCCMD_DATA sfcmd; 199 union SFCCTRL_DATA sfctrl; 200 }; 201 202 #define IDB_BLOCK_TAG_ID 0xFCDC8C3B 203 204 struct id_block_tag { 205 u32 id; 206 u32 version; 207 u32 flags; 208 u16 boot_img_offset; 209 u8 reserved1[10]; 210 u32 dev_param[8]; 211 u8 reserved2[506 - 56]; 212 u16 data_img_len; 213 u16 boot_img_len; 214 u8 reserved3[512 - 510]; 215 } __packed; 216 217 int sfc_init(void __iomem *reg_addr); 218 int sfc_request(struct rk_sfc_op *op, u32 addr, void *data, u32 size); 219 u16 sfc_get_version(void); 220 void sfc_clean_irq(void); 221 u32 sfc_get_max_iosize(void); 222 void sfc_set_delay_lines(u16 cells); 223 void sfc_handle_irq(void); 224 unsigned long rksfc_dma_map_single(unsigned long ptr, int size, int dir); 225 void rksfc_dma_unmap_single(unsigned long ptr, int size, int dir); 226 void rksfc_irq_flag_init(void); 227 void rksfc_wait_for_irq_completed(void); 228 u32 sfc_get_max_dll_cells(void); 229 #endif 230