xref: /OK3568_Linux_fs/kernel/drivers/rkflash/rknandc_base.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun 
3*4882a593Smuzhiyun /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */
4*4882a593Smuzhiyun 
5*4882a593Smuzhiyun #include <asm/cacheflush.h>
6*4882a593Smuzhiyun #include <linux/clk.h>
7*4882a593Smuzhiyun #include <linux/dma-mapping.h>
8*4882a593Smuzhiyun #include <linux/interrupt.h>
9*4882a593Smuzhiyun #include <linux/irq.h>
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/sched.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun #ifdef CONFIG_OF
16*4882a593Smuzhiyun #include <linux/of.h>
17*4882a593Smuzhiyun #endif
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include "nandc.h"
20*4882a593Smuzhiyun #include "rkflash_api.h"
21*4882a593Smuzhiyun #include "rkflash_blk.h"
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define RKNANDC_VERSION_AND_DATE	"rknandc_base v1.1 2017-01-11"
24*4882a593Smuzhiyun #define	RKNANDC_CLK_SET_RATE		(150 * 1000 * 1000)
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun struct rknandc_info {
27*4882a593Smuzhiyun 	void __iomem	*reg_base;
28*4882a593Smuzhiyun 	int	irq;
29*4882a593Smuzhiyun 	int	clk_rate;
30*4882a593Smuzhiyun 	struct clk	*clk;		/* controller's clk*/
31*4882a593Smuzhiyun 	struct clk	*ahb_clk;	/* ahb clk gate*/
32*4882a593Smuzhiyun 	struct clk	*g_clk;		/* clk_src_en gate*/
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun static struct rknandc_info g_nandc_info;
36*4882a593Smuzhiyun static struct device *g_nandc_dev;
37*4882a593Smuzhiyun static struct completion nandc_irq_complete;
38*4882a593Smuzhiyun 
rknandc_dma_map_single(unsigned long ptr,int size,int dir)39*4882a593Smuzhiyun unsigned long rknandc_dma_map_single(unsigned long ptr, int size, int dir)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun 	return dma_map_single(g_nandc_dev, (void *)ptr, size
42*4882a593Smuzhiyun 		, dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun 
rknandc_dma_unmap_single(unsigned long ptr,int size,int dir)45*4882a593Smuzhiyun void rknandc_dma_unmap_single(unsigned long ptr, int size, int dir)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun 	dma_unmap_single(g_nandc_dev, (dma_addr_t)ptr, size
48*4882a593Smuzhiyun 		, dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun 
rknandc_interrupt(int irq,void * dev_id)51*4882a593Smuzhiyun static irqreturn_t rknandc_interrupt(int irq, void *dev_id)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun 	nandc_clean_irq();
54*4882a593Smuzhiyun 	complete(&nandc_irq_complete);
55*4882a593Smuzhiyun 	return IRQ_HANDLED;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun 
rknandc_irq_config(int mode,void * pfun)58*4882a593Smuzhiyun static int rknandc_irq_config(int mode, void *pfun)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun 	int ret = 0;
61*4882a593Smuzhiyun 	int irq = g_nandc_info.irq;
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	if (mode)
64*4882a593Smuzhiyun 		ret = request_irq(irq, pfun, 0, "rknandc",
65*4882a593Smuzhiyun 				  g_nandc_info.reg_base);
66*4882a593Smuzhiyun 	else
67*4882a593Smuzhiyun 		free_irq(irq,  NULL);
68*4882a593Smuzhiyun 	return ret;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun 
rknandc_irq_init(void)71*4882a593Smuzhiyun static int rknandc_irq_init(void)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun 	init_completion(&nandc_irq_complete);
74*4882a593Smuzhiyun 	rknandc_irq_config(1, rknandc_interrupt);
75*4882a593Smuzhiyun 	return 0;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun 
rknandc_irq_deinit(void)78*4882a593Smuzhiyun static int rknandc_irq_deinit(void)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun 	rknandc_irq_config(0, rknandc_interrupt);
81*4882a593Smuzhiyun 	return 0;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun 
rknandc_probe(struct platform_device * pdev)84*4882a593Smuzhiyun static int rknandc_probe(struct platform_device *pdev)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun 	int irq;
87*4882a593Smuzhiyun 	struct resource	*mem;
88*4882a593Smuzhiyun 	void __iomem	*membase;
89*4882a593Smuzhiyun 	int ret;
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	g_nandc_dev = &pdev->dev;
92*4882a593Smuzhiyun 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
93*4882a593Smuzhiyun 	membase = devm_ioremap_resource(&pdev->dev, mem);
94*4882a593Smuzhiyun 	if (!membase) {
95*4882a593Smuzhiyun 		dev_err(&pdev->dev, "no reg resource?\n");
96*4882a593Smuzhiyun 		return -1;
97*4882a593Smuzhiyun 	}
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	irq = platform_get_irq(pdev, 0);
100*4882a593Smuzhiyun 	if (irq < 0) {
101*4882a593Smuzhiyun 		dev_err(&pdev->dev, "no irq resource?\n");
102*4882a593Smuzhiyun 		return irq;
103*4882a593Smuzhiyun 	}
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	g_nandc_info.irq = irq;
106*4882a593Smuzhiyun 	g_nandc_info.reg_base = membase;
107*4882a593Smuzhiyun 	g_nandc_info.ahb_clk = devm_clk_get(&pdev->dev, "hclk_nandc");
108*4882a593Smuzhiyun 	g_nandc_info.clk = devm_clk_get(&pdev->dev, "clk_nandc");
109*4882a593Smuzhiyun 	g_nandc_info.g_clk = devm_clk_get(&pdev->dev, "g_clk_nandc");
110*4882a593Smuzhiyun 	if (unlikely(IS_ERR(g_nandc_info.clk)) ||
111*4882a593Smuzhiyun 	    unlikely(IS_ERR(g_nandc_info.ahb_clk))) {
112*4882a593Smuzhiyun 		dev_err(&pdev->dev, "%s get clk error\n", __func__);
113*4882a593Smuzhiyun 		return -1;
114*4882a593Smuzhiyun 	}
115*4882a593Smuzhiyun 	clk_prepare_enable(g_nandc_info.ahb_clk);
116*4882a593Smuzhiyun 	if (!(IS_ERR(g_nandc_info.g_clk)))
117*4882a593Smuzhiyun 		clk_prepare_enable(g_nandc_info.g_clk);
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	clk_set_rate(g_nandc_info.clk, RKNANDC_CLK_SET_RATE);
120*4882a593Smuzhiyun 	g_nandc_info.clk_rate = clk_get_rate(g_nandc_info.clk);
121*4882a593Smuzhiyun 	clk_prepare_enable(g_nandc_info.clk);
122*4882a593Smuzhiyun 	dev_info(&pdev->dev,
123*4882a593Smuzhiyun 		 "%s clk rate = %d\n",
124*4882a593Smuzhiyun 		 __func__,
125*4882a593Smuzhiyun 		 g_nandc_info.clk_rate);
126*4882a593Smuzhiyun 	rknandc_irq_init();
127*4882a593Smuzhiyun 	ret = rkflash_dev_init(g_nandc_info.reg_base, FLASH_TYPE_NANDC_NAND, &nandc_nand_ops);
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	if (ret)
130*4882a593Smuzhiyun 		return ret;
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	return dma_set_mask(g_nandc_dev, DMA_BIT_MASK(32));
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun 
rknandc_suspend(struct device * dev)135*4882a593Smuzhiyun static int __maybe_unused rknandc_suspend(struct device *dev)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun 	return rkflash_dev_suspend();
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun 
rknandc_resume(struct device * dev)140*4882a593Smuzhiyun static int __maybe_unused rknandc_resume(struct device *dev)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun 	return rkflash_dev_resume(g_nandc_info.reg_base);
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(rknandc_pmops,
146*4882a593Smuzhiyun 			 rknandc_suspend,
147*4882a593Smuzhiyun 			 rknandc_resume);
148*4882a593Smuzhiyun 
rknandc_shutdown(struct platform_device * pdev)149*4882a593Smuzhiyun static void rknandc_shutdown(struct platform_device *pdev)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun 	rkflash_dev_shutdown();
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun #ifdef CONFIG_OF
155*4882a593Smuzhiyun static const struct of_device_id of_rknandc_match[] = {
156*4882a593Smuzhiyun 	{.compatible = "rockchip,rk-nandc"},
157*4882a593Smuzhiyun 	{.compatible = "rockchip,nandc"},
158*4882a593Smuzhiyun 	{}
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun #endif
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun static struct platform_driver rknandc_driver = {
163*4882a593Smuzhiyun 	.probe		= rknandc_probe,
164*4882a593Smuzhiyun 	.shutdown	= rknandc_shutdown,
165*4882a593Smuzhiyun 	.driver		= {
166*4882a593Smuzhiyun 		.name	= "rknandc",
167*4882a593Smuzhiyun #ifdef CONFIG_OF
168*4882a593Smuzhiyun 		.of_match_table	= of_rknandc_match,
169*4882a593Smuzhiyun #endif
170*4882a593Smuzhiyun 		.pm		= &rknandc_pmops,
171*4882a593Smuzhiyun 	},
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun 
rknandc_driver_exit(void)174*4882a593Smuzhiyun static void __exit rknandc_driver_exit(void)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun 	rkflash_dev_exit();
177*4882a593Smuzhiyun 	rknandc_irq_deinit();
178*4882a593Smuzhiyun 	platform_driver_unregister(&rknandc_driver);
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun 
rknandc_driver_init(void)181*4882a593Smuzhiyun static int __init rknandc_driver_init(void)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun 	int ret = 0;
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	pr_err("%s\n", RKNANDC_VERSION_AND_DATE);
186*4882a593Smuzhiyun 	ret = platform_driver_register(&rknandc_driver);
187*4882a593Smuzhiyun 	return ret;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun module_init(rknandc_driver_init);
191*4882a593Smuzhiyun module_exit(rknandc_driver_exit);
192*4882a593Smuzhiyun MODULE_ALIAS("rknandc");
193