1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun /* Copyright (c) 2018 Rockchip Electronics Co. Ltd. */ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #ifndef __FLASH_COM_H 6*4882a593Smuzhiyun #define __FLASH_COM_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include "typedef.h" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define NAND_ERROR INVALID_UINT32 11*4882a593Smuzhiyun #define NAND_OK 0 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define NAND_STS_OK 0 /* bit 0 ecc error or ok */ 14*4882a593Smuzhiyun #define NAND_STS_REFRESH 256 /* need refresh */ 15*4882a593Smuzhiyun #define NAND_STS_EMPTY 512 /* page is not proged */ 16*4882a593Smuzhiyun #define NAND_STS_ECC_ERR NAND_ERROR 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define NAND_IDB_START 64 /* 32 KB*/ 19*4882a593Smuzhiyun #define NAND_IDB_SIZE 512 /* 256 KB*/ 20*4882a593Smuzhiyun #define NAND_IDB_END (NAND_IDB_START + NAND_IDB_SIZE - 1) 21*4882a593Smuzhiyun #define DEFAULT_IDB_RESERVED_BLOCK 8 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define FULL_SLC 0 24*4882a593Smuzhiyun #define SLC 1 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define NAND_FLASH_MLC_PAGE_TAG 0xFFFF 27*4882a593Smuzhiyun #define MAX_FLASH_PAGE_SIZE 0x1000 /* 4KB */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define PAGE_ADDR_BITS 0 30*4882a593Smuzhiyun #define PAGE_ADDR_MASK ((1u << 11) - 1) 31*4882a593Smuzhiyun #define BLOCK_ADDR_BITS 11 32*4882a593Smuzhiyun #define BLOCK_ADDR_MASK ((1u << 14) - 1) 33*4882a593Smuzhiyun #define DIE_ADDR_BITS 25 34*4882a593Smuzhiyun #define DIE_ADDR_MASK ((1u << 3) - 1) 35*4882a593Smuzhiyun #define FLAG_ADDR_BITS 28 36*4882a593Smuzhiyun #define FLAG_ADDR_MASK ((1u << 4) - 1) 37*4882a593Smuzhiyun #define PHY_BLK_DIE_ADDR_BITS 14 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun struct nand_req { 40*4882a593Smuzhiyun u32 status; 41*4882a593Smuzhiyun u32 page_addr; /* 31:28 flag, 27:25: die, 24:11 block, 10:0 page */ 42*4882a593Smuzhiyun u32 *p_data; 43*4882a593Smuzhiyun u32 *p_spare; 44*4882a593Smuzhiyun u32 lpa; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun struct nand_phy_info { 48*4882a593Smuzhiyun u16 nand_type; /* SLC,MLC,TLC */ 49*4882a593Smuzhiyun u16 die_num; /* number of LUNs */ 50*4882a593Smuzhiyun u16 plane_per_die; 51*4882a593Smuzhiyun u16 blk_per_plane; 52*4882a593Smuzhiyun u16 blk_per_die; 53*4882a593Smuzhiyun u16 page_per_blk; /* in MLC mode */ 54*4882a593Smuzhiyun u16 page_per_slc_blk; /* in SLC mode */ 55*4882a593Smuzhiyun u16 sec_per_page; /* physical page data size */ 56*4882a593Smuzhiyun u16 sec_per_blk; /* physical page data size */ 57*4882a593Smuzhiyun u16 byte_per_sec; /* size of logical sectors */ 58*4882a593Smuzhiyun u16 reserved_blk; /* reserved for boot loader in die 0*/ 59*4882a593Smuzhiyun u8 ecc_bits; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun struct nand_ops { 63*4882a593Smuzhiyun s32 (*get_bad_blk_list)(u16 *table, u32 die); 64*4882a593Smuzhiyun u32 (*erase_blk)(u8 cs, u32 page_addr); 65*4882a593Smuzhiyun u32 (*prog_page)(u8 cs, u32 page_addr, u32 *data, u32 *spare); 66*4882a593Smuzhiyun u32 (*read_page)(u8 cs, u32 page_addr, u32 *data, u32 *spare); 67*4882a593Smuzhiyun void (*bch_sel)(u8 bits); 68*4882a593Smuzhiyun void (*set_sec_num)(u8 num); 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun s32 ftl_flash_prog_pages(void *req, u32 num_req, u32 flash_type, u32 check); 72*4882a593Smuzhiyun s32 ftl_flash_read_pages(void *req, u32 num_req, u32 flash_type); 73*4882a593Smuzhiyun s32 ftl_flash_erase_blocks(void *req, u32 num_req); 74*4882a593Smuzhiyun s32 ftl_flash_test_blk(u16 phy_block); 75*4882a593Smuzhiyun s32 ftl_flash_get_bad_blk_list(u16 *table, u32 die); 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #endif 78