1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2013 STMicroelectronics (R&D) Limited 4*4882a593Smuzhiyun * Author: Stephen Gallimore <stephen.gallimore@st.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef __STI_RESET_SYSCFG_H 7*4882a593Smuzhiyun #define __STI_RESET_SYSCFG_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/device.h> 10*4882a593Smuzhiyun #include <linux/regmap.h> 11*4882a593Smuzhiyun #include <linux/reset-controller.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /** 14*4882a593Smuzhiyun * Reset channel description for a system configuration register based 15*4882a593Smuzhiyun * reset controller. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * @compatible: Compatible string of the syscon regmap containing this 18*4882a593Smuzhiyun * channel's control and ack (status) bits. 19*4882a593Smuzhiyun * @reset: Regmap field description of the channel's reset bit. 20*4882a593Smuzhiyun * @ack: Regmap field description of the channel's acknowledge bit. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun struct syscfg_reset_channel_data { 23*4882a593Smuzhiyun const char *compatible; 24*4882a593Smuzhiyun struct reg_field reset; 25*4882a593Smuzhiyun struct reg_field ack; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define _SYSCFG_RST_CH(_c, _rr, _rb, _ar, _ab) \ 29*4882a593Smuzhiyun { .compatible = _c, \ 30*4882a593Smuzhiyun .reset = REG_FIELD(_rr, _rb, _rb), \ 31*4882a593Smuzhiyun .ack = REG_FIELD(_ar, _ab, _ab), } 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define _SYSCFG_RST_CH_NO_ACK(_c, _rr, _rb) \ 34*4882a593Smuzhiyun { .compatible = _c, \ 35*4882a593Smuzhiyun .reset = REG_FIELD(_rr, _rb, _rb), } 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /** 38*4882a593Smuzhiyun * Description of a system configuration register based reset controller. 39*4882a593Smuzhiyun * 40*4882a593Smuzhiyun * @wait_for_ack: The controller will wait for reset assert and de-assert to 41*4882a593Smuzhiyun * be "ack'd" in a channel's ack field. 42*4882a593Smuzhiyun * @active_low: Are the resets in this controller active low, i.e. clearing 43*4882a593Smuzhiyun * the reset bit puts the hardware into reset. 44*4882a593Smuzhiyun * @nr_channels: The number of reset channels in this controller. 45*4882a593Smuzhiyun * @channels: An array of reset channel descriptions. 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun struct syscfg_reset_controller_data { 48*4882a593Smuzhiyun bool wait_for_ack; 49*4882a593Smuzhiyun bool active_low; 50*4882a593Smuzhiyun int nr_channels; 51*4882a593Smuzhiyun const struct syscfg_reset_channel_data *channels; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /** 55*4882a593Smuzhiyun * syscfg_reset_probe(): platform device probe function used by syscfg 56*4882a593Smuzhiyun * reset controller drivers. This registers a reset 57*4882a593Smuzhiyun * controller configured by the OF match data for 58*4882a593Smuzhiyun * the compatible device which should be of type 59*4882a593Smuzhiyun * "struct syscfg_reset_controller_data". 60*4882a593Smuzhiyun * 61*4882a593Smuzhiyun * @pdev: platform device 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun int syscfg_reset_probe(struct platform_device *pdev); 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #endif /* __STI_RESET_SYSCFG_H */ 66