1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
4*4882a593Smuzhiyun * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/device.h>
8*4882a593Smuzhiyun #include <linux/err.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/reset-controller.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define CLR_OFFSET 0x4
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun struct stm32_reset_data {
17*4882a593Smuzhiyun struct reset_controller_dev rcdev;
18*4882a593Smuzhiyun void __iomem *membase;
19*4882a593Smuzhiyun };
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun static inline struct stm32_reset_data *
to_stm32_reset_data(struct reset_controller_dev * rcdev)22*4882a593Smuzhiyun to_stm32_reset_data(struct reset_controller_dev *rcdev)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun return container_of(rcdev, struct stm32_reset_data, rcdev);
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun
stm32_reset_update(struct reset_controller_dev * rcdev,unsigned long id,bool assert)27*4882a593Smuzhiyun static int stm32_reset_update(struct reset_controller_dev *rcdev,
28*4882a593Smuzhiyun unsigned long id, bool assert)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
31*4882a593Smuzhiyun int reg_width = sizeof(u32);
32*4882a593Smuzhiyun int bank = id / (reg_width * BITS_PER_BYTE);
33*4882a593Smuzhiyun int offset = id % (reg_width * BITS_PER_BYTE);
34*4882a593Smuzhiyun void __iomem *addr;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun addr = data->membase + (bank * reg_width);
37*4882a593Smuzhiyun if (!assert)
38*4882a593Smuzhiyun addr += CLR_OFFSET;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun writel(BIT(offset), addr);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun return 0;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
stm32_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)45*4882a593Smuzhiyun static int stm32_reset_assert(struct reset_controller_dev *rcdev,
46*4882a593Smuzhiyun unsigned long id)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun return stm32_reset_update(rcdev, id, true);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
stm32_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)51*4882a593Smuzhiyun static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
52*4882a593Smuzhiyun unsigned long id)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun return stm32_reset_update(rcdev, id, false);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
stm32_reset_status(struct reset_controller_dev * rcdev,unsigned long id)57*4882a593Smuzhiyun static int stm32_reset_status(struct reset_controller_dev *rcdev,
58*4882a593Smuzhiyun unsigned long id)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
61*4882a593Smuzhiyun int reg_width = sizeof(u32);
62*4882a593Smuzhiyun int bank = id / (reg_width * BITS_PER_BYTE);
63*4882a593Smuzhiyun int offset = id % (reg_width * BITS_PER_BYTE);
64*4882a593Smuzhiyun u32 reg;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun reg = readl(data->membase + (bank * reg_width));
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun return !!(reg & BIT(offset));
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun static const struct reset_control_ops stm32_reset_ops = {
72*4882a593Smuzhiyun .assert = stm32_reset_assert,
73*4882a593Smuzhiyun .deassert = stm32_reset_deassert,
74*4882a593Smuzhiyun .status = stm32_reset_status,
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun static const struct of_device_id stm32_reset_dt_ids[] = {
78*4882a593Smuzhiyun { .compatible = "st,stm32mp1-rcc"},
79*4882a593Smuzhiyun { /* sentinel */ },
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
stm32_reset_probe(struct platform_device * pdev)82*4882a593Smuzhiyun static int stm32_reset_probe(struct platform_device *pdev)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun struct device *dev = &pdev->dev;
85*4882a593Smuzhiyun struct stm32_reset_data *data;
86*4882a593Smuzhiyun void __iomem *membase;
87*4882a593Smuzhiyun struct resource *res;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
90*4882a593Smuzhiyun if (!data)
91*4882a593Smuzhiyun return -ENOMEM;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
94*4882a593Smuzhiyun membase = devm_ioremap_resource(dev, res);
95*4882a593Smuzhiyun if (IS_ERR(membase))
96*4882a593Smuzhiyun return PTR_ERR(membase);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun data->membase = membase;
99*4882a593Smuzhiyun data->rcdev.owner = THIS_MODULE;
100*4882a593Smuzhiyun data->rcdev.nr_resets = resource_size(res) * BITS_PER_BYTE;
101*4882a593Smuzhiyun data->rcdev.ops = &stm32_reset_ops;
102*4882a593Smuzhiyun data->rcdev.of_node = dev->of_node;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun return devm_reset_controller_register(dev, &data->rcdev);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun static struct platform_driver stm32_reset_driver = {
108*4882a593Smuzhiyun .probe = stm32_reset_probe,
109*4882a593Smuzhiyun .driver = {
110*4882a593Smuzhiyun .name = "stm32mp1-reset",
111*4882a593Smuzhiyun .of_match_table = stm32_reset_dt_ids,
112*4882a593Smuzhiyun },
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun builtin_platform_driver(stm32_reset_driver);
116