1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2018, Intel Corporation
4*4882a593Smuzhiyun * Copied from reset-sunxi.c
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/err.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun #include <linux/of_address.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/reset-controller.h>
14*4882a593Smuzhiyun #include <linux/reset/reset-simple.h>
15*4882a593Smuzhiyun #include <linux/reset/socfpga.h>
16*4882a593Smuzhiyun #include <linux/slab.h>
17*4882a593Smuzhiyun #include <linux/spinlock.h>
18*4882a593Smuzhiyun #include <linux/types.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define SOCFPGA_NR_BANKS 8
21*4882a593Smuzhiyun
a10_reset_init(struct device_node * np)22*4882a593Smuzhiyun static int a10_reset_init(struct device_node *np)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun struct reset_simple_data *data;
25*4882a593Smuzhiyun struct resource res;
26*4882a593Smuzhiyun resource_size_t size;
27*4882a593Smuzhiyun int ret;
28*4882a593Smuzhiyun u32 reg_offset = 0x10;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun data = kzalloc(sizeof(*data), GFP_KERNEL);
31*4882a593Smuzhiyun if (!data)
32*4882a593Smuzhiyun return -ENOMEM;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun ret = of_address_to_resource(np, 0, &res);
35*4882a593Smuzhiyun if (ret)
36*4882a593Smuzhiyun goto err_alloc;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun size = resource_size(&res);
39*4882a593Smuzhiyun if (!request_mem_region(res.start, size, np->name)) {
40*4882a593Smuzhiyun ret = -EBUSY;
41*4882a593Smuzhiyun goto err_alloc;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun data->membase = ioremap(res.start, size);
45*4882a593Smuzhiyun if (!data->membase) {
46*4882a593Smuzhiyun ret = -ENOMEM;
47*4882a593Smuzhiyun goto err_alloc;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun if (of_property_read_u32(np, "altr,modrst-offset", ®_offset))
51*4882a593Smuzhiyun pr_warn("missing altr,modrst-offset property, assuming 0x10\n");
52*4882a593Smuzhiyun data->membase += reg_offset;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun spin_lock_init(&data->lock);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun data->rcdev.owner = THIS_MODULE;
57*4882a593Smuzhiyun data->rcdev.nr_resets = SOCFPGA_NR_BANKS * 32;
58*4882a593Smuzhiyun data->rcdev.ops = &reset_simple_ops;
59*4882a593Smuzhiyun data->rcdev.of_node = np;
60*4882a593Smuzhiyun data->status_active_low = true;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun return reset_controller_register(&data->rcdev);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun err_alloc:
65*4882a593Smuzhiyun kfree(data);
66*4882a593Smuzhiyun return ret;
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /*
70*4882a593Smuzhiyun * These are the reset controller we need to initialize early on in
71*4882a593Smuzhiyun * our system, before we can even think of using a regular device
72*4882a593Smuzhiyun * driver for it.
73*4882a593Smuzhiyun * The controllers that we can register through the regular device
74*4882a593Smuzhiyun * model are handled by the simple reset driver directly.
75*4882a593Smuzhiyun */
76*4882a593Smuzhiyun static const struct of_device_id socfpga_early_reset_dt_ids[] __initconst = {
77*4882a593Smuzhiyun { .compatible = "altr,rst-mgr", },
78*4882a593Smuzhiyun { /* sentinel */ },
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
socfpga_reset_init(void)81*4882a593Smuzhiyun void __init socfpga_reset_init(void)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun struct device_node *np;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun for_each_matching_node(np, socfpga_early_reset_dt_ids)
86*4882a593Smuzhiyun a10_reset_init(np);
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /*
90*4882a593Smuzhiyun * The early driver is problematic, because it doesn't register
91*4882a593Smuzhiyun * itself as a driver. This causes certain device links to prevent
92*4882a593Smuzhiyun * consumer devices from probing. The hacky solution is to register
93*4882a593Smuzhiyun * an empty driver, whose only job is to attach itself to the reset
94*4882a593Smuzhiyun * manager and call probe.
95*4882a593Smuzhiyun */
96*4882a593Smuzhiyun static const struct of_device_id socfpga_reset_dt_ids[] = {
97*4882a593Smuzhiyun { .compatible = "altr,rst-mgr", },
98*4882a593Smuzhiyun { /* sentinel */ },
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
reset_simple_probe(struct platform_device * pdev)101*4882a593Smuzhiyun static int reset_simple_probe(struct platform_device *pdev)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun return 0;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun static struct platform_driver reset_socfpga_driver = {
107*4882a593Smuzhiyun .probe = reset_simple_probe,
108*4882a593Smuzhiyun .driver = {
109*4882a593Smuzhiyun .name = "socfpga-reset",
110*4882a593Smuzhiyun .of_match_table = socfpga_reset_dt_ids,
111*4882a593Smuzhiyun },
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun builtin_platform_driver(reset_socfpga_driver);
114