1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2018 The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/module.h>
7*4882a593Smuzhiyun #include <linux/of_device.h>
8*4882a593Smuzhiyun #include <linux/platform_device.h>
9*4882a593Smuzhiyun #include <linux/regmap.h>
10*4882a593Smuzhiyun #include <linux/reset-controller.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <dt-bindings/reset/qcom,sdm845-pdc.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define RPMH_PDC_SYNC_RESET 0x100
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun struct qcom_pdc_reset_map {
17*4882a593Smuzhiyun u8 bit;
18*4882a593Smuzhiyun };
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun struct qcom_pdc_reset_data {
21*4882a593Smuzhiyun struct reset_controller_dev rcdev;
22*4882a593Smuzhiyun struct regmap *regmap;
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun static const struct regmap_config sdm845_pdc_regmap_config = {
26*4882a593Smuzhiyun .name = "pdc-reset",
27*4882a593Smuzhiyun .reg_bits = 32,
28*4882a593Smuzhiyun .reg_stride = 4,
29*4882a593Smuzhiyun .val_bits = 32,
30*4882a593Smuzhiyun .max_register = 0x20000,
31*4882a593Smuzhiyun .fast_io = true,
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun static const struct qcom_pdc_reset_map sdm845_pdc_resets[] = {
35*4882a593Smuzhiyun [PDC_APPS_SYNC_RESET] = {0},
36*4882a593Smuzhiyun [PDC_SP_SYNC_RESET] = {1},
37*4882a593Smuzhiyun [PDC_AUDIO_SYNC_RESET] = {2},
38*4882a593Smuzhiyun [PDC_SENSORS_SYNC_RESET] = {3},
39*4882a593Smuzhiyun [PDC_AOP_SYNC_RESET] = {4},
40*4882a593Smuzhiyun [PDC_DEBUG_SYNC_RESET] = {5},
41*4882a593Smuzhiyun [PDC_GPU_SYNC_RESET] = {6},
42*4882a593Smuzhiyun [PDC_DISPLAY_SYNC_RESET] = {7},
43*4882a593Smuzhiyun [PDC_COMPUTE_SYNC_RESET] = {8},
44*4882a593Smuzhiyun [PDC_MODEM_SYNC_RESET] = {9},
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
to_qcom_pdc_reset_data(struct reset_controller_dev * rcdev)47*4882a593Smuzhiyun static inline struct qcom_pdc_reset_data *to_qcom_pdc_reset_data(
48*4882a593Smuzhiyun struct reset_controller_dev *rcdev)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun return container_of(rcdev, struct qcom_pdc_reset_data, rcdev);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
qcom_pdc_control_assert(struct reset_controller_dev * rcdev,unsigned long idx)53*4882a593Smuzhiyun static int qcom_pdc_control_assert(struct reset_controller_dev *rcdev,
54*4882a593Smuzhiyun unsigned long idx)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
59*4882a593Smuzhiyun BIT(sdm845_pdc_resets[idx].bit),
60*4882a593Smuzhiyun BIT(sdm845_pdc_resets[idx].bit));
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
qcom_pdc_control_deassert(struct reset_controller_dev * rcdev,unsigned long idx)63*4882a593Smuzhiyun static int qcom_pdc_control_deassert(struct reset_controller_dev *rcdev,
64*4882a593Smuzhiyun unsigned long idx)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun return regmap_update_bits(data->regmap, RPMH_PDC_SYNC_RESET,
69*4882a593Smuzhiyun BIT(sdm845_pdc_resets[idx].bit), 0);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun static const struct reset_control_ops qcom_pdc_reset_ops = {
73*4882a593Smuzhiyun .assert = qcom_pdc_control_assert,
74*4882a593Smuzhiyun .deassert = qcom_pdc_control_deassert,
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
qcom_pdc_reset_probe(struct platform_device * pdev)77*4882a593Smuzhiyun static int qcom_pdc_reset_probe(struct platform_device *pdev)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun struct qcom_pdc_reset_data *data;
80*4882a593Smuzhiyun struct device *dev = &pdev->dev;
81*4882a593Smuzhiyun void __iomem *base;
82*4882a593Smuzhiyun struct resource *res;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
85*4882a593Smuzhiyun if (!data)
86*4882a593Smuzhiyun return -ENOMEM;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
89*4882a593Smuzhiyun base = devm_ioremap_resource(dev, res);
90*4882a593Smuzhiyun if (IS_ERR(base))
91*4882a593Smuzhiyun return PTR_ERR(base);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun data->regmap = devm_regmap_init_mmio(dev, base,
94*4882a593Smuzhiyun &sdm845_pdc_regmap_config);
95*4882a593Smuzhiyun if (IS_ERR(data->regmap)) {
96*4882a593Smuzhiyun dev_err(dev, "Unable to initialize regmap\n");
97*4882a593Smuzhiyun return PTR_ERR(data->regmap);
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun data->rcdev.owner = THIS_MODULE;
101*4882a593Smuzhiyun data->rcdev.ops = &qcom_pdc_reset_ops;
102*4882a593Smuzhiyun data->rcdev.nr_resets = ARRAY_SIZE(sdm845_pdc_resets);
103*4882a593Smuzhiyun data->rcdev.of_node = dev->of_node;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun return devm_reset_controller_register(dev, &data->rcdev);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun static const struct of_device_id qcom_pdc_reset_of_match[] = {
109*4882a593Smuzhiyun { .compatible = "qcom,sdm845-pdc-global" },
110*4882a593Smuzhiyun {}
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, qcom_pdc_reset_of_match);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun static struct platform_driver qcom_pdc_reset_driver = {
115*4882a593Smuzhiyun .probe = qcom_pdc_reset_probe,
116*4882a593Smuzhiyun .driver = {
117*4882a593Smuzhiyun .name = "qcom_pdc_reset",
118*4882a593Smuzhiyun .of_match_table = qcom_pdc_reset_of_match,
119*4882a593Smuzhiyun },
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun module_platform_driver(qcom_pdc_reset_driver);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun MODULE_DESCRIPTION("Qualcomm PDC Reset Driver");
124*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
125