1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * drivers/reset/reset-oxnas.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
6*4882a593Smuzhiyun * Copyright (C) 2014 Ma Haijun <mahaijuns@gmail.com>
7*4882a593Smuzhiyun * Copyright (C) 2009 Oxford Semiconductor Ltd
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #include <linux/err.h>
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/reset-controller.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/types.h>
17*4882a593Smuzhiyun #include <linux/regmap.h>
18*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /* Regmap offsets */
21*4882a593Smuzhiyun #define RST_SET_REGOFFSET 0x34
22*4882a593Smuzhiyun #define RST_CLR_REGOFFSET 0x38
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun struct oxnas_reset {
25*4882a593Smuzhiyun struct regmap *regmap;
26*4882a593Smuzhiyun struct reset_controller_dev rcdev;
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
oxnas_reset_reset(struct reset_controller_dev * rcdev,unsigned long id)29*4882a593Smuzhiyun static int oxnas_reset_reset(struct reset_controller_dev *rcdev,
30*4882a593Smuzhiyun unsigned long id)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun struct oxnas_reset *data =
33*4882a593Smuzhiyun container_of(rcdev, struct oxnas_reset, rcdev);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun regmap_write(data->regmap, RST_SET_REGOFFSET, BIT(id));
36*4882a593Smuzhiyun msleep(50);
37*4882a593Smuzhiyun regmap_write(data->regmap, RST_CLR_REGOFFSET, BIT(id));
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun return 0;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
oxnas_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)42*4882a593Smuzhiyun static int oxnas_reset_assert(struct reset_controller_dev *rcdev,
43*4882a593Smuzhiyun unsigned long id)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun struct oxnas_reset *data =
46*4882a593Smuzhiyun container_of(rcdev, struct oxnas_reset, rcdev);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun regmap_write(data->regmap, RST_SET_REGOFFSET, BIT(id));
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun return 0;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
oxnas_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)53*4882a593Smuzhiyun static int oxnas_reset_deassert(struct reset_controller_dev *rcdev,
54*4882a593Smuzhiyun unsigned long id)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun struct oxnas_reset *data =
57*4882a593Smuzhiyun container_of(rcdev, struct oxnas_reset, rcdev);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun regmap_write(data->regmap, RST_CLR_REGOFFSET, BIT(id));
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun return 0;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun static const struct reset_control_ops oxnas_reset_ops = {
65*4882a593Smuzhiyun .reset = oxnas_reset_reset,
66*4882a593Smuzhiyun .assert = oxnas_reset_assert,
67*4882a593Smuzhiyun .deassert = oxnas_reset_deassert,
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun static const struct of_device_id oxnas_reset_dt_ids[] = {
71*4882a593Smuzhiyun { .compatible = "oxsemi,ox810se-reset", },
72*4882a593Smuzhiyun { .compatible = "oxsemi,ox820-reset", },
73*4882a593Smuzhiyun { /* sentinel */ },
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
oxnas_reset_probe(struct platform_device * pdev)76*4882a593Smuzhiyun static int oxnas_reset_probe(struct platform_device *pdev)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun struct oxnas_reset *data;
79*4882a593Smuzhiyun struct device *parent;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun parent = pdev->dev.parent;
82*4882a593Smuzhiyun if (!parent) {
83*4882a593Smuzhiyun dev_err(&pdev->dev, "no parent\n");
84*4882a593Smuzhiyun return -ENODEV;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
88*4882a593Smuzhiyun if (!data)
89*4882a593Smuzhiyun return -ENOMEM;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun data->regmap = syscon_node_to_regmap(parent->of_node);
92*4882a593Smuzhiyun if (IS_ERR(data->regmap)) {
93*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to get parent regmap\n");
94*4882a593Smuzhiyun return PTR_ERR(data->regmap);
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun platform_set_drvdata(pdev, data);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun data->rcdev.owner = THIS_MODULE;
100*4882a593Smuzhiyun data->rcdev.nr_resets = 32;
101*4882a593Smuzhiyun data->rcdev.ops = &oxnas_reset_ops;
102*4882a593Smuzhiyun data->rcdev.of_node = pdev->dev.of_node;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun return devm_reset_controller_register(&pdev->dev, &data->rcdev);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun static struct platform_driver oxnas_reset_driver = {
108*4882a593Smuzhiyun .probe = oxnas_reset_probe,
109*4882a593Smuzhiyun .driver = {
110*4882a593Smuzhiyun .name = "oxnas-reset",
111*4882a593Smuzhiyun .of_match_table = oxnas_reset_dt_ids,
112*4882a593Smuzhiyun },
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun builtin_platform_driver(oxnas_reset_driver);
115