1*4882a593Smuzhiyun // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2*4882a593Smuzhiyun // Copyright (c) 2018 BayLibre, SAS.
3*4882a593Smuzhiyun // Author: Jerome Brunet <jbrunet@baylibre.com>
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #include <linux/clk.h>
6*4882a593Smuzhiyun #include <linux/io.h>
7*4882a593Smuzhiyun #include <linux/module.h>
8*4882a593Smuzhiyun #include <linux/of_platform.h>
9*4882a593Smuzhiyun #include <linux/reset-controller.h>
10*4882a593Smuzhiyun #include <linux/spinlock.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun struct meson_audio_arb_data {
15*4882a593Smuzhiyun struct reset_controller_dev rstc;
16*4882a593Smuzhiyun void __iomem *regs;
17*4882a593Smuzhiyun struct clk *clk;
18*4882a593Smuzhiyun const unsigned int *reset_bits;
19*4882a593Smuzhiyun spinlock_t lock;
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun struct meson_audio_arb_match_data {
23*4882a593Smuzhiyun const unsigned int *reset_bits;
24*4882a593Smuzhiyun unsigned int reset_num;
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define ARB_GENERAL_BIT 31
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun static const unsigned int axg_audio_arb_reset_bits[] = {
30*4882a593Smuzhiyun [AXG_ARB_TODDR_A] = 0,
31*4882a593Smuzhiyun [AXG_ARB_TODDR_B] = 1,
32*4882a593Smuzhiyun [AXG_ARB_TODDR_C] = 2,
33*4882a593Smuzhiyun [AXG_ARB_FRDDR_A] = 4,
34*4882a593Smuzhiyun [AXG_ARB_FRDDR_B] = 5,
35*4882a593Smuzhiyun [AXG_ARB_FRDDR_C] = 6,
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun static const struct meson_audio_arb_match_data axg_audio_arb_match = {
39*4882a593Smuzhiyun .reset_bits = axg_audio_arb_reset_bits,
40*4882a593Smuzhiyun .reset_num = ARRAY_SIZE(axg_audio_arb_reset_bits),
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun static const unsigned int sm1_audio_arb_reset_bits[] = {
44*4882a593Smuzhiyun [AXG_ARB_TODDR_A] = 0,
45*4882a593Smuzhiyun [AXG_ARB_TODDR_B] = 1,
46*4882a593Smuzhiyun [AXG_ARB_TODDR_C] = 2,
47*4882a593Smuzhiyun [AXG_ARB_FRDDR_A] = 4,
48*4882a593Smuzhiyun [AXG_ARB_FRDDR_B] = 5,
49*4882a593Smuzhiyun [AXG_ARB_FRDDR_C] = 6,
50*4882a593Smuzhiyun [AXG_ARB_TODDR_D] = 3,
51*4882a593Smuzhiyun [AXG_ARB_FRDDR_D] = 7,
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun static const struct meson_audio_arb_match_data sm1_audio_arb_match = {
55*4882a593Smuzhiyun .reset_bits = sm1_audio_arb_reset_bits,
56*4882a593Smuzhiyun .reset_num = ARRAY_SIZE(sm1_audio_arb_reset_bits),
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
meson_audio_arb_update(struct reset_controller_dev * rcdev,unsigned long id,bool assert)59*4882a593Smuzhiyun static int meson_audio_arb_update(struct reset_controller_dev *rcdev,
60*4882a593Smuzhiyun unsigned long id, bool assert)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun u32 val;
63*4882a593Smuzhiyun struct meson_audio_arb_data *arb =
64*4882a593Smuzhiyun container_of(rcdev, struct meson_audio_arb_data, rstc);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun spin_lock(&arb->lock);
67*4882a593Smuzhiyun val = readl(arb->regs);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun if (assert)
70*4882a593Smuzhiyun val &= ~BIT(arb->reset_bits[id]);
71*4882a593Smuzhiyun else
72*4882a593Smuzhiyun val |= BIT(arb->reset_bits[id]);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun writel(val, arb->regs);
75*4882a593Smuzhiyun spin_unlock(&arb->lock);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun return 0;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
meson_audio_arb_status(struct reset_controller_dev * rcdev,unsigned long id)80*4882a593Smuzhiyun static int meson_audio_arb_status(struct reset_controller_dev *rcdev,
81*4882a593Smuzhiyun unsigned long id)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun u32 val;
84*4882a593Smuzhiyun struct meson_audio_arb_data *arb =
85*4882a593Smuzhiyun container_of(rcdev, struct meson_audio_arb_data, rstc);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun val = readl(arb->regs);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun return !(val & BIT(arb->reset_bits[id]));
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
meson_audio_arb_assert(struct reset_controller_dev * rcdev,unsigned long id)92*4882a593Smuzhiyun static int meson_audio_arb_assert(struct reset_controller_dev *rcdev,
93*4882a593Smuzhiyun unsigned long id)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun return meson_audio_arb_update(rcdev, id, true);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
meson_audio_arb_deassert(struct reset_controller_dev * rcdev,unsigned long id)98*4882a593Smuzhiyun static int meson_audio_arb_deassert(struct reset_controller_dev *rcdev,
99*4882a593Smuzhiyun unsigned long id)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun return meson_audio_arb_update(rcdev, id, false);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun static const struct reset_control_ops meson_audio_arb_rstc_ops = {
105*4882a593Smuzhiyun .assert = meson_audio_arb_assert,
106*4882a593Smuzhiyun .deassert = meson_audio_arb_deassert,
107*4882a593Smuzhiyun .status = meson_audio_arb_status,
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun static const struct of_device_id meson_audio_arb_of_match[] = {
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun .compatible = "amlogic,meson-axg-audio-arb",
113*4882a593Smuzhiyun .data = &axg_audio_arb_match,
114*4882a593Smuzhiyun }, {
115*4882a593Smuzhiyun .compatible = "amlogic,meson-sm1-audio-arb",
116*4882a593Smuzhiyun .data = &sm1_audio_arb_match,
117*4882a593Smuzhiyun },
118*4882a593Smuzhiyun {}
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, meson_audio_arb_of_match);
121*4882a593Smuzhiyun
meson_audio_arb_remove(struct platform_device * pdev)122*4882a593Smuzhiyun static int meson_audio_arb_remove(struct platform_device *pdev)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun struct meson_audio_arb_data *arb = platform_get_drvdata(pdev);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun /* Disable all access */
127*4882a593Smuzhiyun spin_lock(&arb->lock);
128*4882a593Smuzhiyun writel(0, arb->regs);
129*4882a593Smuzhiyun spin_unlock(&arb->lock);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun clk_disable_unprepare(arb->clk);
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun return 0;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
meson_audio_arb_probe(struct platform_device * pdev)136*4882a593Smuzhiyun static int meson_audio_arb_probe(struct platform_device *pdev)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun struct device *dev = &pdev->dev;
139*4882a593Smuzhiyun const struct meson_audio_arb_match_data *data;
140*4882a593Smuzhiyun struct meson_audio_arb_data *arb;
141*4882a593Smuzhiyun struct resource *res;
142*4882a593Smuzhiyun int ret;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun data = of_device_get_match_data(dev);
145*4882a593Smuzhiyun if (!data)
146*4882a593Smuzhiyun return -EINVAL;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun arb = devm_kzalloc(dev, sizeof(*arb), GFP_KERNEL);
149*4882a593Smuzhiyun if (!arb)
150*4882a593Smuzhiyun return -ENOMEM;
151*4882a593Smuzhiyun platform_set_drvdata(pdev, arb);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun arb->clk = devm_clk_get(dev, NULL);
154*4882a593Smuzhiyun if (IS_ERR(arb->clk)) {
155*4882a593Smuzhiyun if (PTR_ERR(arb->clk) != -EPROBE_DEFER)
156*4882a593Smuzhiyun dev_err(dev, "failed to get clock\n");
157*4882a593Smuzhiyun return PTR_ERR(arb->clk);
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
161*4882a593Smuzhiyun arb->regs = devm_ioremap_resource(dev, res);
162*4882a593Smuzhiyun if (IS_ERR(arb->regs))
163*4882a593Smuzhiyun return PTR_ERR(arb->regs);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun spin_lock_init(&arb->lock);
166*4882a593Smuzhiyun arb->reset_bits = data->reset_bits;
167*4882a593Smuzhiyun arb->rstc.nr_resets = data->reset_num;
168*4882a593Smuzhiyun arb->rstc.ops = &meson_audio_arb_rstc_ops;
169*4882a593Smuzhiyun arb->rstc.of_node = dev->of_node;
170*4882a593Smuzhiyun arb->rstc.owner = THIS_MODULE;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun /*
173*4882a593Smuzhiyun * Enable general :
174*4882a593Smuzhiyun * In the initial state, all memory interfaces are disabled
175*4882a593Smuzhiyun * and the general bit is on
176*4882a593Smuzhiyun */
177*4882a593Smuzhiyun ret = clk_prepare_enable(arb->clk);
178*4882a593Smuzhiyun if (ret) {
179*4882a593Smuzhiyun dev_err(dev, "failed to enable arb clock\n");
180*4882a593Smuzhiyun return ret;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun writel(BIT(ARB_GENERAL_BIT), arb->regs);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun /* Register reset controller */
185*4882a593Smuzhiyun ret = devm_reset_controller_register(dev, &arb->rstc);
186*4882a593Smuzhiyun if (ret) {
187*4882a593Smuzhiyun dev_err(dev, "failed to register arb reset controller\n");
188*4882a593Smuzhiyun meson_audio_arb_remove(pdev);
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun return ret;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun static struct platform_driver meson_audio_arb_pdrv = {
195*4882a593Smuzhiyun .probe = meson_audio_arb_probe,
196*4882a593Smuzhiyun .remove = meson_audio_arb_remove,
197*4882a593Smuzhiyun .driver = {
198*4882a593Smuzhiyun .name = "meson-audio-arb-reset",
199*4882a593Smuzhiyun .of_match_table = meson_audio_arb_of_match,
200*4882a593Smuzhiyun },
201*4882a593Smuzhiyun };
202*4882a593Smuzhiyun module_platform_driver(meson_audio_arb_pdrv);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun MODULE_DESCRIPTION("Amlogic A113 Audio Memory Arbiter");
205*4882a593Smuzhiyun MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
206*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
207