1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Broadcom STB generic reset controller for SW_INIT style reset controller
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Florian Fainelli <f.fainelli@gmail.com>
6*4882a593Smuzhiyun * Copyright (C) 2018 Broadcom
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #include <linux/delay.h>
9*4882a593Smuzhiyun #include <linux/device.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/of.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/reset-controller.h>
15*4882a593Smuzhiyun #include <linux/types.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun struct brcmstb_reset {
18*4882a593Smuzhiyun void __iomem *base;
19*4882a593Smuzhiyun struct reset_controller_dev rcdev;
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define SW_INIT_SET 0x00
23*4882a593Smuzhiyun #define SW_INIT_CLEAR 0x04
24*4882a593Smuzhiyun #define SW_INIT_STATUS 0x08
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define SW_INIT_BIT(id) BIT((id) & 0x1f)
27*4882a593Smuzhiyun #define SW_INIT_BANK(id) ((id) >> 5)
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* A full bank contains extra registers that we are not utilizing but still
30*4882a593Smuzhiyun * qualify as a single bank.
31*4882a593Smuzhiyun */
32*4882a593Smuzhiyun #define SW_INIT_BANK_SIZE 0x18
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun static inline
to_brcmstb(struct reset_controller_dev * rcdev)35*4882a593Smuzhiyun struct brcmstb_reset *to_brcmstb(struct reset_controller_dev *rcdev)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun return container_of(rcdev, struct brcmstb_reset, rcdev);
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
brcmstb_reset_assert(struct reset_controller_dev * rcdev,unsigned long id)40*4882a593Smuzhiyun static int brcmstb_reset_assert(struct reset_controller_dev *rcdev,
41*4882a593Smuzhiyun unsigned long id)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE;
44*4882a593Smuzhiyun struct brcmstb_reset *priv = to_brcmstb(rcdev);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_SET);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun return 0;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
brcmstb_reset_deassert(struct reset_controller_dev * rcdev,unsigned long id)51*4882a593Smuzhiyun static int brcmstb_reset_deassert(struct reset_controller_dev *rcdev,
52*4882a593Smuzhiyun unsigned long id)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE;
55*4882a593Smuzhiyun struct brcmstb_reset *priv = to_brcmstb(rcdev);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_CLEAR);
58*4882a593Smuzhiyun /* Maximum reset delay after de-asserting a line and seeing block
59*4882a593Smuzhiyun * operation is typically 14us for the worst case, build some slack
60*4882a593Smuzhiyun * here.
61*4882a593Smuzhiyun */
62*4882a593Smuzhiyun usleep_range(100, 200);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return 0;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
brcmstb_reset_status(struct reset_controller_dev * rcdev,unsigned long id)67*4882a593Smuzhiyun static int brcmstb_reset_status(struct reset_controller_dev *rcdev,
68*4882a593Smuzhiyun unsigned long id)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun unsigned int off = SW_INIT_BANK(id) * SW_INIT_BANK_SIZE;
71*4882a593Smuzhiyun struct brcmstb_reset *priv = to_brcmstb(rcdev);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun return readl_relaxed(priv->base + off + SW_INIT_STATUS) &
74*4882a593Smuzhiyun SW_INIT_BIT(id);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun static const struct reset_control_ops brcmstb_reset_ops = {
78*4882a593Smuzhiyun .assert = brcmstb_reset_assert,
79*4882a593Smuzhiyun .deassert = brcmstb_reset_deassert,
80*4882a593Smuzhiyun .status = brcmstb_reset_status,
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun
brcmstb_reset_probe(struct platform_device * pdev)83*4882a593Smuzhiyun static int brcmstb_reset_probe(struct platform_device *pdev)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun struct device *kdev = &pdev->dev;
86*4882a593Smuzhiyun struct brcmstb_reset *priv;
87*4882a593Smuzhiyun struct resource *res;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL);
90*4882a593Smuzhiyun if (!priv)
91*4882a593Smuzhiyun return -ENOMEM;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
94*4882a593Smuzhiyun priv->base = devm_ioremap_resource(kdev, res);
95*4882a593Smuzhiyun if (IS_ERR(priv->base))
96*4882a593Smuzhiyun return PTR_ERR(priv->base);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun dev_set_drvdata(kdev, priv);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun priv->rcdev.owner = THIS_MODULE;
101*4882a593Smuzhiyun priv->rcdev.nr_resets = DIV_ROUND_DOWN_ULL(resource_size(res),
102*4882a593Smuzhiyun SW_INIT_BANK_SIZE) * 32;
103*4882a593Smuzhiyun priv->rcdev.ops = &brcmstb_reset_ops;
104*4882a593Smuzhiyun priv->rcdev.of_node = kdev->of_node;
105*4882a593Smuzhiyun /* Use defaults: 1 cell and simple xlate function */
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun return devm_reset_controller_register(kdev, &priv->rcdev);
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun static const struct of_device_id brcmstb_reset_of_match[] = {
111*4882a593Smuzhiyun { .compatible = "brcm,brcmstb-reset" },
112*4882a593Smuzhiyun { /* sentinel */ }
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, brcmstb_reset_of_match);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun static struct platform_driver brcmstb_reset_driver = {
117*4882a593Smuzhiyun .probe = brcmstb_reset_probe,
118*4882a593Smuzhiyun .driver = {
119*4882a593Smuzhiyun .name = "brcmstb-reset",
120*4882a593Smuzhiyun .of_match_table = brcmstb_reset_of_match,
121*4882a593Smuzhiyun },
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun module_platform_driver(brcmstb_reset_driver);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun MODULE_AUTHOR("Broadcom");
126*4882a593Smuzhiyun MODULE_DESCRIPTION("Broadcom STB reset controller");
127*4882a593Smuzhiyun MODULE_LICENSE("GPL");
128