1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* Copyright (C) 2018-2020 Broadcom */
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <linux/device.h>
5*4882a593Smuzhiyun #include <linux/iopoll.h>
6*4882a593Smuzhiyun #include <linux/module.h>
7*4882a593Smuzhiyun #include <linux/of.h>
8*4882a593Smuzhiyun #include <linux/platform_device.h>
9*4882a593Smuzhiyun #include <linux/reset-controller.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define BRCM_RESCAL_START 0x0
12*4882a593Smuzhiyun #define BRCM_RESCAL_START_BIT BIT(0)
13*4882a593Smuzhiyun #define BRCM_RESCAL_CTRL 0x4
14*4882a593Smuzhiyun #define BRCM_RESCAL_STATUS 0x8
15*4882a593Smuzhiyun #define BRCM_RESCAL_STATUS_BIT BIT(0)
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun struct brcm_rescal_reset {
18*4882a593Smuzhiyun void __iomem *base;
19*4882a593Smuzhiyun struct device *dev;
20*4882a593Smuzhiyun struct reset_controller_dev rcdev;
21*4882a593Smuzhiyun };
22*4882a593Smuzhiyun
brcm_rescal_reset_set(struct reset_controller_dev * rcdev,unsigned long id)23*4882a593Smuzhiyun static int brcm_rescal_reset_set(struct reset_controller_dev *rcdev,
24*4882a593Smuzhiyun unsigned long id)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun struct brcm_rescal_reset *data =
27*4882a593Smuzhiyun container_of(rcdev, struct brcm_rescal_reset, rcdev);
28*4882a593Smuzhiyun void __iomem *base = data->base;
29*4882a593Smuzhiyun u32 reg;
30*4882a593Smuzhiyun int ret;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun reg = readl(base + BRCM_RESCAL_START);
33*4882a593Smuzhiyun writel(reg | BRCM_RESCAL_START_BIT, base + BRCM_RESCAL_START);
34*4882a593Smuzhiyun reg = readl(base + BRCM_RESCAL_START);
35*4882a593Smuzhiyun if (!(reg & BRCM_RESCAL_START_BIT)) {
36*4882a593Smuzhiyun dev_err(data->dev, "failed to start SATA/PCIe rescal\n");
37*4882a593Smuzhiyun return -EIO;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun ret = readl_poll_timeout(base + BRCM_RESCAL_STATUS, reg,
41*4882a593Smuzhiyun (reg & BRCM_RESCAL_STATUS_BIT), 100, 1000);
42*4882a593Smuzhiyun if (ret) {
43*4882a593Smuzhiyun dev_err(data->dev, "time out on SATA/PCIe rescal\n");
44*4882a593Smuzhiyun return ret;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun reg = readl(base + BRCM_RESCAL_START);
48*4882a593Smuzhiyun writel(reg & ~BRCM_RESCAL_START_BIT, base + BRCM_RESCAL_START);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun dev_dbg(data->dev, "SATA/PCIe rescal success\n");
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun return 0;
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
brcm_rescal_reset_xlate(struct reset_controller_dev * rcdev,const struct of_phandle_args * reset_spec)55*4882a593Smuzhiyun static int brcm_rescal_reset_xlate(struct reset_controller_dev *rcdev,
56*4882a593Smuzhiyun const struct of_phandle_args *reset_spec)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun /* This is needed if #reset-cells == 0. */
59*4882a593Smuzhiyun return 0;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun static const struct reset_control_ops brcm_rescal_reset_ops = {
63*4882a593Smuzhiyun .reset = brcm_rescal_reset_set,
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
brcm_rescal_reset_probe(struct platform_device * pdev)66*4882a593Smuzhiyun static int brcm_rescal_reset_probe(struct platform_device *pdev)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun struct brcm_rescal_reset *data;
69*4882a593Smuzhiyun struct resource *res;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
72*4882a593Smuzhiyun if (!data)
73*4882a593Smuzhiyun return -ENOMEM;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
76*4882a593Smuzhiyun data->base = devm_ioremap_resource(&pdev->dev, res);
77*4882a593Smuzhiyun if (IS_ERR(data->base))
78*4882a593Smuzhiyun return PTR_ERR(data->base);
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun data->rcdev.owner = THIS_MODULE;
81*4882a593Smuzhiyun data->rcdev.nr_resets = 1;
82*4882a593Smuzhiyun data->rcdev.ops = &brcm_rescal_reset_ops;
83*4882a593Smuzhiyun data->rcdev.of_node = pdev->dev.of_node;
84*4882a593Smuzhiyun data->rcdev.of_xlate = brcm_rescal_reset_xlate;
85*4882a593Smuzhiyun data->dev = &pdev->dev;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun return devm_reset_controller_register(&pdev->dev, &data->rcdev);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun static const struct of_device_id brcm_rescal_reset_of_match[] = {
91*4882a593Smuzhiyun { .compatible = "brcm,bcm7216-pcie-sata-rescal" },
92*4882a593Smuzhiyun { },
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, brcm_rescal_reset_of_match);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun static struct platform_driver brcm_rescal_reset_driver = {
97*4882a593Smuzhiyun .probe = brcm_rescal_reset_probe,
98*4882a593Smuzhiyun .driver = {
99*4882a593Smuzhiyun .name = "brcm-rescal-reset",
100*4882a593Smuzhiyun .of_match_table = brcm_rescal_reset_of_match,
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun module_platform_driver(brcm_rescal_reset_driver);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun MODULE_AUTHOR("Broadcom");
106*4882a593Smuzhiyun MODULE_DESCRIPTION("Broadcom SATA/PCIe rescal reset controller");
107*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
108