1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2016-2017 Linaro Ltd.
4*4882a593Smuzhiyun * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun #include <linux/kernel.h>
7*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/of_device.h>
10*4882a593Smuzhiyun #include <linux/platform_device.h>
11*4882a593Smuzhiyun #include <linux/regmap.h>
12*4882a593Smuzhiyun #include <linux/reset-controller.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun struct hi3660_reset_controller {
15*4882a593Smuzhiyun struct reset_controller_dev rst;
16*4882a593Smuzhiyun struct regmap *map;
17*4882a593Smuzhiyun };
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define to_hi3660_reset_controller(_rst) \
20*4882a593Smuzhiyun container_of(_rst, struct hi3660_reset_controller, rst)
21*4882a593Smuzhiyun
hi3660_reset_program_hw(struct reset_controller_dev * rcdev,unsigned long idx,bool assert)22*4882a593Smuzhiyun static int hi3660_reset_program_hw(struct reset_controller_dev *rcdev,
23*4882a593Smuzhiyun unsigned long idx, bool assert)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun struct hi3660_reset_controller *rc = to_hi3660_reset_controller(rcdev);
26*4882a593Smuzhiyun unsigned int offset = idx >> 8;
27*4882a593Smuzhiyun unsigned int mask = BIT(idx & 0x1f);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun if (assert)
30*4882a593Smuzhiyun return regmap_write(rc->map, offset, mask);
31*4882a593Smuzhiyun else
32*4882a593Smuzhiyun return regmap_write(rc->map, offset + 4, mask);
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
hi3660_reset_assert(struct reset_controller_dev * rcdev,unsigned long idx)35*4882a593Smuzhiyun static int hi3660_reset_assert(struct reset_controller_dev *rcdev,
36*4882a593Smuzhiyun unsigned long idx)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun return hi3660_reset_program_hw(rcdev, idx, true);
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
hi3660_reset_deassert(struct reset_controller_dev * rcdev,unsigned long idx)41*4882a593Smuzhiyun static int hi3660_reset_deassert(struct reset_controller_dev *rcdev,
42*4882a593Smuzhiyun unsigned long idx)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun return hi3660_reset_program_hw(rcdev, idx, false);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
hi3660_reset_dev(struct reset_controller_dev * rcdev,unsigned long idx)47*4882a593Smuzhiyun static int hi3660_reset_dev(struct reset_controller_dev *rcdev,
48*4882a593Smuzhiyun unsigned long idx)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun int err;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun err = hi3660_reset_assert(rcdev, idx);
53*4882a593Smuzhiyun if (err)
54*4882a593Smuzhiyun return err;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun return hi3660_reset_deassert(rcdev, idx);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static const struct reset_control_ops hi3660_reset_ops = {
60*4882a593Smuzhiyun .reset = hi3660_reset_dev,
61*4882a593Smuzhiyun .assert = hi3660_reset_assert,
62*4882a593Smuzhiyun .deassert = hi3660_reset_deassert,
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
hi3660_reset_xlate(struct reset_controller_dev * rcdev,const struct of_phandle_args * reset_spec)65*4882a593Smuzhiyun static int hi3660_reset_xlate(struct reset_controller_dev *rcdev,
66*4882a593Smuzhiyun const struct of_phandle_args *reset_spec)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun unsigned int offset, bit;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun offset = reset_spec->args[0];
71*4882a593Smuzhiyun bit = reset_spec->args[1];
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun return (offset << 8) | bit;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
hi3660_reset_probe(struct platform_device * pdev)76*4882a593Smuzhiyun static int hi3660_reset_probe(struct platform_device *pdev)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun struct hi3660_reset_controller *rc;
79*4882a593Smuzhiyun struct device_node *np = pdev->dev.of_node;
80*4882a593Smuzhiyun struct device *dev = &pdev->dev;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun rc = devm_kzalloc(dev, sizeof(*rc), GFP_KERNEL);
83*4882a593Smuzhiyun if (!rc)
84*4882a593Smuzhiyun return -ENOMEM;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun rc->map = syscon_regmap_lookup_by_phandle(np, "hisi,rst-syscon");
87*4882a593Smuzhiyun if (IS_ERR(rc->map)) {
88*4882a593Smuzhiyun dev_err(dev, "failed to get hi3660,rst-syscon\n");
89*4882a593Smuzhiyun return PTR_ERR(rc->map);
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun rc->rst.ops = &hi3660_reset_ops,
93*4882a593Smuzhiyun rc->rst.of_node = np;
94*4882a593Smuzhiyun rc->rst.of_reset_n_cells = 2;
95*4882a593Smuzhiyun rc->rst.of_xlate = hi3660_reset_xlate;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun return reset_controller_register(&rc->rst);
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun static const struct of_device_id hi3660_reset_match[] = {
101*4882a593Smuzhiyun { .compatible = "hisilicon,hi3660-reset", },
102*4882a593Smuzhiyun {},
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, hi3660_reset_match);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun static struct platform_driver hi3660_reset_driver = {
107*4882a593Smuzhiyun .probe = hi3660_reset_probe,
108*4882a593Smuzhiyun .driver = {
109*4882a593Smuzhiyun .name = "hi3660-reset",
110*4882a593Smuzhiyun .of_match_table = hi3660_reset_match,
111*4882a593Smuzhiyun },
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun
hi3660_reset_init(void)114*4882a593Smuzhiyun static int __init hi3660_reset_init(void)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun return platform_driver_register(&hi3660_reset_driver);
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun arch_initcall(hi3660_reset_init);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun MODULE_LICENSE("GPL");
121*4882a593Smuzhiyun MODULE_ALIAS("platform:hi3660-reset");
122*4882a593Smuzhiyun MODULE_DESCRIPTION("HiSilicon Hi3660 Reset Driver");
123