1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
4*4882a593Smuzhiyun * Authors: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5*4882a593Smuzhiyun * Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/arm-smccc.h>
9*4882a593Smuzhiyun #include <linux/dma-mapping.h>
10*4882a593Smuzhiyun #include <linux/interrupt.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/mailbox_client.h>
13*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/of_address.h>
16*4882a593Smuzhiyun #include <linux/of_device.h>
17*4882a593Smuzhiyun #include <linux/of_reserved_mem.h>
18*4882a593Smuzhiyun #include <linux/pm_wakeirq.h>
19*4882a593Smuzhiyun #include <linux/regmap.h>
20*4882a593Smuzhiyun #include <linux/remoteproc.h>
21*4882a593Smuzhiyun #include <linux/reset.h>
22*4882a593Smuzhiyun #include <linux/slab.h>
23*4882a593Smuzhiyun #include <linux/workqueue.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #include "remoteproc_internal.h"
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define HOLD_BOOT 0
28*4882a593Smuzhiyun #define RELEASE_BOOT 1
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define MBOX_NB_VQ 2
31*4882a593Smuzhiyun #define MBOX_NB_MBX 3
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define STM32_SMC_RCC 0x82001000
34*4882a593Smuzhiyun #define STM32_SMC_REG_WRITE 0x1
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define STM32_MBX_VQ0 "vq0"
37*4882a593Smuzhiyun #define STM32_MBX_VQ0_ID 0
38*4882a593Smuzhiyun #define STM32_MBX_VQ1 "vq1"
39*4882a593Smuzhiyun #define STM32_MBX_VQ1_ID 1
40*4882a593Smuzhiyun #define STM32_MBX_SHUTDOWN "shutdown"
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define RSC_TBL_SIZE 1024
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define M4_STATE_OFF 0
45*4882a593Smuzhiyun #define M4_STATE_INI 1
46*4882a593Smuzhiyun #define M4_STATE_CRUN 2
47*4882a593Smuzhiyun #define M4_STATE_CSTOP 3
48*4882a593Smuzhiyun #define M4_STATE_STANDBY 4
49*4882a593Smuzhiyun #define M4_STATE_CRASH 5
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun struct stm32_syscon {
52*4882a593Smuzhiyun struct regmap *map;
53*4882a593Smuzhiyun u32 reg;
54*4882a593Smuzhiyun u32 mask;
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun struct stm32_rproc_mem {
58*4882a593Smuzhiyun char name[20];
59*4882a593Smuzhiyun void __iomem *cpu_addr;
60*4882a593Smuzhiyun phys_addr_t bus_addr;
61*4882a593Smuzhiyun u32 dev_addr;
62*4882a593Smuzhiyun size_t size;
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun struct stm32_rproc_mem_ranges {
66*4882a593Smuzhiyun u32 dev_addr;
67*4882a593Smuzhiyun u32 bus_addr;
68*4882a593Smuzhiyun u32 size;
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun struct stm32_mbox {
72*4882a593Smuzhiyun const unsigned char name[10];
73*4882a593Smuzhiyun struct mbox_chan *chan;
74*4882a593Smuzhiyun struct mbox_client client;
75*4882a593Smuzhiyun struct work_struct vq_work;
76*4882a593Smuzhiyun int vq_id;
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun struct stm32_rproc {
80*4882a593Smuzhiyun struct reset_control *rst;
81*4882a593Smuzhiyun struct stm32_syscon hold_boot;
82*4882a593Smuzhiyun struct stm32_syscon pdds;
83*4882a593Smuzhiyun struct stm32_syscon m4_state;
84*4882a593Smuzhiyun struct stm32_syscon rsctbl;
85*4882a593Smuzhiyun int wdg_irq;
86*4882a593Smuzhiyun u32 nb_rmems;
87*4882a593Smuzhiyun struct stm32_rproc_mem *rmems;
88*4882a593Smuzhiyun struct stm32_mbox mb[MBOX_NB_MBX];
89*4882a593Smuzhiyun struct workqueue_struct *workqueue;
90*4882a593Smuzhiyun bool secured_soc;
91*4882a593Smuzhiyun void __iomem *rsc_va;
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
stm32_rproc_pa_to_da(struct rproc * rproc,phys_addr_t pa,u64 * da)94*4882a593Smuzhiyun static int stm32_rproc_pa_to_da(struct rproc *rproc, phys_addr_t pa, u64 *da)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun unsigned int i;
97*4882a593Smuzhiyun struct stm32_rproc *ddata = rproc->priv;
98*4882a593Smuzhiyun struct stm32_rproc_mem *p_mem;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun for (i = 0; i < ddata->nb_rmems; i++) {
101*4882a593Smuzhiyun p_mem = &ddata->rmems[i];
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun if (pa < p_mem->bus_addr ||
104*4882a593Smuzhiyun pa >= p_mem->bus_addr + p_mem->size)
105*4882a593Smuzhiyun continue;
106*4882a593Smuzhiyun *da = pa - p_mem->bus_addr + p_mem->dev_addr;
107*4882a593Smuzhiyun dev_dbg(rproc->dev.parent, "pa %pa to da %llx\n", &pa, *da);
108*4882a593Smuzhiyun return 0;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun return -EINVAL;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
stm32_rproc_mem_alloc(struct rproc * rproc,struct rproc_mem_entry * mem)114*4882a593Smuzhiyun static int stm32_rproc_mem_alloc(struct rproc *rproc,
115*4882a593Smuzhiyun struct rproc_mem_entry *mem)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun struct device *dev = rproc->dev.parent;
118*4882a593Smuzhiyun void *va;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun dev_dbg(dev, "map memory: %pa+%x\n", &mem->dma, mem->len);
121*4882a593Smuzhiyun va = ioremap_wc(mem->dma, mem->len);
122*4882a593Smuzhiyun if (IS_ERR_OR_NULL(va)) {
123*4882a593Smuzhiyun dev_err(dev, "Unable to map memory region: %pa+%x\n",
124*4882a593Smuzhiyun &mem->dma, mem->len);
125*4882a593Smuzhiyun return -ENOMEM;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun /* Update memory entry va */
129*4882a593Smuzhiyun mem->va = va;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun return 0;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
stm32_rproc_mem_release(struct rproc * rproc,struct rproc_mem_entry * mem)134*4882a593Smuzhiyun static int stm32_rproc_mem_release(struct rproc *rproc,
135*4882a593Smuzhiyun struct rproc_mem_entry *mem)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun dev_dbg(rproc->dev.parent, "unmap memory: %pa\n", &mem->dma);
138*4882a593Smuzhiyun iounmap(mem->va);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun return 0;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
stm32_rproc_of_memory_translations(struct platform_device * pdev,struct stm32_rproc * ddata)143*4882a593Smuzhiyun static int stm32_rproc_of_memory_translations(struct platform_device *pdev,
144*4882a593Smuzhiyun struct stm32_rproc *ddata)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun struct device *parent, *dev = &pdev->dev;
147*4882a593Smuzhiyun struct device_node *np;
148*4882a593Smuzhiyun struct stm32_rproc_mem *p_mems;
149*4882a593Smuzhiyun struct stm32_rproc_mem_ranges *mem_range;
150*4882a593Smuzhiyun int cnt, array_size, i, ret = 0;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun parent = dev->parent;
153*4882a593Smuzhiyun np = parent->of_node;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun cnt = of_property_count_elems_of_size(np, "dma-ranges",
156*4882a593Smuzhiyun sizeof(*mem_range));
157*4882a593Smuzhiyun if (cnt <= 0) {
158*4882a593Smuzhiyun dev_err(dev, "%s: dma-ranges property not defined\n", __func__);
159*4882a593Smuzhiyun return -EINVAL;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun p_mems = devm_kcalloc(dev, cnt, sizeof(*p_mems), GFP_KERNEL);
163*4882a593Smuzhiyun if (!p_mems)
164*4882a593Smuzhiyun return -ENOMEM;
165*4882a593Smuzhiyun mem_range = kcalloc(cnt, sizeof(*mem_range), GFP_KERNEL);
166*4882a593Smuzhiyun if (!mem_range)
167*4882a593Smuzhiyun return -ENOMEM;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun array_size = cnt * sizeof(struct stm32_rproc_mem_ranges) / sizeof(u32);
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun ret = of_property_read_u32_array(np, "dma-ranges",
172*4882a593Smuzhiyun (u32 *)mem_range, array_size);
173*4882a593Smuzhiyun if (ret) {
174*4882a593Smuzhiyun dev_err(dev, "error while get dma-ranges property: %x\n", ret);
175*4882a593Smuzhiyun goto free_mem;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun for (i = 0; i < cnt; i++) {
179*4882a593Smuzhiyun p_mems[i].bus_addr = mem_range[i].bus_addr;
180*4882a593Smuzhiyun p_mems[i].dev_addr = mem_range[i].dev_addr;
181*4882a593Smuzhiyun p_mems[i].size = mem_range[i].size;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun dev_dbg(dev, "memory range[%i]: da %#x, pa %pa, size %#zx:\n",
184*4882a593Smuzhiyun i, p_mems[i].dev_addr, &p_mems[i].bus_addr,
185*4882a593Smuzhiyun p_mems[i].size);
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun ddata->rmems = p_mems;
189*4882a593Smuzhiyun ddata->nb_rmems = cnt;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun free_mem:
192*4882a593Smuzhiyun kfree(mem_range);
193*4882a593Smuzhiyun return ret;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
stm32_rproc_mbox_idx(struct rproc * rproc,const unsigned char * name)196*4882a593Smuzhiyun static int stm32_rproc_mbox_idx(struct rproc *rproc, const unsigned char *name)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun struct stm32_rproc *ddata = rproc->priv;
199*4882a593Smuzhiyun int i;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(ddata->mb); i++) {
202*4882a593Smuzhiyun if (!strncmp(ddata->mb[i].name, name, strlen(name)))
203*4882a593Smuzhiyun return i;
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun dev_err(&rproc->dev, "mailbox %s not found\n", name);
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun return -EINVAL;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
stm32_rproc_elf_load_rsc_table(struct rproc * rproc,const struct firmware * fw)210*4882a593Smuzhiyun static int stm32_rproc_elf_load_rsc_table(struct rproc *rproc,
211*4882a593Smuzhiyun const struct firmware *fw)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun if (rproc_elf_load_rsc_table(rproc, fw))
214*4882a593Smuzhiyun dev_warn(&rproc->dev, "no resource table found for this firmware\n");
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun return 0;
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun
stm32_rproc_parse_memory_regions(struct rproc * rproc)219*4882a593Smuzhiyun static int stm32_rproc_parse_memory_regions(struct rproc *rproc)
220*4882a593Smuzhiyun {
221*4882a593Smuzhiyun struct device *dev = rproc->dev.parent;
222*4882a593Smuzhiyun struct device_node *np = dev->of_node;
223*4882a593Smuzhiyun struct of_phandle_iterator it;
224*4882a593Smuzhiyun struct rproc_mem_entry *mem;
225*4882a593Smuzhiyun struct reserved_mem *rmem;
226*4882a593Smuzhiyun u64 da;
227*4882a593Smuzhiyun int index = 0;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun /* Register associated reserved memory regions */
230*4882a593Smuzhiyun of_phandle_iterator_init(&it, np, "memory-region", NULL, 0);
231*4882a593Smuzhiyun while (of_phandle_iterator_next(&it) == 0) {
232*4882a593Smuzhiyun rmem = of_reserved_mem_lookup(it.node);
233*4882a593Smuzhiyun if (!rmem) {
234*4882a593Smuzhiyun dev_err(dev, "unable to acquire memory-region\n");
235*4882a593Smuzhiyun return -EINVAL;
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun if (stm32_rproc_pa_to_da(rproc, rmem->base, &da) < 0) {
239*4882a593Smuzhiyun dev_err(dev, "memory region not valid %pa\n",
240*4882a593Smuzhiyun &rmem->base);
241*4882a593Smuzhiyun return -EINVAL;
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun /* No need to map vdev buffer */
245*4882a593Smuzhiyun if (strcmp(it.node->name, "vdev0buffer")) {
246*4882a593Smuzhiyun /* Register memory region */
247*4882a593Smuzhiyun mem = rproc_mem_entry_init(dev, NULL,
248*4882a593Smuzhiyun (dma_addr_t)rmem->base,
249*4882a593Smuzhiyun rmem->size, da,
250*4882a593Smuzhiyun stm32_rproc_mem_alloc,
251*4882a593Smuzhiyun stm32_rproc_mem_release,
252*4882a593Smuzhiyun it.node->name);
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun if (mem)
255*4882a593Smuzhiyun rproc_coredump_add_segment(rproc, da,
256*4882a593Smuzhiyun rmem->size);
257*4882a593Smuzhiyun } else {
258*4882a593Smuzhiyun /* Register reserved memory for vdev buffer alloc */
259*4882a593Smuzhiyun mem = rproc_of_resm_mem_entry_init(dev, index,
260*4882a593Smuzhiyun rmem->size,
261*4882a593Smuzhiyun rmem->base,
262*4882a593Smuzhiyun it.node->name);
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun if (!mem)
266*4882a593Smuzhiyun return -ENOMEM;
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun rproc_add_carveout(rproc, mem);
269*4882a593Smuzhiyun index++;
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun return 0;
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun
stm32_rproc_parse_fw(struct rproc * rproc,const struct firmware * fw)275*4882a593Smuzhiyun static int stm32_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw)
276*4882a593Smuzhiyun {
277*4882a593Smuzhiyun int ret = stm32_rproc_parse_memory_regions(rproc);
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun if (ret)
280*4882a593Smuzhiyun return ret;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun return stm32_rproc_elf_load_rsc_table(rproc, fw);
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun
stm32_rproc_wdg(int irq,void * data)285*4882a593Smuzhiyun static irqreturn_t stm32_rproc_wdg(int irq, void *data)
286*4882a593Smuzhiyun {
287*4882a593Smuzhiyun struct platform_device *pdev = data;
288*4882a593Smuzhiyun struct rproc *rproc = platform_get_drvdata(pdev);
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun rproc_report_crash(rproc, RPROC_WATCHDOG);
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun return IRQ_HANDLED;
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun
stm32_rproc_mb_vq_work(struct work_struct * work)295*4882a593Smuzhiyun static void stm32_rproc_mb_vq_work(struct work_struct *work)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun struct stm32_mbox *mb = container_of(work, struct stm32_mbox, vq_work);
298*4882a593Smuzhiyun struct rproc *rproc = dev_get_drvdata(mb->client.dev);
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun if (rproc_vq_interrupt(rproc, mb->vq_id) == IRQ_NONE)
301*4882a593Smuzhiyun dev_dbg(&rproc->dev, "no message found in vq%d\n", mb->vq_id);
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun
stm32_rproc_mb_callback(struct mbox_client * cl,void * data)304*4882a593Smuzhiyun static void stm32_rproc_mb_callback(struct mbox_client *cl, void *data)
305*4882a593Smuzhiyun {
306*4882a593Smuzhiyun struct rproc *rproc = dev_get_drvdata(cl->dev);
307*4882a593Smuzhiyun struct stm32_mbox *mb = container_of(cl, struct stm32_mbox, client);
308*4882a593Smuzhiyun struct stm32_rproc *ddata = rproc->priv;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun queue_work(ddata->workqueue, &mb->vq_work);
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun
stm32_rproc_free_mbox(struct rproc * rproc)313*4882a593Smuzhiyun static void stm32_rproc_free_mbox(struct rproc *rproc)
314*4882a593Smuzhiyun {
315*4882a593Smuzhiyun struct stm32_rproc *ddata = rproc->priv;
316*4882a593Smuzhiyun unsigned int i;
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(ddata->mb); i++) {
319*4882a593Smuzhiyun if (ddata->mb[i].chan)
320*4882a593Smuzhiyun mbox_free_channel(ddata->mb[i].chan);
321*4882a593Smuzhiyun ddata->mb[i].chan = NULL;
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun static const struct stm32_mbox stm32_rproc_mbox[MBOX_NB_MBX] = {
326*4882a593Smuzhiyun {
327*4882a593Smuzhiyun .name = STM32_MBX_VQ0,
328*4882a593Smuzhiyun .vq_id = STM32_MBX_VQ0_ID,
329*4882a593Smuzhiyun .client = {
330*4882a593Smuzhiyun .rx_callback = stm32_rproc_mb_callback,
331*4882a593Smuzhiyun .tx_block = false,
332*4882a593Smuzhiyun },
333*4882a593Smuzhiyun },
334*4882a593Smuzhiyun {
335*4882a593Smuzhiyun .name = STM32_MBX_VQ1,
336*4882a593Smuzhiyun .vq_id = STM32_MBX_VQ1_ID,
337*4882a593Smuzhiyun .client = {
338*4882a593Smuzhiyun .rx_callback = stm32_rproc_mb_callback,
339*4882a593Smuzhiyun .tx_block = false,
340*4882a593Smuzhiyun },
341*4882a593Smuzhiyun },
342*4882a593Smuzhiyun {
343*4882a593Smuzhiyun .name = STM32_MBX_SHUTDOWN,
344*4882a593Smuzhiyun .vq_id = -1,
345*4882a593Smuzhiyun .client = {
346*4882a593Smuzhiyun .tx_block = true,
347*4882a593Smuzhiyun .tx_done = NULL,
348*4882a593Smuzhiyun .tx_tout = 500, /* 500 ms time out */
349*4882a593Smuzhiyun },
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun };
352*4882a593Smuzhiyun
stm32_rproc_request_mbox(struct rproc * rproc)353*4882a593Smuzhiyun static int stm32_rproc_request_mbox(struct rproc *rproc)
354*4882a593Smuzhiyun {
355*4882a593Smuzhiyun struct stm32_rproc *ddata = rproc->priv;
356*4882a593Smuzhiyun struct device *dev = &rproc->dev;
357*4882a593Smuzhiyun unsigned int i;
358*4882a593Smuzhiyun int j;
359*4882a593Smuzhiyun const unsigned char *name;
360*4882a593Smuzhiyun struct mbox_client *cl;
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun /* Initialise mailbox structure table */
363*4882a593Smuzhiyun memcpy(ddata->mb, stm32_rproc_mbox, sizeof(stm32_rproc_mbox));
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun for (i = 0; i < MBOX_NB_MBX; i++) {
366*4882a593Smuzhiyun name = ddata->mb[i].name;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun cl = &ddata->mb[i].client;
369*4882a593Smuzhiyun cl->dev = dev->parent;
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun ddata->mb[i].chan = mbox_request_channel_byname(cl, name);
372*4882a593Smuzhiyun if (IS_ERR(ddata->mb[i].chan)) {
373*4882a593Smuzhiyun if (PTR_ERR(ddata->mb[i].chan) == -EPROBE_DEFER)
374*4882a593Smuzhiyun goto err_probe;
375*4882a593Smuzhiyun dev_warn(dev, "cannot get %s mbox\n", name);
376*4882a593Smuzhiyun ddata->mb[i].chan = NULL;
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun if (ddata->mb[i].vq_id >= 0) {
379*4882a593Smuzhiyun INIT_WORK(&ddata->mb[i].vq_work,
380*4882a593Smuzhiyun stm32_rproc_mb_vq_work);
381*4882a593Smuzhiyun }
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun return 0;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun err_probe:
387*4882a593Smuzhiyun for (j = i - 1; j >= 0; j--)
388*4882a593Smuzhiyun if (ddata->mb[j].chan)
389*4882a593Smuzhiyun mbox_free_channel(ddata->mb[j].chan);
390*4882a593Smuzhiyun return -EPROBE_DEFER;
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun
stm32_rproc_set_hold_boot(struct rproc * rproc,bool hold)393*4882a593Smuzhiyun static int stm32_rproc_set_hold_boot(struct rproc *rproc, bool hold)
394*4882a593Smuzhiyun {
395*4882a593Smuzhiyun struct stm32_rproc *ddata = rproc->priv;
396*4882a593Smuzhiyun struct stm32_syscon hold_boot = ddata->hold_boot;
397*4882a593Smuzhiyun struct arm_smccc_res smc_res;
398*4882a593Smuzhiyun int val, err;
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun val = hold ? HOLD_BOOT : RELEASE_BOOT;
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_HAVE_ARM_SMCCC) && ddata->secured_soc) {
403*4882a593Smuzhiyun arm_smccc_smc(STM32_SMC_RCC, STM32_SMC_REG_WRITE,
404*4882a593Smuzhiyun hold_boot.reg, val, 0, 0, 0, 0, &smc_res);
405*4882a593Smuzhiyun err = smc_res.a0;
406*4882a593Smuzhiyun } else {
407*4882a593Smuzhiyun err = regmap_update_bits(hold_boot.map, hold_boot.reg,
408*4882a593Smuzhiyun hold_boot.mask, val);
409*4882a593Smuzhiyun }
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun if (err)
412*4882a593Smuzhiyun dev_err(&rproc->dev, "failed to set hold boot\n");
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun return err;
415*4882a593Smuzhiyun }
416*4882a593Smuzhiyun
stm32_rproc_add_coredump_trace(struct rproc * rproc)417*4882a593Smuzhiyun static void stm32_rproc_add_coredump_trace(struct rproc *rproc)
418*4882a593Smuzhiyun {
419*4882a593Smuzhiyun struct rproc_debug_trace *trace;
420*4882a593Smuzhiyun struct rproc_dump_segment *segment;
421*4882a593Smuzhiyun bool already_added;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun list_for_each_entry(trace, &rproc->traces, node) {
424*4882a593Smuzhiyun already_added = false;
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun list_for_each_entry(segment, &rproc->dump_segments, node) {
427*4882a593Smuzhiyun if (segment->da == trace->trace_mem.da) {
428*4882a593Smuzhiyun already_added = true;
429*4882a593Smuzhiyun break;
430*4882a593Smuzhiyun }
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun if (!already_added)
434*4882a593Smuzhiyun rproc_coredump_add_segment(rproc, trace->trace_mem.da,
435*4882a593Smuzhiyun trace->trace_mem.len);
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun }
438*4882a593Smuzhiyun
stm32_rproc_start(struct rproc * rproc)439*4882a593Smuzhiyun static int stm32_rproc_start(struct rproc *rproc)
440*4882a593Smuzhiyun {
441*4882a593Smuzhiyun struct stm32_rproc *ddata = rproc->priv;
442*4882a593Smuzhiyun int err;
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun stm32_rproc_add_coredump_trace(rproc);
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun /* clear remote proc Deep Sleep */
447*4882a593Smuzhiyun if (ddata->pdds.map) {
448*4882a593Smuzhiyun err = regmap_update_bits(ddata->pdds.map, ddata->pdds.reg,
449*4882a593Smuzhiyun ddata->pdds.mask, 0);
450*4882a593Smuzhiyun if (err) {
451*4882a593Smuzhiyun dev_err(&rproc->dev, "failed to clear pdds\n");
452*4882a593Smuzhiyun return err;
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun err = stm32_rproc_set_hold_boot(rproc, false);
457*4882a593Smuzhiyun if (err)
458*4882a593Smuzhiyun return err;
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun return stm32_rproc_set_hold_boot(rproc, true);
461*4882a593Smuzhiyun }
462*4882a593Smuzhiyun
stm32_rproc_attach(struct rproc * rproc)463*4882a593Smuzhiyun static int stm32_rproc_attach(struct rproc *rproc)
464*4882a593Smuzhiyun {
465*4882a593Smuzhiyun stm32_rproc_add_coredump_trace(rproc);
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun return stm32_rproc_set_hold_boot(rproc, true);
468*4882a593Smuzhiyun }
469*4882a593Smuzhiyun
stm32_rproc_stop(struct rproc * rproc)470*4882a593Smuzhiyun static int stm32_rproc_stop(struct rproc *rproc)
471*4882a593Smuzhiyun {
472*4882a593Smuzhiyun struct stm32_rproc *ddata = rproc->priv;
473*4882a593Smuzhiyun int err, dummy_data, idx;
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun /* request shutdown of the remote processor */
476*4882a593Smuzhiyun if (rproc->state != RPROC_OFFLINE) {
477*4882a593Smuzhiyun idx = stm32_rproc_mbox_idx(rproc, STM32_MBX_SHUTDOWN);
478*4882a593Smuzhiyun if (idx >= 0 && ddata->mb[idx].chan) {
479*4882a593Smuzhiyun /* a dummy data is sent to allow to block on transmit */
480*4882a593Smuzhiyun err = mbox_send_message(ddata->mb[idx].chan,
481*4882a593Smuzhiyun &dummy_data);
482*4882a593Smuzhiyun if (err < 0)
483*4882a593Smuzhiyun dev_warn(&rproc->dev, "warning: remote FW shutdown without ack\n");
484*4882a593Smuzhiyun }
485*4882a593Smuzhiyun }
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun err = stm32_rproc_set_hold_boot(rproc, true);
488*4882a593Smuzhiyun if (err)
489*4882a593Smuzhiyun return err;
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun err = reset_control_assert(ddata->rst);
492*4882a593Smuzhiyun if (err) {
493*4882a593Smuzhiyun dev_err(&rproc->dev, "failed to assert the reset\n");
494*4882a593Smuzhiyun return err;
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun /* to allow platform Standby power mode, set remote proc Deep Sleep */
498*4882a593Smuzhiyun if (ddata->pdds.map) {
499*4882a593Smuzhiyun err = regmap_update_bits(ddata->pdds.map, ddata->pdds.reg,
500*4882a593Smuzhiyun ddata->pdds.mask, 1);
501*4882a593Smuzhiyun if (err) {
502*4882a593Smuzhiyun dev_err(&rproc->dev, "failed to set pdds\n");
503*4882a593Smuzhiyun return err;
504*4882a593Smuzhiyun }
505*4882a593Smuzhiyun }
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun /* update coprocessor state to OFF if available */
508*4882a593Smuzhiyun if (ddata->m4_state.map) {
509*4882a593Smuzhiyun err = regmap_update_bits(ddata->m4_state.map,
510*4882a593Smuzhiyun ddata->m4_state.reg,
511*4882a593Smuzhiyun ddata->m4_state.mask,
512*4882a593Smuzhiyun M4_STATE_OFF);
513*4882a593Smuzhiyun if (err) {
514*4882a593Smuzhiyun dev_err(&rproc->dev, "failed to set copro state\n");
515*4882a593Smuzhiyun return err;
516*4882a593Smuzhiyun }
517*4882a593Smuzhiyun }
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun return 0;
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun
stm32_rproc_kick(struct rproc * rproc,int vqid)522*4882a593Smuzhiyun static void stm32_rproc_kick(struct rproc *rproc, int vqid)
523*4882a593Smuzhiyun {
524*4882a593Smuzhiyun struct stm32_rproc *ddata = rproc->priv;
525*4882a593Smuzhiyun unsigned int i;
526*4882a593Smuzhiyun int err;
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun if (WARN_ON(vqid >= MBOX_NB_VQ))
529*4882a593Smuzhiyun return;
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun for (i = 0; i < MBOX_NB_MBX; i++) {
532*4882a593Smuzhiyun if (vqid != ddata->mb[i].vq_id)
533*4882a593Smuzhiyun continue;
534*4882a593Smuzhiyun if (!ddata->mb[i].chan)
535*4882a593Smuzhiyun return;
536*4882a593Smuzhiyun err = mbox_send_message(ddata->mb[i].chan, (void *)(long)vqid);
537*4882a593Smuzhiyun if (err < 0)
538*4882a593Smuzhiyun dev_err(&rproc->dev, "%s: failed (%s, err:%d)\n",
539*4882a593Smuzhiyun __func__, ddata->mb[i].name, err);
540*4882a593Smuzhiyun return;
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun }
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun static struct rproc_ops st_rproc_ops = {
545*4882a593Smuzhiyun .start = stm32_rproc_start,
546*4882a593Smuzhiyun .stop = stm32_rproc_stop,
547*4882a593Smuzhiyun .attach = stm32_rproc_attach,
548*4882a593Smuzhiyun .kick = stm32_rproc_kick,
549*4882a593Smuzhiyun .load = rproc_elf_load_segments,
550*4882a593Smuzhiyun .parse_fw = stm32_rproc_parse_fw,
551*4882a593Smuzhiyun .find_loaded_rsc_table = rproc_elf_find_loaded_rsc_table,
552*4882a593Smuzhiyun .sanity_check = rproc_elf_sanity_check,
553*4882a593Smuzhiyun .get_boot_addr = rproc_elf_get_boot_addr,
554*4882a593Smuzhiyun };
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun static const struct of_device_id stm32_rproc_match[] = {
557*4882a593Smuzhiyun { .compatible = "st,stm32mp1-m4" },
558*4882a593Smuzhiyun {},
559*4882a593Smuzhiyun };
560*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, stm32_rproc_match);
561*4882a593Smuzhiyun
stm32_rproc_get_syscon(struct device_node * np,const char * prop,struct stm32_syscon * syscon)562*4882a593Smuzhiyun static int stm32_rproc_get_syscon(struct device_node *np, const char *prop,
563*4882a593Smuzhiyun struct stm32_syscon *syscon)
564*4882a593Smuzhiyun {
565*4882a593Smuzhiyun int err = 0;
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun syscon->map = syscon_regmap_lookup_by_phandle(np, prop);
568*4882a593Smuzhiyun if (IS_ERR(syscon->map)) {
569*4882a593Smuzhiyun err = PTR_ERR(syscon->map);
570*4882a593Smuzhiyun syscon->map = NULL;
571*4882a593Smuzhiyun goto out;
572*4882a593Smuzhiyun }
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun err = of_property_read_u32_index(np, prop, 1, &syscon->reg);
575*4882a593Smuzhiyun if (err)
576*4882a593Smuzhiyun goto out;
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun err = of_property_read_u32_index(np, prop, 2, &syscon->mask);
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun out:
581*4882a593Smuzhiyun return err;
582*4882a593Smuzhiyun }
583*4882a593Smuzhiyun
stm32_rproc_parse_dt(struct platform_device * pdev,struct stm32_rproc * ddata,bool * auto_boot)584*4882a593Smuzhiyun static int stm32_rproc_parse_dt(struct platform_device *pdev,
585*4882a593Smuzhiyun struct stm32_rproc *ddata, bool *auto_boot)
586*4882a593Smuzhiyun {
587*4882a593Smuzhiyun struct device *dev = &pdev->dev;
588*4882a593Smuzhiyun struct device_node *np = dev->of_node;
589*4882a593Smuzhiyun struct stm32_syscon tz;
590*4882a593Smuzhiyun unsigned int tzen;
591*4882a593Smuzhiyun int err, irq;
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun irq = platform_get_irq(pdev, 0);
594*4882a593Smuzhiyun if (irq == -EPROBE_DEFER)
595*4882a593Smuzhiyun return -EPROBE_DEFER;
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun if (irq > 0) {
598*4882a593Smuzhiyun err = devm_request_irq(dev, irq, stm32_rproc_wdg, 0,
599*4882a593Smuzhiyun dev_name(dev), pdev);
600*4882a593Smuzhiyun if (err) {
601*4882a593Smuzhiyun dev_err(dev, "failed to request wdg irq\n");
602*4882a593Smuzhiyun return err;
603*4882a593Smuzhiyun }
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun ddata->wdg_irq = irq;
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun if (of_property_read_bool(np, "wakeup-source")) {
608*4882a593Smuzhiyun device_init_wakeup(dev, true);
609*4882a593Smuzhiyun dev_pm_set_wake_irq(dev, irq);
610*4882a593Smuzhiyun }
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun dev_info(dev, "wdg irq registered\n");
613*4882a593Smuzhiyun }
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun ddata->rst = devm_reset_control_get_by_index(dev, 0);
616*4882a593Smuzhiyun if (IS_ERR(ddata->rst)) {
617*4882a593Smuzhiyun dev_err(dev, "failed to get mcu reset\n");
618*4882a593Smuzhiyun return PTR_ERR(ddata->rst);
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun /*
622*4882a593Smuzhiyun * if platform is secured the hold boot bit must be written by
623*4882a593Smuzhiyun * smc call and read normally.
624*4882a593Smuzhiyun * if not secure the hold boot bit could be read/write normally
625*4882a593Smuzhiyun */
626*4882a593Smuzhiyun err = stm32_rproc_get_syscon(np, "st,syscfg-tz", &tz);
627*4882a593Smuzhiyun if (err) {
628*4882a593Smuzhiyun dev_err(dev, "failed to get tz syscfg\n");
629*4882a593Smuzhiyun return err;
630*4882a593Smuzhiyun }
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun err = regmap_read(tz.map, tz.reg, &tzen);
633*4882a593Smuzhiyun if (err) {
634*4882a593Smuzhiyun dev_err(dev, "failed to read tzen\n");
635*4882a593Smuzhiyun return err;
636*4882a593Smuzhiyun }
637*4882a593Smuzhiyun ddata->secured_soc = tzen & tz.mask;
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun err = stm32_rproc_get_syscon(np, "st,syscfg-holdboot",
640*4882a593Smuzhiyun &ddata->hold_boot);
641*4882a593Smuzhiyun if (err) {
642*4882a593Smuzhiyun dev_err(dev, "failed to get hold boot\n");
643*4882a593Smuzhiyun return err;
644*4882a593Smuzhiyun }
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun err = stm32_rproc_get_syscon(np, "st,syscfg-pdds", &ddata->pdds);
647*4882a593Smuzhiyun if (err)
648*4882a593Smuzhiyun dev_info(dev, "failed to get pdds\n");
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun *auto_boot = of_property_read_bool(np, "st,auto-boot");
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun /*
653*4882a593Smuzhiyun * See if we can check the M4 status, i.e if it was started
654*4882a593Smuzhiyun * from the boot loader or not.
655*4882a593Smuzhiyun */
656*4882a593Smuzhiyun err = stm32_rproc_get_syscon(np, "st,syscfg-m4-state",
657*4882a593Smuzhiyun &ddata->m4_state);
658*4882a593Smuzhiyun if (err) {
659*4882a593Smuzhiyun /* remember this */
660*4882a593Smuzhiyun ddata->m4_state.map = NULL;
661*4882a593Smuzhiyun /* no coprocessor state syscon (optional) */
662*4882a593Smuzhiyun dev_warn(dev, "m4 state not supported\n");
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun /* no need to go further */
665*4882a593Smuzhiyun return 0;
666*4882a593Smuzhiyun }
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun /* See if we can get the resource table */
669*4882a593Smuzhiyun err = stm32_rproc_get_syscon(np, "st,syscfg-rsc-tbl",
670*4882a593Smuzhiyun &ddata->rsctbl);
671*4882a593Smuzhiyun if (err) {
672*4882a593Smuzhiyun /* no rsc table syscon (optional) */
673*4882a593Smuzhiyun dev_warn(dev, "rsc tbl syscon not supported\n");
674*4882a593Smuzhiyun }
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun return 0;
677*4882a593Smuzhiyun }
678*4882a593Smuzhiyun
stm32_rproc_get_m4_status(struct stm32_rproc * ddata,unsigned int * state)679*4882a593Smuzhiyun static int stm32_rproc_get_m4_status(struct stm32_rproc *ddata,
680*4882a593Smuzhiyun unsigned int *state)
681*4882a593Smuzhiyun {
682*4882a593Smuzhiyun /* See stm32_rproc_parse_dt() */
683*4882a593Smuzhiyun if (!ddata->m4_state.map) {
684*4882a593Smuzhiyun /*
685*4882a593Smuzhiyun * We couldn't get the coprocessor's state, assume
686*4882a593Smuzhiyun * it is not running.
687*4882a593Smuzhiyun */
688*4882a593Smuzhiyun *state = M4_STATE_OFF;
689*4882a593Smuzhiyun return 0;
690*4882a593Smuzhiyun }
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun return regmap_read(ddata->m4_state.map, ddata->m4_state.reg, state);
693*4882a593Smuzhiyun }
694*4882a593Smuzhiyun
stm32_rproc_da_to_pa(struct platform_device * pdev,struct stm32_rproc * ddata,u64 da,phys_addr_t * pa)695*4882a593Smuzhiyun static int stm32_rproc_da_to_pa(struct platform_device *pdev,
696*4882a593Smuzhiyun struct stm32_rproc *ddata,
697*4882a593Smuzhiyun u64 da, phys_addr_t *pa)
698*4882a593Smuzhiyun {
699*4882a593Smuzhiyun struct device *dev = &pdev->dev;
700*4882a593Smuzhiyun struct stm32_rproc_mem *p_mem;
701*4882a593Smuzhiyun unsigned int i;
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun for (i = 0; i < ddata->nb_rmems; i++) {
704*4882a593Smuzhiyun p_mem = &ddata->rmems[i];
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun if (da < p_mem->dev_addr ||
707*4882a593Smuzhiyun da >= p_mem->dev_addr + p_mem->size)
708*4882a593Smuzhiyun continue;
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun *pa = da - p_mem->dev_addr + p_mem->bus_addr;
711*4882a593Smuzhiyun dev_dbg(dev, "da %llx to pa %#x\n", da, *pa);
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun return 0;
714*4882a593Smuzhiyun }
715*4882a593Smuzhiyun
716*4882a593Smuzhiyun dev_err(dev, "can't translate da %llx\n", da);
717*4882a593Smuzhiyun
718*4882a593Smuzhiyun return -EINVAL;
719*4882a593Smuzhiyun }
720*4882a593Smuzhiyun
stm32_rproc_get_loaded_rsc_table(struct platform_device * pdev,struct rproc * rproc,struct stm32_rproc * ddata)721*4882a593Smuzhiyun static int stm32_rproc_get_loaded_rsc_table(struct platform_device *pdev,
722*4882a593Smuzhiyun struct rproc *rproc,
723*4882a593Smuzhiyun struct stm32_rproc *ddata)
724*4882a593Smuzhiyun {
725*4882a593Smuzhiyun struct device *dev = &pdev->dev;
726*4882a593Smuzhiyun phys_addr_t rsc_pa;
727*4882a593Smuzhiyun u32 rsc_da;
728*4882a593Smuzhiyun int err;
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun err = regmap_read(ddata->rsctbl.map, ddata->rsctbl.reg, &rsc_da);
731*4882a593Smuzhiyun if (err) {
732*4882a593Smuzhiyun dev_err(dev, "failed to read rsc tbl addr\n");
733*4882a593Smuzhiyun return err;
734*4882a593Smuzhiyun }
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun if (!rsc_da)
737*4882a593Smuzhiyun /* no rsc table */
738*4882a593Smuzhiyun return 0;
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun err = stm32_rproc_da_to_pa(pdev, ddata, rsc_da, &rsc_pa);
741*4882a593Smuzhiyun if (err)
742*4882a593Smuzhiyun return err;
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun ddata->rsc_va = devm_ioremap_wc(dev, rsc_pa, RSC_TBL_SIZE);
745*4882a593Smuzhiyun if (IS_ERR_OR_NULL(ddata->rsc_va)) {
746*4882a593Smuzhiyun dev_err(dev, "Unable to map memory region: %pa+%zx\n",
747*4882a593Smuzhiyun &rsc_pa, RSC_TBL_SIZE);
748*4882a593Smuzhiyun ddata->rsc_va = NULL;
749*4882a593Smuzhiyun return -ENOMEM;
750*4882a593Smuzhiyun }
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun /*
753*4882a593Smuzhiyun * The resource table is already loaded in device memory, no need
754*4882a593Smuzhiyun * to work with a cached table.
755*4882a593Smuzhiyun */
756*4882a593Smuzhiyun rproc->cached_table = NULL;
757*4882a593Smuzhiyun /* Assuming the resource table fits in 1kB is fair */
758*4882a593Smuzhiyun rproc->table_sz = RSC_TBL_SIZE;
759*4882a593Smuzhiyun rproc->table_ptr = (struct resource_table *)ddata->rsc_va;
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun return 0;
762*4882a593Smuzhiyun }
763*4882a593Smuzhiyun
stm32_rproc_probe(struct platform_device * pdev)764*4882a593Smuzhiyun static int stm32_rproc_probe(struct platform_device *pdev)
765*4882a593Smuzhiyun {
766*4882a593Smuzhiyun struct device *dev = &pdev->dev;
767*4882a593Smuzhiyun struct stm32_rproc *ddata;
768*4882a593Smuzhiyun struct device_node *np = dev->of_node;
769*4882a593Smuzhiyun struct rproc *rproc;
770*4882a593Smuzhiyun unsigned int state;
771*4882a593Smuzhiyun int ret;
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
774*4882a593Smuzhiyun if (ret)
775*4882a593Smuzhiyun return ret;
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun rproc = rproc_alloc(dev, np->name, &st_rproc_ops, NULL, sizeof(*ddata));
778*4882a593Smuzhiyun if (!rproc)
779*4882a593Smuzhiyun return -ENOMEM;
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun ddata = rproc->priv;
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
784*4882a593Smuzhiyun
785*4882a593Smuzhiyun ret = stm32_rproc_parse_dt(pdev, ddata, &rproc->auto_boot);
786*4882a593Smuzhiyun if (ret)
787*4882a593Smuzhiyun goto free_rproc;
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun ret = stm32_rproc_of_memory_translations(pdev, ddata);
790*4882a593Smuzhiyun if (ret)
791*4882a593Smuzhiyun goto free_rproc;
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun ret = stm32_rproc_get_m4_status(ddata, &state);
794*4882a593Smuzhiyun if (ret)
795*4882a593Smuzhiyun goto free_rproc;
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun if (state == M4_STATE_CRUN) {
798*4882a593Smuzhiyun rproc->state = RPROC_DETACHED;
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun ret = stm32_rproc_parse_memory_regions(rproc);
801*4882a593Smuzhiyun if (ret)
802*4882a593Smuzhiyun goto free_resources;
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun ret = stm32_rproc_get_loaded_rsc_table(pdev, rproc, ddata);
805*4882a593Smuzhiyun if (ret)
806*4882a593Smuzhiyun goto free_resources;
807*4882a593Smuzhiyun }
808*4882a593Smuzhiyun
809*4882a593Smuzhiyun rproc->has_iommu = false;
810*4882a593Smuzhiyun ddata->workqueue = create_workqueue(dev_name(dev));
811*4882a593Smuzhiyun if (!ddata->workqueue) {
812*4882a593Smuzhiyun dev_err(dev, "cannot create workqueue\n");
813*4882a593Smuzhiyun ret = -ENOMEM;
814*4882a593Smuzhiyun goto free_resources;
815*4882a593Smuzhiyun }
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun platform_set_drvdata(pdev, rproc);
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun ret = stm32_rproc_request_mbox(rproc);
820*4882a593Smuzhiyun if (ret)
821*4882a593Smuzhiyun goto free_wkq;
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun ret = rproc_add(rproc);
824*4882a593Smuzhiyun if (ret)
825*4882a593Smuzhiyun goto free_mb;
826*4882a593Smuzhiyun
827*4882a593Smuzhiyun return 0;
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun free_mb:
830*4882a593Smuzhiyun stm32_rproc_free_mbox(rproc);
831*4882a593Smuzhiyun free_wkq:
832*4882a593Smuzhiyun destroy_workqueue(ddata->workqueue);
833*4882a593Smuzhiyun free_resources:
834*4882a593Smuzhiyun rproc_resource_cleanup(rproc);
835*4882a593Smuzhiyun free_rproc:
836*4882a593Smuzhiyun if (device_may_wakeup(dev)) {
837*4882a593Smuzhiyun dev_pm_clear_wake_irq(dev);
838*4882a593Smuzhiyun device_init_wakeup(dev, false);
839*4882a593Smuzhiyun }
840*4882a593Smuzhiyun rproc_free(rproc);
841*4882a593Smuzhiyun return ret;
842*4882a593Smuzhiyun }
843*4882a593Smuzhiyun
stm32_rproc_remove(struct platform_device * pdev)844*4882a593Smuzhiyun static int stm32_rproc_remove(struct platform_device *pdev)
845*4882a593Smuzhiyun {
846*4882a593Smuzhiyun struct rproc *rproc = platform_get_drvdata(pdev);
847*4882a593Smuzhiyun struct stm32_rproc *ddata = rproc->priv;
848*4882a593Smuzhiyun struct device *dev = &pdev->dev;
849*4882a593Smuzhiyun
850*4882a593Smuzhiyun if (atomic_read(&rproc->power) > 0)
851*4882a593Smuzhiyun rproc_shutdown(rproc);
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun rproc_del(rproc);
854*4882a593Smuzhiyun stm32_rproc_free_mbox(rproc);
855*4882a593Smuzhiyun destroy_workqueue(ddata->workqueue);
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun if (device_may_wakeup(dev)) {
858*4882a593Smuzhiyun dev_pm_clear_wake_irq(dev);
859*4882a593Smuzhiyun device_init_wakeup(dev, false);
860*4882a593Smuzhiyun }
861*4882a593Smuzhiyun rproc_free(rproc);
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun return 0;
864*4882a593Smuzhiyun }
865*4882a593Smuzhiyun
stm32_rproc_suspend(struct device * dev)866*4882a593Smuzhiyun static int __maybe_unused stm32_rproc_suspend(struct device *dev)
867*4882a593Smuzhiyun {
868*4882a593Smuzhiyun struct rproc *rproc = dev_get_drvdata(dev);
869*4882a593Smuzhiyun struct stm32_rproc *ddata = rproc->priv;
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun if (device_may_wakeup(dev))
872*4882a593Smuzhiyun return enable_irq_wake(ddata->wdg_irq);
873*4882a593Smuzhiyun
874*4882a593Smuzhiyun return 0;
875*4882a593Smuzhiyun }
876*4882a593Smuzhiyun
stm32_rproc_resume(struct device * dev)877*4882a593Smuzhiyun static int __maybe_unused stm32_rproc_resume(struct device *dev)
878*4882a593Smuzhiyun {
879*4882a593Smuzhiyun struct rproc *rproc = dev_get_drvdata(dev);
880*4882a593Smuzhiyun struct stm32_rproc *ddata = rproc->priv;
881*4882a593Smuzhiyun
882*4882a593Smuzhiyun if (device_may_wakeup(dev))
883*4882a593Smuzhiyun return disable_irq_wake(ddata->wdg_irq);
884*4882a593Smuzhiyun
885*4882a593Smuzhiyun return 0;
886*4882a593Smuzhiyun }
887*4882a593Smuzhiyun
888*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(stm32_rproc_pm_ops,
889*4882a593Smuzhiyun stm32_rproc_suspend, stm32_rproc_resume);
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun static struct platform_driver stm32_rproc_driver = {
892*4882a593Smuzhiyun .probe = stm32_rproc_probe,
893*4882a593Smuzhiyun .remove = stm32_rproc_remove,
894*4882a593Smuzhiyun .driver = {
895*4882a593Smuzhiyun .name = "stm32-rproc",
896*4882a593Smuzhiyun .pm = &stm32_rproc_pm_ops,
897*4882a593Smuzhiyun .of_match_table = of_match_ptr(stm32_rproc_match),
898*4882a593Smuzhiyun },
899*4882a593Smuzhiyun };
900*4882a593Smuzhiyun module_platform_driver(stm32_rproc_driver);
901*4882a593Smuzhiyun
902*4882a593Smuzhiyun MODULE_DESCRIPTION("STM32 Remote Processor Control Driver");
903*4882a593Smuzhiyun MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
904*4882a593Smuzhiyun MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
905*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
906*4882a593Smuzhiyun
907