1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Qualcomm Wireless Connectivity Subsystem Iris driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016 Linaro Ltd
6*4882a593Smuzhiyun * Copyright (C) 2014 Sony Mobile Communications AB
7*4882a593Smuzhiyun * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/of_device.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "qcom_wcnss.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun struct qcom_iris {
20*4882a593Smuzhiyun struct device *dev;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun struct clk *xo_clk;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun struct regulator_bulk_data *vregs;
25*4882a593Smuzhiyun size_t num_vregs;
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun struct iris_data {
29*4882a593Smuzhiyun const struct wcnss_vreg_info *vregs;
30*4882a593Smuzhiyun size_t num_vregs;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun bool use_48mhz_xo;
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static const struct iris_data wcn3620_data = {
36*4882a593Smuzhiyun .vregs = (struct wcnss_vreg_info[]) {
37*4882a593Smuzhiyun { "vddxo", 1800000, 1800000, 10000 },
38*4882a593Smuzhiyun { "vddrfa", 1300000, 1300000, 100000 },
39*4882a593Smuzhiyun { "vddpa", 3300000, 3300000, 515000 },
40*4882a593Smuzhiyun { "vdddig", 1800000, 1800000, 10000 },
41*4882a593Smuzhiyun },
42*4882a593Smuzhiyun .num_vregs = 4,
43*4882a593Smuzhiyun .use_48mhz_xo = false,
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun static const struct iris_data wcn3660_data = {
47*4882a593Smuzhiyun .vregs = (struct wcnss_vreg_info[]) {
48*4882a593Smuzhiyun { "vddxo", 1800000, 1800000, 10000 },
49*4882a593Smuzhiyun { "vddrfa", 1300000, 1300000, 100000 },
50*4882a593Smuzhiyun { "vddpa", 2900000, 3000000, 515000 },
51*4882a593Smuzhiyun { "vdddig", 1200000, 1225000, 10000 },
52*4882a593Smuzhiyun },
53*4882a593Smuzhiyun .num_vregs = 4,
54*4882a593Smuzhiyun .use_48mhz_xo = true,
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun static const struct iris_data wcn3680_data = {
58*4882a593Smuzhiyun .vregs = (struct wcnss_vreg_info[]) {
59*4882a593Smuzhiyun { "vddxo", 1800000, 1800000, 10000 },
60*4882a593Smuzhiyun { "vddrfa", 1300000, 1300000, 100000 },
61*4882a593Smuzhiyun { "vddpa", 3300000, 3300000, 515000 },
62*4882a593Smuzhiyun { "vdddig", 1800000, 1800000, 10000 },
63*4882a593Smuzhiyun },
64*4882a593Smuzhiyun .num_vregs = 4,
65*4882a593Smuzhiyun .use_48mhz_xo = true,
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
qcom_iris_enable(struct qcom_iris * iris)68*4882a593Smuzhiyun int qcom_iris_enable(struct qcom_iris *iris)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun int ret;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun ret = regulator_bulk_enable(iris->num_vregs, iris->vregs);
73*4882a593Smuzhiyun if (ret)
74*4882a593Smuzhiyun return ret;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun ret = clk_prepare_enable(iris->xo_clk);
77*4882a593Smuzhiyun if (ret) {
78*4882a593Smuzhiyun dev_err(iris->dev, "failed to enable xo clk\n");
79*4882a593Smuzhiyun goto disable_regulators;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun return 0;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun disable_regulators:
85*4882a593Smuzhiyun regulator_bulk_disable(iris->num_vregs, iris->vregs);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun return ret;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
qcom_iris_disable(struct qcom_iris * iris)90*4882a593Smuzhiyun void qcom_iris_disable(struct qcom_iris *iris)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun clk_disable_unprepare(iris->xo_clk);
93*4882a593Smuzhiyun regulator_bulk_disable(iris->num_vregs, iris->vregs);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
qcom_iris_probe(struct platform_device * pdev)96*4882a593Smuzhiyun static int qcom_iris_probe(struct platform_device *pdev)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun const struct iris_data *data;
99*4882a593Smuzhiyun struct qcom_wcnss *wcnss;
100*4882a593Smuzhiyun struct qcom_iris *iris;
101*4882a593Smuzhiyun int ret;
102*4882a593Smuzhiyun int i;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun iris = devm_kzalloc(&pdev->dev, sizeof(struct qcom_iris), GFP_KERNEL);
105*4882a593Smuzhiyun if (!iris)
106*4882a593Smuzhiyun return -ENOMEM;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun data = of_device_get_match_data(&pdev->dev);
109*4882a593Smuzhiyun wcnss = dev_get_drvdata(pdev->dev.parent);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun iris->xo_clk = devm_clk_get(&pdev->dev, "xo");
112*4882a593Smuzhiyun if (IS_ERR(iris->xo_clk)) {
113*4882a593Smuzhiyun if (PTR_ERR(iris->xo_clk) != -EPROBE_DEFER)
114*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to acquire xo clk\n");
115*4882a593Smuzhiyun return PTR_ERR(iris->xo_clk);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun iris->num_vregs = data->num_vregs;
119*4882a593Smuzhiyun iris->vregs = devm_kcalloc(&pdev->dev,
120*4882a593Smuzhiyun iris->num_vregs,
121*4882a593Smuzhiyun sizeof(struct regulator_bulk_data),
122*4882a593Smuzhiyun GFP_KERNEL);
123*4882a593Smuzhiyun if (!iris->vregs)
124*4882a593Smuzhiyun return -ENOMEM;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun for (i = 0; i < iris->num_vregs; i++)
127*4882a593Smuzhiyun iris->vregs[i].supply = data->vregs[i].name;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun ret = devm_regulator_bulk_get(&pdev->dev, iris->num_vregs, iris->vregs);
130*4882a593Smuzhiyun if (ret) {
131*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to get regulators\n");
132*4882a593Smuzhiyun return ret;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun for (i = 0; i < iris->num_vregs; i++) {
136*4882a593Smuzhiyun if (data->vregs[i].max_voltage)
137*4882a593Smuzhiyun regulator_set_voltage(iris->vregs[i].consumer,
138*4882a593Smuzhiyun data->vregs[i].min_voltage,
139*4882a593Smuzhiyun data->vregs[i].max_voltage);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun if (data->vregs[i].load_uA)
142*4882a593Smuzhiyun regulator_set_load(iris->vregs[i].consumer,
143*4882a593Smuzhiyun data->vregs[i].load_uA);
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun qcom_wcnss_assign_iris(wcnss, iris, data->use_48mhz_xo);
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun return 0;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
qcom_iris_remove(struct platform_device * pdev)151*4882a593Smuzhiyun static int qcom_iris_remove(struct platform_device *pdev)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun struct qcom_wcnss *wcnss = dev_get_drvdata(pdev->dev.parent);
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun qcom_wcnss_assign_iris(wcnss, NULL, false);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun return 0;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun static const struct of_device_id iris_of_match[] = {
161*4882a593Smuzhiyun { .compatible = "qcom,wcn3620", .data = &wcn3620_data },
162*4882a593Smuzhiyun { .compatible = "qcom,wcn3660", .data = &wcn3660_data },
163*4882a593Smuzhiyun { .compatible = "qcom,wcn3680", .data = &wcn3680_data },
164*4882a593Smuzhiyun {}
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, iris_of_match);
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun struct platform_driver qcom_iris_driver = {
169*4882a593Smuzhiyun .probe = qcom_iris_probe,
170*4882a593Smuzhiyun .remove = qcom_iris_remove,
171*4882a593Smuzhiyun .driver = {
172*4882a593Smuzhiyun .name = "qcom-iris",
173*4882a593Smuzhiyun .of_match_table = iris_of_match,
174*4882a593Smuzhiyun },
175*4882a593Smuzhiyun };
176