1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __QCOM_WNCSS_H__ 3*4882a593Smuzhiyun #define __QCOM_WNCSS_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun struct qcom_iris; 6*4882a593Smuzhiyun struct qcom_wcnss; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun extern struct platform_driver qcom_iris_driver; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct wcnss_vreg_info { 11*4882a593Smuzhiyun const char * const name; 12*4882a593Smuzhiyun int min_voltage; 13*4882a593Smuzhiyun int max_voltage; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun int load_uA; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun bool super_turbo; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun int qcom_iris_enable(struct qcom_iris *iris); 21*4882a593Smuzhiyun void qcom_iris_disable(struct qcom_iris *iris); 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss, struct qcom_iris *iris, bool use_48mhz_xo); 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #endif 26