1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019 MediaTek Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __RPROC_MTK_COMMON_H 7*4882a593Smuzhiyun #define __RPROC_MTK_COMMON_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/interrupt.h> 10*4882a593Smuzhiyun #include <linux/kernel.h> 11*4882a593Smuzhiyun #include <linux/platform_device.h> 12*4882a593Smuzhiyun #include <linux/remoteproc.h> 13*4882a593Smuzhiyun #include <linux/remoteproc/mtk_scp.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define MT8183_SW_RSTN 0x0 16*4882a593Smuzhiyun #define MT8183_SW_RSTN_BIT BIT(0) 17*4882a593Smuzhiyun #define MT8183_SCP_TO_HOST 0x1C 18*4882a593Smuzhiyun #define MT8183_SCP_IPC_INT_BIT BIT(0) 19*4882a593Smuzhiyun #define MT8183_SCP_WDT_INT_BIT BIT(8) 20*4882a593Smuzhiyun #define MT8183_HOST_TO_SCP 0x28 21*4882a593Smuzhiyun #define MT8183_HOST_IPC_INT_BIT BIT(0) 22*4882a593Smuzhiyun #define MT8183_WDT_CFG 0x84 23*4882a593Smuzhiyun #define MT8183_SCP_CLK_SW_SEL 0x4000 24*4882a593Smuzhiyun #define MT8183_SCP_CLK_DIV_SEL 0x4024 25*4882a593Smuzhiyun #define MT8183_SCP_SRAM_PDN 0x402C 26*4882a593Smuzhiyun #define MT8183_SCP_L1_SRAM_PD 0x4080 27*4882a593Smuzhiyun #define MT8183_SCP_TCM_TAIL_SRAM_PD 0x4094 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define MT8183_SCP_CACHE_SEL(x) (0x14000 + (x) * 0x3000) 30*4882a593Smuzhiyun #define MT8183_SCP_CACHE_CON MT8183_SCP_CACHE_SEL(0) 31*4882a593Smuzhiyun #define MT8183_SCP_DCACHE_CON MT8183_SCP_CACHE_SEL(1) 32*4882a593Smuzhiyun #define MT8183_SCP_CACHESIZE_8KB BIT(8) 33*4882a593Smuzhiyun #define MT8183_SCP_CACHE_CON_WAYEN BIT(10) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define MT8192_L2TCM_SRAM_PD_0 0x10C0 36*4882a593Smuzhiyun #define MT8192_L2TCM_SRAM_PD_1 0x10C4 37*4882a593Smuzhiyun #define MT8192_L2TCM_SRAM_PD_2 0x10C8 38*4882a593Smuzhiyun #define MT8192_L1TCM_SRAM_PDN 0x102C 39*4882a593Smuzhiyun #define MT8192_CPU0_SRAM_PD 0x1080 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define MT8192_SCP2APMCU_IPC_SET 0x4080 42*4882a593Smuzhiyun #define MT8192_SCP2APMCU_IPC_CLR 0x4084 43*4882a593Smuzhiyun #define MT8192_SCP_IPC_INT_BIT BIT(0) 44*4882a593Smuzhiyun #define MT8192_SCP2SPM_IPC_CLR 0x4094 45*4882a593Smuzhiyun #define MT8192_GIPC_IN_SET 0x4098 46*4882a593Smuzhiyun #define MT8192_HOST_IPC_INT_BIT BIT(0) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define MT8192_CORE0_SW_RSTN_CLR 0x10000 49*4882a593Smuzhiyun #define MT8192_CORE0_SW_RSTN_SET 0x10004 50*4882a593Smuzhiyun #define MT8192_CORE0_WDT_IRQ 0x10030 51*4882a593Smuzhiyun #define MT8192_CORE0_WDT_CFG 0x10034 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define SCP_FW_VER_LEN 32 54*4882a593Smuzhiyun #define SCP_SHARE_BUFFER_SIZE 288 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun struct scp_run { 57*4882a593Smuzhiyun u32 signaled; 58*4882a593Smuzhiyun s8 fw_ver[SCP_FW_VER_LEN]; 59*4882a593Smuzhiyun u32 dec_capability; 60*4882a593Smuzhiyun u32 enc_capability; 61*4882a593Smuzhiyun wait_queue_head_t wq; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun struct scp_ipi_desc { 65*4882a593Smuzhiyun /* For protecting handler. */ 66*4882a593Smuzhiyun struct mutex lock; 67*4882a593Smuzhiyun scp_ipi_handler_t handler; 68*4882a593Smuzhiyun void *priv; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun struct mtk_scp; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun struct mtk_scp_of_data { 74*4882a593Smuzhiyun int (*scp_before_load)(struct mtk_scp *scp); 75*4882a593Smuzhiyun void (*scp_irq_handler)(struct mtk_scp *scp); 76*4882a593Smuzhiyun void (*scp_reset_assert)(struct mtk_scp *scp); 77*4882a593Smuzhiyun void (*scp_reset_deassert)(struct mtk_scp *scp); 78*4882a593Smuzhiyun void (*scp_stop)(struct mtk_scp *scp); 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun u32 host_to_scp_reg; 81*4882a593Smuzhiyun u32 host_to_scp_int_bit; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun struct mtk_scp { 85*4882a593Smuzhiyun struct device *dev; 86*4882a593Smuzhiyun struct rproc *rproc; 87*4882a593Smuzhiyun struct clk *clk; 88*4882a593Smuzhiyun void __iomem *reg_base; 89*4882a593Smuzhiyun void __iomem *sram_base; 90*4882a593Smuzhiyun size_t sram_size; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun const struct mtk_scp_of_data *data; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun struct mtk_share_obj __iomem *recv_buf; 95*4882a593Smuzhiyun struct mtk_share_obj __iomem *send_buf; 96*4882a593Smuzhiyun struct scp_run run; 97*4882a593Smuzhiyun /* To prevent multiple ipi_send run concurrently. */ 98*4882a593Smuzhiyun struct mutex send_lock; 99*4882a593Smuzhiyun struct scp_ipi_desc ipi_desc[SCP_IPI_MAX]; 100*4882a593Smuzhiyun bool ipi_id_ack[SCP_IPI_MAX]; 101*4882a593Smuzhiyun wait_queue_head_t ack_wq; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun void __iomem *cpu_addr; 104*4882a593Smuzhiyun dma_addr_t dma_addr; 105*4882a593Smuzhiyun size_t dram_size; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun struct rproc_subdev *rpmsg_subdev; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /** 111*4882a593Smuzhiyun * struct mtk_share_obj - SRAM buffer shared with AP and SCP 112*4882a593Smuzhiyun * 113*4882a593Smuzhiyun * @id: IPI id 114*4882a593Smuzhiyun * @len: share buffer length 115*4882a593Smuzhiyun * @share_buf: share buffer data 116*4882a593Smuzhiyun */ 117*4882a593Smuzhiyun struct mtk_share_obj { 118*4882a593Smuzhiyun u32 id; 119*4882a593Smuzhiyun u32 len; 120*4882a593Smuzhiyun u8 share_buf[SCP_SHARE_BUFFER_SIZE]; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun void scp_memcpy_aligned(void __iomem *dst, const void *src, unsigned int len); 124*4882a593Smuzhiyun void scp_ipi_lock(struct mtk_scp *scp, u32 id); 125*4882a593Smuzhiyun void scp_ipi_unlock(struct mtk_scp *scp, u32 id); 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #endif 128