xref: /OK3568_Linux_fs/kernel/drivers/remoteproc/da8xx_remoteproc.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Remote processor machine-specific module for DA8XX
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2013 Texas Instruments, Inc.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/bitops.h>
9*4882a593Smuzhiyun #include <linux/clk.h>
10*4882a593Smuzhiyun #include <linux/reset.h>
11*4882a593Smuzhiyun #include <linux/err.h>
12*4882a593Smuzhiyun #include <linux/interrupt.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/irq.h>
15*4882a593Smuzhiyun #include <linux/kernel.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/of_reserved_mem.h>
18*4882a593Smuzhiyun #include <linux/platform_device.h>
19*4882a593Smuzhiyun #include <linux/remoteproc.h>
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #include "remoteproc_internal.h"
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun static char *da8xx_fw_name;
24*4882a593Smuzhiyun module_param(da8xx_fw_name, charp, 0444);
25*4882a593Smuzhiyun MODULE_PARM_DESC(da8xx_fw_name,
26*4882a593Smuzhiyun 		 "Name of DSP firmware file in /lib/firmware (if not specified defaults to 'rproc-dsp-fw')");
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun  * OMAP-L138 Technical References:
30*4882a593Smuzhiyun  * http://www.ti.com/product/omap-l138
31*4882a593Smuzhiyun  */
32*4882a593Smuzhiyun #define SYSCFG_CHIPSIG0 BIT(0)
33*4882a593Smuzhiyun #define SYSCFG_CHIPSIG1 BIT(1)
34*4882a593Smuzhiyun #define SYSCFG_CHIPSIG2 BIT(2)
35*4882a593Smuzhiyun #define SYSCFG_CHIPSIG3 BIT(3)
36*4882a593Smuzhiyun #define SYSCFG_CHIPSIG4 BIT(4)
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #define DA8XX_RPROC_LOCAL_ADDRESS_MASK	(SZ_16M - 1)
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun /**
41*4882a593Smuzhiyun  * struct da8xx_rproc_mem - internal memory structure
42*4882a593Smuzhiyun  * @cpu_addr: MPU virtual address of the memory region
43*4882a593Smuzhiyun  * @bus_addr: Bus address used to access the memory region
44*4882a593Smuzhiyun  * @dev_addr: Device address of the memory region from DSP view
45*4882a593Smuzhiyun  * @size: Size of the memory region
46*4882a593Smuzhiyun  */
47*4882a593Smuzhiyun struct da8xx_rproc_mem {
48*4882a593Smuzhiyun 	void __iomem *cpu_addr;
49*4882a593Smuzhiyun 	phys_addr_t bus_addr;
50*4882a593Smuzhiyun 	u32 dev_addr;
51*4882a593Smuzhiyun 	size_t size;
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun /**
55*4882a593Smuzhiyun  * struct da8xx_rproc - da8xx remote processor instance state
56*4882a593Smuzhiyun  * @rproc: rproc handle
57*4882a593Smuzhiyun  * @mem: internal memory regions data
58*4882a593Smuzhiyun  * @num_mems: number of internal memory regions
59*4882a593Smuzhiyun  * @dsp_clk: placeholder for platform's DSP clk
60*4882a593Smuzhiyun  * @ack_fxn: chip-specific ack function for ack'ing irq
61*4882a593Smuzhiyun  * @irq_data: ack_fxn function parameter
62*4882a593Smuzhiyun  * @chipsig: virt ptr to DSP interrupt registers (CHIPSIG & CHIPSIG_CLR)
63*4882a593Smuzhiyun  * @bootreg: virt ptr to DSP boot address register (HOST1CFG)
64*4882a593Smuzhiyun  * @irq: irq # used by this instance
65*4882a593Smuzhiyun  */
66*4882a593Smuzhiyun struct da8xx_rproc {
67*4882a593Smuzhiyun 	struct rproc *rproc;
68*4882a593Smuzhiyun 	struct da8xx_rproc_mem *mem;
69*4882a593Smuzhiyun 	int num_mems;
70*4882a593Smuzhiyun 	struct clk *dsp_clk;
71*4882a593Smuzhiyun 	struct reset_control *dsp_reset;
72*4882a593Smuzhiyun 	void (*ack_fxn)(struct irq_data *data);
73*4882a593Smuzhiyun 	struct irq_data *irq_data;
74*4882a593Smuzhiyun 	void __iomem *chipsig;
75*4882a593Smuzhiyun 	void __iomem *bootreg;
76*4882a593Smuzhiyun 	int irq;
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun /**
80*4882a593Smuzhiyun  * handle_event() - inbound virtqueue message workqueue function
81*4882a593Smuzhiyun  *
82*4882a593Smuzhiyun  * This function is registered as a kernel thread and is scheduled by the
83*4882a593Smuzhiyun  * kernel handler.
84*4882a593Smuzhiyun  */
handle_event(int irq,void * p)85*4882a593Smuzhiyun static irqreturn_t handle_event(int irq, void *p)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun 	struct rproc *rproc = (struct rproc *)p;
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	/* Process incoming buffers on all our vrings */
90*4882a593Smuzhiyun 	rproc_vq_interrupt(rproc, 0);
91*4882a593Smuzhiyun 	rproc_vq_interrupt(rproc, 1);
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	return IRQ_HANDLED;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun /**
97*4882a593Smuzhiyun  * da8xx_rproc_callback() - inbound virtqueue message handler
98*4882a593Smuzhiyun  *
99*4882a593Smuzhiyun  * This handler is invoked directly by the kernel whenever the remote
100*4882a593Smuzhiyun  * core (DSP) has modified the state of a virtqueue.  There is no
101*4882a593Smuzhiyun  * "payload" message indicating the virtqueue index as is the case with
102*4882a593Smuzhiyun  * mailbox-based implementations on OMAP4.  As such, this handler "polls"
103*4882a593Smuzhiyun  * each known virtqueue index for every invocation.
104*4882a593Smuzhiyun  */
da8xx_rproc_callback(int irq,void * p)105*4882a593Smuzhiyun static irqreturn_t da8xx_rproc_callback(int irq, void *p)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun 	struct rproc *rproc = (struct rproc *)p;
108*4882a593Smuzhiyun 	struct da8xx_rproc *drproc = (struct da8xx_rproc *)rproc->priv;
109*4882a593Smuzhiyun 	u32 chipsig;
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	chipsig = readl(drproc->chipsig);
112*4882a593Smuzhiyun 	if (chipsig & SYSCFG_CHIPSIG0) {
113*4882a593Smuzhiyun 		/* Clear interrupt level source */
114*4882a593Smuzhiyun 		writel(SYSCFG_CHIPSIG0, drproc->chipsig + 4);
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 		/*
117*4882a593Smuzhiyun 		 * ACK intr to AINTC.
118*4882a593Smuzhiyun 		 *
119*4882a593Smuzhiyun 		 * It has already been ack'ed by the kernel before calling
120*4882a593Smuzhiyun 		 * this function, but since the ARM<->DSP interrupts in the
121*4882a593Smuzhiyun 		 * CHIPSIG register are "level" instead of "pulse" variety,
122*4882a593Smuzhiyun 		 * we need to ack it after taking down the level else we'll
123*4882a593Smuzhiyun 		 * be called again immediately after returning.
124*4882a593Smuzhiyun 		 */
125*4882a593Smuzhiyun 		drproc->ack_fxn(drproc->irq_data);
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 		return IRQ_WAKE_THREAD;
128*4882a593Smuzhiyun 	}
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	return IRQ_HANDLED;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
da8xx_rproc_start(struct rproc * rproc)133*4882a593Smuzhiyun static int da8xx_rproc_start(struct rproc *rproc)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun 	struct device *dev = rproc->dev.parent;
136*4882a593Smuzhiyun 	struct da8xx_rproc *drproc = (struct da8xx_rproc *)rproc->priv;
137*4882a593Smuzhiyun 	struct clk *dsp_clk = drproc->dsp_clk;
138*4882a593Smuzhiyun 	struct reset_control *dsp_reset = drproc->dsp_reset;
139*4882a593Smuzhiyun 	int ret;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	/* hw requires the start (boot) address be on 1KB boundary */
142*4882a593Smuzhiyun 	if (rproc->bootaddr & 0x3ff) {
143*4882a593Smuzhiyun 		dev_err(dev, "invalid boot address: must be aligned to 1KB\n");
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 		return -EINVAL;
146*4882a593Smuzhiyun 	}
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	writel(rproc->bootaddr, drproc->bootreg);
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	ret = clk_prepare_enable(dsp_clk);
151*4882a593Smuzhiyun 	if (ret) {
152*4882a593Smuzhiyun 		dev_err(dev, "clk_prepare_enable() failed: %d\n", ret);
153*4882a593Smuzhiyun 		return ret;
154*4882a593Smuzhiyun 	}
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	ret = reset_control_deassert(dsp_reset);
157*4882a593Smuzhiyun 	if (ret) {
158*4882a593Smuzhiyun 		dev_err(dev, "reset_control_deassert() failed: %d\n", ret);
159*4882a593Smuzhiyun 		clk_disable_unprepare(dsp_clk);
160*4882a593Smuzhiyun 		return ret;
161*4882a593Smuzhiyun 	}
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	return 0;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun 
da8xx_rproc_stop(struct rproc * rproc)166*4882a593Smuzhiyun static int da8xx_rproc_stop(struct rproc *rproc)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun 	struct da8xx_rproc *drproc = rproc->priv;
169*4882a593Smuzhiyun 	struct device *dev = rproc->dev.parent;
170*4882a593Smuzhiyun 	int ret;
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	ret = reset_control_assert(drproc->dsp_reset);
173*4882a593Smuzhiyun 	if (ret) {
174*4882a593Smuzhiyun 		dev_err(dev, "reset_control_assert() failed: %d\n", ret);
175*4882a593Smuzhiyun 		return ret;
176*4882a593Smuzhiyun 	}
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	clk_disable_unprepare(drproc->dsp_clk);
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	return 0;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun /* kick a virtqueue */
da8xx_rproc_kick(struct rproc * rproc,int vqid)184*4882a593Smuzhiyun static void da8xx_rproc_kick(struct rproc *rproc, int vqid)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun 	struct da8xx_rproc *drproc = (struct da8xx_rproc *)rproc->priv;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	/* Interrupt remote proc */
189*4882a593Smuzhiyun 	writel(SYSCFG_CHIPSIG2, drproc->chipsig);
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun static const struct rproc_ops da8xx_rproc_ops = {
193*4882a593Smuzhiyun 	.start = da8xx_rproc_start,
194*4882a593Smuzhiyun 	.stop = da8xx_rproc_stop,
195*4882a593Smuzhiyun 	.kick = da8xx_rproc_kick,
196*4882a593Smuzhiyun };
197*4882a593Smuzhiyun 
da8xx_rproc_get_internal_memories(struct platform_device * pdev,struct da8xx_rproc * drproc)198*4882a593Smuzhiyun static int da8xx_rproc_get_internal_memories(struct platform_device *pdev,
199*4882a593Smuzhiyun 					     struct da8xx_rproc *drproc)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun 	static const char * const mem_names[] = {"l2sram", "l1pram", "l1dram"};
202*4882a593Smuzhiyun 	int num_mems = ARRAY_SIZE(mem_names);
203*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
204*4882a593Smuzhiyun 	struct resource *res;
205*4882a593Smuzhiyun 	int i;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	drproc->mem = devm_kcalloc(dev, num_mems, sizeof(*drproc->mem),
208*4882a593Smuzhiyun 				   GFP_KERNEL);
209*4882a593Smuzhiyun 	if (!drproc->mem)
210*4882a593Smuzhiyun 		return -ENOMEM;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	for (i = 0; i < num_mems; i++) {
213*4882a593Smuzhiyun 		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
214*4882a593Smuzhiyun 						   mem_names[i]);
215*4882a593Smuzhiyun 		drproc->mem[i].cpu_addr = devm_ioremap_resource(dev, res);
216*4882a593Smuzhiyun 		if (IS_ERR(drproc->mem[i].cpu_addr)) {
217*4882a593Smuzhiyun 			dev_err(dev, "failed to parse and map %s memory\n",
218*4882a593Smuzhiyun 				mem_names[i]);
219*4882a593Smuzhiyun 			return PTR_ERR(drproc->mem[i].cpu_addr);
220*4882a593Smuzhiyun 		}
221*4882a593Smuzhiyun 		drproc->mem[i].bus_addr = res->start;
222*4882a593Smuzhiyun 		drproc->mem[i].dev_addr =
223*4882a593Smuzhiyun 				res->start & DA8XX_RPROC_LOCAL_ADDRESS_MASK;
224*4882a593Smuzhiyun 		drproc->mem[i].size = resource_size(res);
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 		dev_dbg(dev, "memory %8s: bus addr %pa size 0x%zx va %p da 0x%x\n",
227*4882a593Smuzhiyun 			mem_names[i], &drproc->mem[i].bus_addr,
228*4882a593Smuzhiyun 			drproc->mem[i].size, drproc->mem[i].cpu_addr,
229*4882a593Smuzhiyun 			drproc->mem[i].dev_addr);
230*4882a593Smuzhiyun 	}
231*4882a593Smuzhiyun 	drproc->num_mems = num_mems;
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	return 0;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun 
da8xx_rproc_probe(struct platform_device * pdev)236*4882a593Smuzhiyun static int da8xx_rproc_probe(struct platform_device *pdev)
237*4882a593Smuzhiyun {
238*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
239*4882a593Smuzhiyun 	struct da8xx_rproc *drproc;
240*4882a593Smuzhiyun 	struct rproc *rproc;
241*4882a593Smuzhiyun 	struct irq_data *irq_data;
242*4882a593Smuzhiyun 	struct resource *bootreg_res;
243*4882a593Smuzhiyun 	struct resource *chipsig_res;
244*4882a593Smuzhiyun 	struct clk *dsp_clk;
245*4882a593Smuzhiyun 	struct reset_control *dsp_reset;
246*4882a593Smuzhiyun 	void __iomem *chipsig;
247*4882a593Smuzhiyun 	void __iomem *bootreg;
248*4882a593Smuzhiyun 	int irq;
249*4882a593Smuzhiyun 	int ret;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	irq = platform_get_irq(pdev, 0);
252*4882a593Smuzhiyun 	if (irq < 0)
253*4882a593Smuzhiyun 		return irq;
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	irq_data = irq_get_irq_data(irq);
256*4882a593Smuzhiyun 	if (!irq_data) {
257*4882a593Smuzhiyun 		dev_err(dev, "irq_get_irq_data(%d): NULL\n", irq);
258*4882a593Smuzhiyun 		return -EINVAL;
259*4882a593Smuzhiyun 	}
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	bootreg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
262*4882a593Smuzhiyun 						   "host1cfg");
263*4882a593Smuzhiyun 	bootreg = devm_ioremap_resource(dev, bootreg_res);
264*4882a593Smuzhiyun 	if (IS_ERR(bootreg))
265*4882a593Smuzhiyun 		return PTR_ERR(bootreg);
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	chipsig_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
268*4882a593Smuzhiyun 						   "chipsig");
269*4882a593Smuzhiyun 	chipsig = devm_ioremap_resource(dev, chipsig_res);
270*4882a593Smuzhiyun 	if (IS_ERR(chipsig))
271*4882a593Smuzhiyun 		return PTR_ERR(chipsig);
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	dsp_clk = devm_clk_get(dev, NULL);
274*4882a593Smuzhiyun 	if (IS_ERR(dsp_clk)) {
275*4882a593Smuzhiyun 		dev_err(dev, "clk_get error: %ld\n", PTR_ERR(dsp_clk));
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 		return PTR_ERR(dsp_clk);
278*4882a593Smuzhiyun 	}
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	dsp_reset = devm_reset_control_get_exclusive(dev, NULL);
281*4882a593Smuzhiyun 	if (IS_ERR(dsp_reset)) {
282*4882a593Smuzhiyun 		if (PTR_ERR(dsp_reset) != -EPROBE_DEFER)
283*4882a593Smuzhiyun 			dev_err(dev, "unable to get reset control: %ld\n",
284*4882a593Smuzhiyun 				PTR_ERR(dsp_reset));
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 		return PTR_ERR(dsp_reset);
287*4882a593Smuzhiyun 	}
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	if (dev->of_node) {
290*4882a593Smuzhiyun 		ret = of_reserved_mem_device_init(dev);
291*4882a593Smuzhiyun 		if (ret) {
292*4882a593Smuzhiyun 			dev_err(dev, "device does not have specific CMA pool: %d\n",
293*4882a593Smuzhiyun 				ret);
294*4882a593Smuzhiyun 			return ret;
295*4882a593Smuzhiyun 		}
296*4882a593Smuzhiyun 	}
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	rproc = rproc_alloc(dev, "dsp", &da8xx_rproc_ops, da8xx_fw_name,
299*4882a593Smuzhiyun 		sizeof(*drproc));
300*4882a593Smuzhiyun 	if (!rproc) {
301*4882a593Smuzhiyun 		ret = -ENOMEM;
302*4882a593Smuzhiyun 		goto free_mem;
303*4882a593Smuzhiyun 	}
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 	/* error recovery is not supported at present */
306*4882a593Smuzhiyun 	rproc->recovery_disabled = true;
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun 	drproc = rproc->priv;
309*4882a593Smuzhiyun 	drproc->rproc = rproc;
310*4882a593Smuzhiyun 	drproc->dsp_clk = dsp_clk;
311*4882a593Smuzhiyun 	drproc->dsp_reset = dsp_reset;
312*4882a593Smuzhiyun 	rproc->has_iommu = false;
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 	ret = da8xx_rproc_get_internal_memories(pdev, drproc);
315*4882a593Smuzhiyun 	if (ret)
316*4882a593Smuzhiyun 		goto free_rproc;
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	platform_set_drvdata(pdev, rproc);
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun 	/* everything the ISR needs is now setup, so hook it up */
321*4882a593Smuzhiyun 	ret = devm_request_threaded_irq(dev, irq, da8xx_rproc_callback,
322*4882a593Smuzhiyun 					handle_event, 0, "da8xx-remoteproc",
323*4882a593Smuzhiyun 					rproc);
324*4882a593Smuzhiyun 	if (ret) {
325*4882a593Smuzhiyun 		dev_err(dev, "devm_request_threaded_irq error: %d\n", ret);
326*4882a593Smuzhiyun 		goto free_rproc;
327*4882a593Smuzhiyun 	}
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	/*
330*4882a593Smuzhiyun 	 * rproc_add() can end up enabling the DSP's clk with the DSP
331*4882a593Smuzhiyun 	 * *not* in reset, but da8xx_rproc_start() needs the DSP to be
332*4882a593Smuzhiyun 	 * held in reset at the time it is called.
333*4882a593Smuzhiyun 	 */
334*4882a593Smuzhiyun 	ret = reset_control_assert(dsp_reset);
335*4882a593Smuzhiyun 	if (ret)
336*4882a593Smuzhiyun 		goto free_rproc;
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 	drproc->chipsig = chipsig;
339*4882a593Smuzhiyun 	drproc->bootreg = bootreg;
340*4882a593Smuzhiyun 	drproc->ack_fxn = irq_data->chip->irq_ack;
341*4882a593Smuzhiyun 	drproc->irq_data = irq_data;
342*4882a593Smuzhiyun 	drproc->irq = irq;
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 	ret = rproc_add(rproc);
345*4882a593Smuzhiyun 	if (ret) {
346*4882a593Smuzhiyun 		dev_err(dev, "rproc_add failed: %d\n", ret);
347*4882a593Smuzhiyun 		goto free_rproc;
348*4882a593Smuzhiyun 	}
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	return 0;
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun free_rproc:
353*4882a593Smuzhiyun 	rproc_free(rproc);
354*4882a593Smuzhiyun free_mem:
355*4882a593Smuzhiyun 	if (dev->of_node)
356*4882a593Smuzhiyun 		of_reserved_mem_device_release(dev);
357*4882a593Smuzhiyun 	return ret;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun 
da8xx_rproc_remove(struct platform_device * pdev)360*4882a593Smuzhiyun static int da8xx_rproc_remove(struct platform_device *pdev)
361*4882a593Smuzhiyun {
362*4882a593Smuzhiyun 	struct rproc *rproc = platform_get_drvdata(pdev);
363*4882a593Smuzhiyun 	struct da8xx_rproc *drproc = (struct da8xx_rproc *)rproc->priv;
364*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun 	/*
367*4882a593Smuzhiyun 	 * The devm subsystem might end up releasing things before
368*4882a593Smuzhiyun 	 * freeing the irq, thus allowing an interrupt to sneak in while
369*4882a593Smuzhiyun 	 * the device is being removed.  This should prevent that.
370*4882a593Smuzhiyun 	 */
371*4882a593Smuzhiyun 	disable_irq(drproc->irq);
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun 	rproc_del(rproc);
374*4882a593Smuzhiyun 	rproc_free(rproc);
375*4882a593Smuzhiyun 	if (dev->of_node)
376*4882a593Smuzhiyun 		of_reserved_mem_device_release(dev);
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	return 0;
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun static const struct of_device_id davinci_rproc_of_match[] __maybe_unused = {
382*4882a593Smuzhiyun 	{ .compatible = "ti,da850-dsp", },
383*4882a593Smuzhiyun 	{ /* sentinel */ },
384*4882a593Smuzhiyun };
385*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, davinci_rproc_of_match);
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun static struct platform_driver da8xx_rproc_driver = {
388*4882a593Smuzhiyun 	.probe = da8xx_rproc_probe,
389*4882a593Smuzhiyun 	.remove = da8xx_rproc_remove,
390*4882a593Smuzhiyun 	.driver = {
391*4882a593Smuzhiyun 		.name = "davinci-rproc",
392*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(davinci_rproc_of_match),
393*4882a593Smuzhiyun 	},
394*4882a593Smuzhiyun };
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun module_platform_driver(da8xx_rproc_driver);
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
399*4882a593Smuzhiyun MODULE_DESCRIPTION("DA8XX Remote Processor control driver");
400