1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // wm831x-dcdc.c -- DC-DC buck converter driver for the WM831x series
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Copyright 2009 Wolfson Microelectronics PLC.
6*4882a593Smuzhiyun //
7*4882a593Smuzhiyun // Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/moduleparam.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/bitops.h>
13*4882a593Smuzhiyun #include <linux/err.h>
14*4882a593Smuzhiyun #include <linux/i2c.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/regulator/driver.h>
17*4882a593Smuzhiyun #include <linux/regulator/machine.h>
18*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <linux/mfd/wm831x/core.h>
22*4882a593Smuzhiyun #include <linux/mfd/wm831x/regulator.h>
23*4882a593Smuzhiyun #include <linux/mfd/wm831x/pdata.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define WM831X_BUCKV_MAX_SELECTOR 0x68
26*4882a593Smuzhiyun #define WM831X_BUCKP_MAX_SELECTOR 0x66
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define WM831X_DCDC_MODE_FAST 0
29*4882a593Smuzhiyun #define WM831X_DCDC_MODE_NORMAL 1
30*4882a593Smuzhiyun #define WM831X_DCDC_MODE_IDLE 2
31*4882a593Smuzhiyun #define WM831X_DCDC_MODE_STANDBY 3
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define WM831X_DCDC_MAX_NAME 9
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Register offsets in control block */
36*4882a593Smuzhiyun #define WM831X_DCDC_CONTROL_1 0
37*4882a593Smuzhiyun #define WM831X_DCDC_CONTROL_2 1
38*4882a593Smuzhiyun #define WM831X_DCDC_ON_CONFIG 2
39*4882a593Smuzhiyun #define WM831X_DCDC_SLEEP_CONTROL 3
40*4882a593Smuzhiyun #define WM831X_DCDC_DVS_CONTROL 4
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /*
43*4882a593Smuzhiyun * Shared
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun struct wm831x_dcdc {
47*4882a593Smuzhiyun char name[WM831X_DCDC_MAX_NAME];
48*4882a593Smuzhiyun char supply_name[WM831X_DCDC_MAX_NAME];
49*4882a593Smuzhiyun struct regulator_desc desc;
50*4882a593Smuzhiyun int base;
51*4882a593Smuzhiyun struct wm831x *wm831x;
52*4882a593Smuzhiyun struct regulator_dev *regulator;
53*4882a593Smuzhiyun struct gpio_desc *dvs_gpiod;
54*4882a593Smuzhiyun int dvs_gpio_state;
55*4882a593Smuzhiyun int on_vsel;
56*4882a593Smuzhiyun int dvs_vsel;
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
wm831x_dcdc_get_mode(struct regulator_dev * rdev)59*4882a593Smuzhiyun static unsigned int wm831x_dcdc_get_mode(struct regulator_dev *rdev)
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
63*4882a593Smuzhiyun struct wm831x *wm831x = dcdc->wm831x;
64*4882a593Smuzhiyun u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
65*4882a593Smuzhiyun int val;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun val = wm831x_reg_read(wm831x, reg);
68*4882a593Smuzhiyun if (val < 0)
69*4882a593Smuzhiyun return val;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun val = (val & WM831X_DC1_ON_MODE_MASK) >> WM831X_DC1_ON_MODE_SHIFT;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun switch (val) {
74*4882a593Smuzhiyun case WM831X_DCDC_MODE_FAST:
75*4882a593Smuzhiyun return REGULATOR_MODE_FAST;
76*4882a593Smuzhiyun case WM831X_DCDC_MODE_NORMAL:
77*4882a593Smuzhiyun return REGULATOR_MODE_NORMAL;
78*4882a593Smuzhiyun case WM831X_DCDC_MODE_STANDBY:
79*4882a593Smuzhiyun return REGULATOR_MODE_STANDBY;
80*4882a593Smuzhiyun case WM831X_DCDC_MODE_IDLE:
81*4882a593Smuzhiyun return REGULATOR_MODE_IDLE;
82*4882a593Smuzhiyun default:
83*4882a593Smuzhiyun BUG();
84*4882a593Smuzhiyun return -EINVAL;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
wm831x_dcdc_set_mode_int(struct wm831x * wm831x,int reg,unsigned int mode)88*4882a593Smuzhiyun static int wm831x_dcdc_set_mode_int(struct wm831x *wm831x, int reg,
89*4882a593Smuzhiyun unsigned int mode)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun int val;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun switch (mode) {
94*4882a593Smuzhiyun case REGULATOR_MODE_FAST:
95*4882a593Smuzhiyun val = WM831X_DCDC_MODE_FAST;
96*4882a593Smuzhiyun break;
97*4882a593Smuzhiyun case REGULATOR_MODE_NORMAL:
98*4882a593Smuzhiyun val = WM831X_DCDC_MODE_NORMAL;
99*4882a593Smuzhiyun break;
100*4882a593Smuzhiyun case REGULATOR_MODE_STANDBY:
101*4882a593Smuzhiyun val = WM831X_DCDC_MODE_STANDBY;
102*4882a593Smuzhiyun break;
103*4882a593Smuzhiyun case REGULATOR_MODE_IDLE:
104*4882a593Smuzhiyun val = WM831X_DCDC_MODE_IDLE;
105*4882a593Smuzhiyun break;
106*4882a593Smuzhiyun default:
107*4882a593Smuzhiyun return -EINVAL;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun return wm831x_set_bits(wm831x, reg, WM831X_DC1_ON_MODE_MASK,
111*4882a593Smuzhiyun val << WM831X_DC1_ON_MODE_SHIFT);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
wm831x_dcdc_set_mode(struct regulator_dev * rdev,unsigned int mode)114*4882a593Smuzhiyun static int wm831x_dcdc_set_mode(struct regulator_dev *rdev, unsigned int mode)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
117*4882a593Smuzhiyun struct wm831x *wm831x = dcdc->wm831x;
118*4882a593Smuzhiyun u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun return wm831x_dcdc_set_mode_int(wm831x, reg, mode);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
wm831x_dcdc_set_suspend_mode(struct regulator_dev * rdev,unsigned int mode)123*4882a593Smuzhiyun static int wm831x_dcdc_set_suspend_mode(struct regulator_dev *rdev,
124*4882a593Smuzhiyun unsigned int mode)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
127*4882a593Smuzhiyun struct wm831x *wm831x = dcdc->wm831x;
128*4882a593Smuzhiyun u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun return wm831x_dcdc_set_mode_int(wm831x, reg, mode);
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
wm831x_dcdc_get_status(struct regulator_dev * rdev)133*4882a593Smuzhiyun static int wm831x_dcdc_get_status(struct regulator_dev *rdev)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
136*4882a593Smuzhiyun struct wm831x *wm831x = dcdc->wm831x;
137*4882a593Smuzhiyun int ret;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun /* First, check for errors */
140*4882a593Smuzhiyun ret = wm831x_reg_read(wm831x, WM831X_DCDC_UV_STATUS);
141*4882a593Smuzhiyun if (ret < 0)
142*4882a593Smuzhiyun return ret;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun if (ret & (1 << rdev_get_id(rdev))) {
145*4882a593Smuzhiyun dev_dbg(wm831x->dev, "DCDC%d under voltage\n",
146*4882a593Smuzhiyun rdev_get_id(rdev) + 1);
147*4882a593Smuzhiyun return REGULATOR_STATUS_ERROR;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun /* DCDC1 and DCDC2 can additionally detect high voltage/current */
151*4882a593Smuzhiyun if (rdev_get_id(rdev) < 2) {
152*4882a593Smuzhiyun if (ret & (WM831X_DC1_OV_STS << rdev_get_id(rdev))) {
153*4882a593Smuzhiyun dev_dbg(wm831x->dev, "DCDC%d over voltage\n",
154*4882a593Smuzhiyun rdev_get_id(rdev) + 1);
155*4882a593Smuzhiyun return REGULATOR_STATUS_ERROR;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun if (ret & (WM831X_DC1_HC_STS << rdev_get_id(rdev))) {
159*4882a593Smuzhiyun dev_dbg(wm831x->dev, "DCDC%d over current\n",
160*4882a593Smuzhiyun rdev_get_id(rdev) + 1);
161*4882a593Smuzhiyun return REGULATOR_STATUS_ERROR;
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun /* Is the regulator on? */
166*4882a593Smuzhiyun ret = wm831x_reg_read(wm831x, WM831X_DCDC_STATUS);
167*4882a593Smuzhiyun if (ret < 0)
168*4882a593Smuzhiyun return ret;
169*4882a593Smuzhiyun if (!(ret & (1 << rdev_get_id(rdev))))
170*4882a593Smuzhiyun return REGULATOR_STATUS_OFF;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun /* TODO: When we handle hardware control modes so we can report the
173*4882a593Smuzhiyun * current mode. */
174*4882a593Smuzhiyun return REGULATOR_STATUS_ON;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
wm831x_dcdc_uv_irq(int irq,void * data)177*4882a593Smuzhiyun static irqreturn_t wm831x_dcdc_uv_irq(int irq, void *data)
178*4882a593Smuzhiyun {
179*4882a593Smuzhiyun struct wm831x_dcdc *dcdc = data;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun regulator_notifier_call_chain(dcdc->regulator,
182*4882a593Smuzhiyun REGULATOR_EVENT_UNDER_VOLTAGE,
183*4882a593Smuzhiyun NULL);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun return IRQ_HANDLED;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
wm831x_dcdc_oc_irq(int irq,void * data)188*4882a593Smuzhiyun static irqreturn_t wm831x_dcdc_oc_irq(int irq, void *data)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun struct wm831x_dcdc *dcdc = data;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun regulator_notifier_call_chain(dcdc->regulator,
193*4882a593Smuzhiyun REGULATOR_EVENT_OVER_CURRENT,
194*4882a593Smuzhiyun NULL);
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun return IRQ_HANDLED;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun /*
200*4882a593Smuzhiyun * BUCKV specifics
201*4882a593Smuzhiyun */
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun static const struct linear_range wm831x_buckv_ranges[] = {
204*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(600000, 0, 0x7, 0),
205*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(600000, 0x8, 0x68, 12500),
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun
wm831x_buckv_set_dvs(struct regulator_dev * rdev,int state)208*4882a593Smuzhiyun static int wm831x_buckv_set_dvs(struct regulator_dev *rdev, int state)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun if (state == dcdc->dvs_gpio_state)
213*4882a593Smuzhiyun return 0;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun dcdc->dvs_gpio_state = state;
216*4882a593Smuzhiyun gpiod_set_value(dcdc->dvs_gpiod, state);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun /* Should wait for DVS state change to be asserted if we have
219*4882a593Smuzhiyun * a GPIO for it, for now assume the device is configured
220*4882a593Smuzhiyun * for the fastest possible transition.
221*4882a593Smuzhiyun */
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun return 0;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
wm831x_buckv_set_voltage_sel(struct regulator_dev * rdev,unsigned vsel)226*4882a593Smuzhiyun static int wm831x_buckv_set_voltage_sel(struct regulator_dev *rdev,
227*4882a593Smuzhiyun unsigned vsel)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
230*4882a593Smuzhiyun struct wm831x *wm831x = dcdc->wm831x;
231*4882a593Smuzhiyun int on_reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
232*4882a593Smuzhiyun int dvs_reg = dcdc->base + WM831X_DCDC_DVS_CONTROL;
233*4882a593Smuzhiyun int ret;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun /* If this value is already set then do a GPIO update if we can */
236*4882a593Smuzhiyun if (dcdc->dvs_gpiod && dcdc->on_vsel == vsel)
237*4882a593Smuzhiyun return wm831x_buckv_set_dvs(rdev, 0);
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun if (dcdc->dvs_gpiod && dcdc->dvs_vsel == vsel)
240*4882a593Smuzhiyun return wm831x_buckv_set_dvs(rdev, 1);
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun /* Always set the ON status to the minimum voltage */
243*4882a593Smuzhiyun ret = wm831x_set_bits(wm831x, on_reg, WM831X_DC1_ON_VSEL_MASK, vsel);
244*4882a593Smuzhiyun if (ret < 0)
245*4882a593Smuzhiyun return ret;
246*4882a593Smuzhiyun dcdc->on_vsel = vsel;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun if (!dcdc->dvs_gpiod)
249*4882a593Smuzhiyun return ret;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun /* Kick the voltage transition now */
252*4882a593Smuzhiyun ret = wm831x_buckv_set_dvs(rdev, 0);
253*4882a593Smuzhiyun if (ret < 0)
254*4882a593Smuzhiyun return ret;
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun /*
257*4882a593Smuzhiyun * If this VSEL is higher than the last one we've seen then
258*4882a593Smuzhiyun * remember it as the DVS VSEL. This is optimised for CPUfreq
259*4882a593Smuzhiyun * usage where we want to get to the highest voltage very
260*4882a593Smuzhiyun * quickly.
261*4882a593Smuzhiyun */
262*4882a593Smuzhiyun if (vsel > dcdc->dvs_vsel) {
263*4882a593Smuzhiyun ret = wm831x_set_bits(wm831x, dvs_reg,
264*4882a593Smuzhiyun WM831X_DC1_DVS_VSEL_MASK,
265*4882a593Smuzhiyun vsel);
266*4882a593Smuzhiyun if (ret == 0)
267*4882a593Smuzhiyun dcdc->dvs_vsel = vsel;
268*4882a593Smuzhiyun else
269*4882a593Smuzhiyun dev_warn(wm831x->dev,
270*4882a593Smuzhiyun "Failed to set DCDC DVS VSEL: %d\n", ret);
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun return 0;
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun
wm831x_buckv_set_suspend_voltage(struct regulator_dev * rdev,int uV)276*4882a593Smuzhiyun static int wm831x_buckv_set_suspend_voltage(struct regulator_dev *rdev,
277*4882a593Smuzhiyun int uV)
278*4882a593Smuzhiyun {
279*4882a593Smuzhiyun struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
280*4882a593Smuzhiyun struct wm831x *wm831x = dcdc->wm831x;
281*4882a593Smuzhiyun u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL;
282*4882a593Smuzhiyun int vsel;
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun vsel = regulator_map_voltage_linear_range(rdev, uV, uV);
285*4882a593Smuzhiyun if (vsel < 0)
286*4882a593Smuzhiyun return vsel;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun return wm831x_set_bits(wm831x, reg, WM831X_DC1_SLP_VSEL_MASK, vsel);
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun
wm831x_buckv_get_voltage_sel(struct regulator_dev * rdev)291*4882a593Smuzhiyun static int wm831x_buckv_get_voltage_sel(struct regulator_dev *rdev)
292*4882a593Smuzhiyun {
293*4882a593Smuzhiyun struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun if (dcdc->dvs_gpiod && dcdc->dvs_gpio_state)
296*4882a593Smuzhiyun return dcdc->dvs_vsel;
297*4882a593Smuzhiyun else
298*4882a593Smuzhiyun return dcdc->on_vsel;
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun /* Current limit options */
302*4882a593Smuzhiyun static const unsigned int wm831x_dcdc_ilim[] = {
303*4882a593Smuzhiyun 125000, 250000, 375000, 500000, 625000, 750000, 875000, 1000000
304*4882a593Smuzhiyun };
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun static const struct regulator_ops wm831x_buckv_ops = {
307*4882a593Smuzhiyun .set_voltage_sel = wm831x_buckv_set_voltage_sel,
308*4882a593Smuzhiyun .get_voltage_sel = wm831x_buckv_get_voltage_sel,
309*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
310*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
311*4882a593Smuzhiyun .set_suspend_voltage = wm831x_buckv_set_suspend_voltage,
312*4882a593Smuzhiyun .set_current_limit = regulator_set_current_limit_regmap,
313*4882a593Smuzhiyun .get_current_limit = regulator_get_current_limit_regmap,
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
316*4882a593Smuzhiyun .enable = regulator_enable_regmap,
317*4882a593Smuzhiyun .disable = regulator_disable_regmap,
318*4882a593Smuzhiyun .get_status = wm831x_dcdc_get_status,
319*4882a593Smuzhiyun .get_mode = wm831x_dcdc_get_mode,
320*4882a593Smuzhiyun .set_mode = wm831x_dcdc_set_mode,
321*4882a593Smuzhiyun .set_suspend_mode = wm831x_dcdc_set_suspend_mode,
322*4882a593Smuzhiyun };
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun /*
325*4882a593Smuzhiyun * Set up DVS control. We just log errors since we can still run
326*4882a593Smuzhiyun * (with reduced performance) if we fail.
327*4882a593Smuzhiyun */
wm831x_buckv_dvs_init(struct platform_device * pdev,struct wm831x_dcdc * dcdc,struct wm831x_buckv_pdata * pdata)328*4882a593Smuzhiyun static void wm831x_buckv_dvs_init(struct platform_device *pdev,
329*4882a593Smuzhiyun struct wm831x_dcdc *dcdc,
330*4882a593Smuzhiyun struct wm831x_buckv_pdata *pdata)
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun struct wm831x *wm831x = dcdc->wm831x;
333*4882a593Smuzhiyun int ret;
334*4882a593Smuzhiyun u16 ctrl;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun if (!pdata)
337*4882a593Smuzhiyun return;
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun /* gpiolib won't let us read the GPIO status so pick the higher
340*4882a593Smuzhiyun * of the two existing voltages so we take it as platform data.
341*4882a593Smuzhiyun */
342*4882a593Smuzhiyun dcdc->dvs_gpio_state = pdata->dvs_init_state;
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun dcdc->dvs_gpiod = devm_gpiod_get(&pdev->dev, "dvs",
345*4882a593Smuzhiyun dcdc->dvs_gpio_state ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW);
346*4882a593Smuzhiyun if (IS_ERR(dcdc->dvs_gpiod)) {
347*4882a593Smuzhiyun dev_err(wm831x->dev, "Failed to get %s DVS GPIO: %ld\n",
348*4882a593Smuzhiyun dcdc->name, PTR_ERR(dcdc->dvs_gpiod));
349*4882a593Smuzhiyun return;
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun switch (pdata->dvs_control_src) {
353*4882a593Smuzhiyun case 1:
354*4882a593Smuzhiyun ctrl = 2 << WM831X_DC1_DVS_SRC_SHIFT;
355*4882a593Smuzhiyun break;
356*4882a593Smuzhiyun case 2:
357*4882a593Smuzhiyun ctrl = 3 << WM831X_DC1_DVS_SRC_SHIFT;
358*4882a593Smuzhiyun break;
359*4882a593Smuzhiyun default:
360*4882a593Smuzhiyun dev_err(wm831x->dev, "Invalid DVS control source %d for %s\n",
361*4882a593Smuzhiyun pdata->dvs_control_src, dcdc->name);
362*4882a593Smuzhiyun return;
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun /* If DVS_VSEL is set to the minimum value then raise it to ON_VSEL
366*4882a593Smuzhiyun * to make bootstrapping a bit smoother.
367*4882a593Smuzhiyun */
368*4882a593Smuzhiyun if (!dcdc->dvs_vsel) {
369*4882a593Smuzhiyun ret = wm831x_set_bits(wm831x,
370*4882a593Smuzhiyun dcdc->base + WM831X_DCDC_DVS_CONTROL,
371*4882a593Smuzhiyun WM831X_DC1_DVS_VSEL_MASK, dcdc->on_vsel);
372*4882a593Smuzhiyun if (ret == 0)
373*4882a593Smuzhiyun dcdc->dvs_vsel = dcdc->on_vsel;
374*4882a593Smuzhiyun else
375*4882a593Smuzhiyun dev_warn(wm831x->dev, "Failed to set DVS_VSEL: %d\n",
376*4882a593Smuzhiyun ret);
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun ret = wm831x_set_bits(wm831x, dcdc->base + WM831X_DCDC_DVS_CONTROL,
380*4882a593Smuzhiyun WM831X_DC1_DVS_SRC_MASK, ctrl);
381*4882a593Smuzhiyun if (ret < 0) {
382*4882a593Smuzhiyun dev_err(wm831x->dev, "Failed to set %s DVS source: %d\n",
383*4882a593Smuzhiyun dcdc->name, ret);
384*4882a593Smuzhiyun }
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun
wm831x_buckv_probe(struct platform_device * pdev)387*4882a593Smuzhiyun static int wm831x_buckv_probe(struct platform_device *pdev)
388*4882a593Smuzhiyun {
389*4882a593Smuzhiyun struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
390*4882a593Smuzhiyun struct wm831x_pdata *pdata = dev_get_platdata(wm831x->dev);
391*4882a593Smuzhiyun struct regulator_config config = { };
392*4882a593Smuzhiyun int id;
393*4882a593Smuzhiyun struct wm831x_dcdc *dcdc;
394*4882a593Smuzhiyun struct resource *res;
395*4882a593Smuzhiyun int ret, irq;
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun if (pdata && pdata->wm831x_num)
398*4882a593Smuzhiyun id = (pdata->wm831x_num * 10) + 1;
399*4882a593Smuzhiyun else
400*4882a593Smuzhiyun id = 0;
401*4882a593Smuzhiyun id = pdev->id - id;
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun dev_dbg(&pdev->dev, "Probing DCDC%d\n", id + 1);
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun dcdc = devm_kzalloc(&pdev->dev, sizeof(struct wm831x_dcdc),
406*4882a593Smuzhiyun GFP_KERNEL);
407*4882a593Smuzhiyun if (!dcdc)
408*4882a593Smuzhiyun return -ENOMEM;
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun dcdc->wm831x = wm831x;
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_REG, 0);
413*4882a593Smuzhiyun if (res == NULL) {
414*4882a593Smuzhiyun dev_err(&pdev->dev, "No REG resource\n");
415*4882a593Smuzhiyun ret = -EINVAL;
416*4882a593Smuzhiyun goto err;
417*4882a593Smuzhiyun }
418*4882a593Smuzhiyun dcdc->base = res->start;
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun snprintf(dcdc->name, sizeof(dcdc->name), "DCDC%d", id + 1);
421*4882a593Smuzhiyun dcdc->desc.name = dcdc->name;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun snprintf(dcdc->supply_name, sizeof(dcdc->supply_name),
424*4882a593Smuzhiyun "DC%dVDD", id + 1);
425*4882a593Smuzhiyun dcdc->desc.supply_name = dcdc->supply_name;
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun dcdc->desc.id = id;
428*4882a593Smuzhiyun dcdc->desc.type = REGULATOR_VOLTAGE;
429*4882a593Smuzhiyun dcdc->desc.n_voltages = WM831X_BUCKV_MAX_SELECTOR + 1;
430*4882a593Smuzhiyun dcdc->desc.linear_ranges = wm831x_buckv_ranges;
431*4882a593Smuzhiyun dcdc->desc.n_linear_ranges = ARRAY_SIZE(wm831x_buckv_ranges);
432*4882a593Smuzhiyun dcdc->desc.ops = &wm831x_buckv_ops;
433*4882a593Smuzhiyun dcdc->desc.owner = THIS_MODULE;
434*4882a593Smuzhiyun dcdc->desc.enable_reg = WM831X_DCDC_ENABLE;
435*4882a593Smuzhiyun dcdc->desc.enable_mask = 1 << id;
436*4882a593Smuzhiyun dcdc->desc.csel_reg = dcdc->base + WM831X_DCDC_CONTROL_2;
437*4882a593Smuzhiyun dcdc->desc.csel_mask = WM831X_DC1_HC_THR_MASK;
438*4882a593Smuzhiyun dcdc->desc.n_current_limits = ARRAY_SIZE(wm831x_dcdc_ilim);
439*4882a593Smuzhiyun dcdc->desc.curr_table = wm831x_dcdc_ilim;
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun ret = wm831x_reg_read(wm831x, dcdc->base + WM831X_DCDC_ON_CONFIG);
442*4882a593Smuzhiyun if (ret < 0) {
443*4882a593Smuzhiyun dev_err(wm831x->dev, "Failed to read ON VSEL: %d\n", ret);
444*4882a593Smuzhiyun goto err;
445*4882a593Smuzhiyun }
446*4882a593Smuzhiyun dcdc->on_vsel = ret & WM831X_DC1_ON_VSEL_MASK;
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun ret = wm831x_reg_read(wm831x, dcdc->base + WM831X_DCDC_DVS_CONTROL);
449*4882a593Smuzhiyun if (ret < 0) {
450*4882a593Smuzhiyun dev_err(wm831x->dev, "Failed to read DVS VSEL: %d\n", ret);
451*4882a593Smuzhiyun goto err;
452*4882a593Smuzhiyun }
453*4882a593Smuzhiyun dcdc->dvs_vsel = ret & WM831X_DC1_DVS_VSEL_MASK;
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun if (pdata && pdata->dcdc[id])
456*4882a593Smuzhiyun wm831x_buckv_dvs_init(pdev, dcdc,
457*4882a593Smuzhiyun pdata->dcdc[id]->driver_data);
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun config.dev = pdev->dev.parent;
460*4882a593Smuzhiyun if (pdata)
461*4882a593Smuzhiyun config.init_data = pdata->dcdc[id];
462*4882a593Smuzhiyun config.driver_data = dcdc;
463*4882a593Smuzhiyun config.regmap = wm831x->regmap;
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun dcdc->regulator = devm_regulator_register(&pdev->dev, &dcdc->desc,
466*4882a593Smuzhiyun &config);
467*4882a593Smuzhiyun if (IS_ERR(dcdc->regulator)) {
468*4882a593Smuzhiyun ret = PTR_ERR(dcdc->regulator);
469*4882a593Smuzhiyun dev_err(wm831x->dev, "Failed to register DCDC%d: %d\n",
470*4882a593Smuzhiyun id + 1, ret);
471*4882a593Smuzhiyun goto err;
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "UV"));
475*4882a593Smuzhiyun ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
476*4882a593Smuzhiyun wm831x_dcdc_uv_irq,
477*4882a593Smuzhiyun IRQF_TRIGGER_RISING | IRQF_ONESHOT,
478*4882a593Smuzhiyun dcdc->name, dcdc);
479*4882a593Smuzhiyun if (ret != 0) {
480*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to request UV IRQ %d: %d\n",
481*4882a593Smuzhiyun irq, ret);
482*4882a593Smuzhiyun goto err;
483*4882a593Smuzhiyun }
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "HC"));
486*4882a593Smuzhiyun ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
487*4882a593Smuzhiyun wm831x_dcdc_oc_irq,
488*4882a593Smuzhiyun IRQF_TRIGGER_RISING | IRQF_ONESHOT,
489*4882a593Smuzhiyun dcdc->name, dcdc);
490*4882a593Smuzhiyun if (ret != 0) {
491*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to request HC IRQ %d: %d\n",
492*4882a593Smuzhiyun irq, ret);
493*4882a593Smuzhiyun goto err;
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun platform_set_drvdata(pdev, dcdc);
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun return 0;
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun err:
501*4882a593Smuzhiyun return ret;
502*4882a593Smuzhiyun }
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun static struct platform_driver wm831x_buckv_driver = {
505*4882a593Smuzhiyun .probe = wm831x_buckv_probe,
506*4882a593Smuzhiyun .driver = {
507*4882a593Smuzhiyun .name = "wm831x-buckv",
508*4882a593Smuzhiyun },
509*4882a593Smuzhiyun };
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun /*
512*4882a593Smuzhiyun * BUCKP specifics
513*4882a593Smuzhiyun */
514*4882a593Smuzhiyun
wm831x_buckp_set_suspend_voltage(struct regulator_dev * rdev,int uV)515*4882a593Smuzhiyun static int wm831x_buckp_set_suspend_voltage(struct regulator_dev *rdev, int uV)
516*4882a593Smuzhiyun {
517*4882a593Smuzhiyun struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
518*4882a593Smuzhiyun struct wm831x *wm831x = dcdc->wm831x;
519*4882a593Smuzhiyun u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL;
520*4882a593Smuzhiyun int sel;
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun sel = regulator_map_voltage_linear(rdev, uV, uV);
523*4882a593Smuzhiyun if (sel < 0)
524*4882a593Smuzhiyun return sel;
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun return wm831x_set_bits(wm831x, reg, WM831X_DC3_ON_VSEL_MASK, sel);
527*4882a593Smuzhiyun }
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun static const struct regulator_ops wm831x_buckp_ops = {
530*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
531*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
532*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
533*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear,
534*4882a593Smuzhiyun .set_suspend_voltage = wm831x_buckp_set_suspend_voltage,
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
537*4882a593Smuzhiyun .enable = regulator_enable_regmap,
538*4882a593Smuzhiyun .disable = regulator_disable_regmap,
539*4882a593Smuzhiyun .get_status = wm831x_dcdc_get_status,
540*4882a593Smuzhiyun .get_mode = wm831x_dcdc_get_mode,
541*4882a593Smuzhiyun .set_mode = wm831x_dcdc_set_mode,
542*4882a593Smuzhiyun .set_suspend_mode = wm831x_dcdc_set_suspend_mode,
543*4882a593Smuzhiyun };
544*4882a593Smuzhiyun
wm831x_buckp_probe(struct platform_device * pdev)545*4882a593Smuzhiyun static int wm831x_buckp_probe(struct platform_device *pdev)
546*4882a593Smuzhiyun {
547*4882a593Smuzhiyun struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
548*4882a593Smuzhiyun struct wm831x_pdata *pdata = dev_get_platdata(wm831x->dev);
549*4882a593Smuzhiyun struct regulator_config config = { };
550*4882a593Smuzhiyun int id;
551*4882a593Smuzhiyun struct wm831x_dcdc *dcdc;
552*4882a593Smuzhiyun struct resource *res;
553*4882a593Smuzhiyun int ret, irq;
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun if (pdata && pdata->wm831x_num)
556*4882a593Smuzhiyun id = (pdata->wm831x_num * 10) + 1;
557*4882a593Smuzhiyun else
558*4882a593Smuzhiyun id = 0;
559*4882a593Smuzhiyun id = pdev->id - id;
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun dev_dbg(&pdev->dev, "Probing DCDC%d\n", id + 1);
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun dcdc = devm_kzalloc(&pdev->dev, sizeof(struct wm831x_dcdc),
564*4882a593Smuzhiyun GFP_KERNEL);
565*4882a593Smuzhiyun if (!dcdc)
566*4882a593Smuzhiyun return -ENOMEM;
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun dcdc->wm831x = wm831x;
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_REG, 0);
571*4882a593Smuzhiyun if (res == NULL) {
572*4882a593Smuzhiyun dev_err(&pdev->dev, "No REG resource\n");
573*4882a593Smuzhiyun ret = -EINVAL;
574*4882a593Smuzhiyun goto err;
575*4882a593Smuzhiyun }
576*4882a593Smuzhiyun dcdc->base = res->start;
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun snprintf(dcdc->name, sizeof(dcdc->name), "DCDC%d", id + 1);
579*4882a593Smuzhiyun dcdc->desc.name = dcdc->name;
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun snprintf(dcdc->supply_name, sizeof(dcdc->supply_name),
582*4882a593Smuzhiyun "DC%dVDD", id + 1);
583*4882a593Smuzhiyun dcdc->desc.supply_name = dcdc->supply_name;
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun dcdc->desc.id = id;
586*4882a593Smuzhiyun dcdc->desc.type = REGULATOR_VOLTAGE;
587*4882a593Smuzhiyun dcdc->desc.n_voltages = WM831X_BUCKP_MAX_SELECTOR + 1;
588*4882a593Smuzhiyun dcdc->desc.ops = &wm831x_buckp_ops;
589*4882a593Smuzhiyun dcdc->desc.owner = THIS_MODULE;
590*4882a593Smuzhiyun dcdc->desc.vsel_reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
591*4882a593Smuzhiyun dcdc->desc.vsel_mask = WM831X_DC3_ON_VSEL_MASK;
592*4882a593Smuzhiyun dcdc->desc.enable_reg = WM831X_DCDC_ENABLE;
593*4882a593Smuzhiyun dcdc->desc.enable_mask = 1 << id;
594*4882a593Smuzhiyun dcdc->desc.min_uV = 850000;
595*4882a593Smuzhiyun dcdc->desc.uV_step = 25000;
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun config.dev = pdev->dev.parent;
598*4882a593Smuzhiyun if (pdata)
599*4882a593Smuzhiyun config.init_data = pdata->dcdc[id];
600*4882a593Smuzhiyun config.driver_data = dcdc;
601*4882a593Smuzhiyun config.regmap = wm831x->regmap;
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun dcdc->regulator = devm_regulator_register(&pdev->dev, &dcdc->desc,
604*4882a593Smuzhiyun &config);
605*4882a593Smuzhiyun if (IS_ERR(dcdc->regulator)) {
606*4882a593Smuzhiyun ret = PTR_ERR(dcdc->regulator);
607*4882a593Smuzhiyun dev_err(wm831x->dev, "Failed to register DCDC%d: %d\n",
608*4882a593Smuzhiyun id + 1, ret);
609*4882a593Smuzhiyun goto err;
610*4882a593Smuzhiyun }
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "UV"));
613*4882a593Smuzhiyun ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
614*4882a593Smuzhiyun wm831x_dcdc_uv_irq,
615*4882a593Smuzhiyun IRQF_TRIGGER_RISING | IRQF_ONESHOT,
616*4882a593Smuzhiyun dcdc->name, dcdc);
617*4882a593Smuzhiyun if (ret != 0) {
618*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to request UV IRQ %d: %d\n",
619*4882a593Smuzhiyun irq, ret);
620*4882a593Smuzhiyun goto err;
621*4882a593Smuzhiyun }
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun platform_set_drvdata(pdev, dcdc);
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun return 0;
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun err:
628*4882a593Smuzhiyun return ret;
629*4882a593Smuzhiyun }
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun static struct platform_driver wm831x_buckp_driver = {
632*4882a593Smuzhiyun .probe = wm831x_buckp_probe,
633*4882a593Smuzhiyun .driver = {
634*4882a593Smuzhiyun .name = "wm831x-buckp",
635*4882a593Smuzhiyun },
636*4882a593Smuzhiyun };
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun /*
639*4882a593Smuzhiyun * DCDC boost convertors
640*4882a593Smuzhiyun */
641*4882a593Smuzhiyun
wm831x_boostp_get_status(struct regulator_dev * rdev)642*4882a593Smuzhiyun static int wm831x_boostp_get_status(struct regulator_dev *rdev)
643*4882a593Smuzhiyun {
644*4882a593Smuzhiyun struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
645*4882a593Smuzhiyun struct wm831x *wm831x = dcdc->wm831x;
646*4882a593Smuzhiyun int ret;
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun /* First, check for errors */
649*4882a593Smuzhiyun ret = wm831x_reg_read(wm831x, WM831X_DCDC_UV_STATUS);
650*4882a593Smuzhiyun if (ret < 0)
651*4882a593Smuzhiyun return ret;
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun if (ret & (1 << rdev_get_id(rdev))) {
654*4882a593Smuzhiyun dev_dbg(wm831x->dev, "DCDC%d under voltage\n",
655*4882a593Smuzhiyun rdev_get_id(rdev) + 1);
656*4882a593Smuzhiyun return REGULATOR_STATUS_ERROR;
657*4882a593Smuzhiyun }
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun /* Is the regulator on? */
660*4882a593Smuzhiyun ret = wm831x_reg_read(wm831x, WM831X_DCDC_STATUS);
661*4882a593Smuzhiyun if (ret < 0)
662*4882a593Smuzhiyun return ret;
663*4882a593Smuzhiyun if (ret & (1 << rdev_get_id(rdev)))
664*4882a593Smuzhiyun return REGULATOR_STATUS_ON;
665*4882a593Smuzhiyun else
666*4882a593Smuzhiyun return REGULATOR_STATUS_OFF;
667*4882a593Smuzhiyun }
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun static const struct regulator_ops wm831x_boostp_ops = {
670*4882a593Smuzhiyun .get_status = wm831x_boostp_get_status,
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
673*4882a593Smuzhiyun .enable = regulator_enable_regmap,
674*4882a593Smuzhiyun .disable = regulator_disable_regmap,
675*4882a593Smuzhiyun };
676*4882a593Smuzhiyun
wm831x_boostp_probe(struct platform_device * pdev)677*4882a593Smuzhiyun static int wm831x_boostp_probe(struct platform_device *pdev)
678*4882a593Smuzhiyun {
679*4882a593Smuzhiyun struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
680*4882a593Smuzhiyun struct wm831x_pdata *pdata = dev_get_platdata(wm831x->dev);
681*4882a593Smuzhiyun struct regulator_config config = { };
682*4882a593Smuzhiyun int id = pdev->id % ARRAY_SIZE(pdata->dcdc);
683*4882a593Smuzhiyun struct wm831x_dcdc *dcdc;
684*4882a593Smuzhiyun struct resource *res;
685*4882a593Smuzhiyun int ret, irq;
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun dev_dbg(&pdev->dev, "Probing DCDC%d\n", id + 1);
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun if (pdata == NULL || pdata->dcdc[id] == NULL)
690*4882a593Smuzhiyun return -ENODEV;
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun dcdc = devm_kzalloc(&pdev->dev, sizeof(struct wm831x_dcdc), GFP_KERNEL);
693*4882a593Smuzhiyun if (!dcdc)
694*4882a593Smuzhiyun return -ENOMEM;
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun dcdc->wm831x = wm831x;
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_REG, 0);
699*4882a593Smuzhiyun if (res == NULL) {
700*4882a593Smuzhiyun dev_err(&pdev->dev, "No REG resource\n");
701*4882a593Smuzhiyun return -EINVAL;
702*4882a593Smuzhiyun }
703*4882a593Smuzhiyun dcdc->base = res->start;
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun snprintf(dcdc->name, sizeof(dcdc->name), "DCDC%d", id + 1);
706*4882a593Smuzhiyun dcdc->desc.name = dcdc->name;
707*4882a593Smuzhiyun dcdc->desc.id = id;
708*4882a593Smuzhiyun dcdc->desc.type = REGULATOR_VOLTAGE;
709*4882a593Smuzhiyun dcdc->desc.ops = &wm831x_boostp_ops;
710*4882a593Smuzhiyun dcdc->desc.owner = THIS_MODULE;
711*4882a593Smuzhiyun dcdc->desc.enable_reg = WM831X_DCDC_ENABLE;
712*4882a593Smuzhiyun dcdc->desc.enable_mask = 1 << id;
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun config.dev = pdev->dev.parent;
715*4882a593Smuzhiyun if (pdata)
716*4882a593Smuzhiyun config.init_data = pdata->dcdc[id];
717*4882a593Smuzhiyun config.driver_data = dcdc;
718*4882a593Smuzhiyun config.regmap = wm831x->regmap;
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun dcdc->regulator = devm_regulator_register(&pdev->dev, &dcdc->desc,
721*4882a593Smuzhiyun &config);
722*4882a593Smuzhiyun if (IS_ERR(dcdc->regulator)) {
723*4882a593Smuzhiyun ret = PTR_ERR(dcdc->regulator);
724*4882a593Smuzhiyun dev_err(wm831x->dev, "Failed to register DCDC%d: %d\n",
725*4882a593Smuzhiyun id + 1, ret);
726*4882a593Smuzhiyun return ret;
727*4882a593Smuzhiyun }
728*4882a593Smuzhiyun
729*4882a593Smuzhiyun irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "UV"));
730*4882a593Smuzhiyun ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
731*4882a593Smuzhiyun wm831x_dcdc_uv_irq,
732*4882a593Smuzhiyun IRQF_TRIGGER_RISING | IRQF_ONESHOT,
733*4882a593Smuzhiyun dcdc->name,
734*4882a593Smuzhiyun dcdc);
735*4882a593Smuzhiyun if (ret != 0) {
736*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to request UV IRQ %d: %d\n",
737*4882a593Smuzhiyun irq, ret);
738*4882a593Smuzhiyun return ret;
739*4882a593Smuzhiyun }
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun platform_set_drvdata(pdev, dcdc);
742*4882a593Smuzhiyun
743*4882a593Smuzhiyun return 0;
744*4882a593Smuzhiyun }
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun static struct platform_driver wm831x_boostp_driver = {
747*4882a593Smuzhiyun .probe = wm831x_boostp_probe,
748*4882a593Smuzhiyun .driver = {
749*4882a593Smuzhiyun .name = "wm831x-boostp",
750*4882a593Smuzhiyun },
751*4882a593Smuzhiyun };
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun /*
754*4882a593Smuzhiyun * External Power Enable
755*4882a593Smuzhiyun *
756*4882a593Smuzhiyun * These aren't actually DCDCs but look like them in hardware so share
757*4882a593Smuzhiyun * code.
758*4882a593Smuzhiyun */
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun #define WM831X_EPE_BASE 6
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun static const struct regulator_ops wm831x_epe_ops = {
763*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
764*4882a593Smuzhiyun .enable = regulator_enable_regmap,
765*4882a593Smuzhiyun .disable = regulator_disable_regmap,
766*4882a593Smuzhiyun .get_status = wm831x_dcdc_get_status,
767*4882a593Smuzhiyun };
768*4882a593Smuzhiyun
wm831x_epe_probe(struct platform_device * pdev)769*4882a593Smuzhiyun static int wm831x_epe_probe(struct platform_device *pdev)
770*4882a593Smuzhiyun {
771*4882a593Smuzhiyun struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
772*4882a593Smuzhiyun struct wm831x_pdata *pdata = dev_get_platdata(wm831x->dev);
773*4882a593Smuzhiyun struct regulator_config config = { };
774*4882a593Smuzhiyun int id = pdev->id % ARRAY_SIZE(pdata->epe);
775*4882a593Smuzhiyun struct wm831x_dcdc *dcdc;
776*4882a593Smuzhiyun int ret;
777*4882a593Smuzhiyun
778*4882a593Smuzhiyun dev_dbg(&pdev->dev, "Probing EPE%d\n", id + 1);
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun dcdc = devm_kzalloc(&pdev->dev, sizeof(struct wm831x_dcdc), GFP_KERNEL);
781*4882a593Smuzhiyun if (!dcdc)
782*4882a593Smuzhiyun return -ENOMEM;
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun dcdc->wm831x = wm831x;
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun /* For current parts this is correct; probably need to revisit
787*4882a593Smuzhiyun * in future.
788*4882a593Smuzhiyun */
789*4882a593Smuzhiyun snprintf(dcdc->name, sizeof(dcdc->name), "EPE%d", id + 1);
790*4882a593Smuzhiyun dcdc->desc.name = dcdc->name;
791*4882a593Smuzhiyun dcdc->desc.id = id + WM831X_EPE_BASE; /* Offset in DCDC registers */
792*4882a593Smuzhiyun dcdc->desc.ops = &wm831x_epe_ops;
793*4882a593Smuzhiyun dcdc->desc.type = REGULATOR_VOLTAGE;
794*4882a593Smuzhiyun dcdc->desc.owner = THIS_MODULE;
795*4882a593Smuzhiyun dcdc->desc.enable_reg = WM831X_DCDC_ENABLE;
796*4882a593Smuzhiyun dcdc->desc.enable_mask = 1 << dcdc->desc.id;
797*4882a593Smuzhiyun
798*4882a593Smuzhiyun config.dev = pdev->dev.parent;
799*4882a593Smuzhiyun if (pdata)
800*4882a593Smuzhiyun config.init_data = pdata->epe[id];
801*4882a593Smuzhiyun config.driver_data = dcdc;
802*4882a593Smuzhiyun config.regmap = wm831x->regmap;
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun dcdc->regulator = devm_regulator_register(&pdev->dev, &dcdc->desc,
805*4882a593Smuzhiyun &config);
806*4882a593Smuzhiyun if (IS_ERR(dcdc->regulator)) {
807*4882a593Smuzhiyun ret = PTR_ERR(dcdc->regulator);
808*4882a593Smuzhiyun dev_err(wm831x->dev, "Failed to register EPE%d: %d\n",
809*4882a593Smuzhiyun id + 1, ret);
810*4882a593Smuzhiyun goto err;
811*4882a593Smuzhiyun }
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun platform_set_drvdata(pdev, dcdc);
814*4882a593Smuzhiyun
815*4882a593Smuzhiyun return 0;
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun err:
818*4882a593Smuzhiyun return ret;
819*4882a593Smuzhiyun }
820*4882a593Smuzhiyun
821*4882a593Smuzhiyun static struct platform_driver wm831x_epe_driver = {
822*4882a593Smuzhiyun .probe = wm831x_epe_probe,
823*4882a593Smuzhiyun .driver = {
824*4882a593Smuzhiyun .name = "wm831x-epe",
825*4882a593Smuzhiyun },
826*4882a593Smuzhiyun };
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun static struct platform_driver * const drivers[] = {
829*4882a593Smuzhiyun &wm831x_buckv_driver,
830*4882a593Smuzhiyun &wm831x_buckp_driver,
831*4882a593Smuzhiyun &wm831x_boostp_driver,
832*4882a593Smuzhiyun &wm831x_epe_driver,
833*4882a593Smuzhiyun };
834*4882a593Smuzhiyun
wm831x_dcdc_init(void)835*4882a593Smuzhiyun static int __init wm831x_dcdc_init(void)
836*4882a593Smuzhiyun {
837*4882a593Smuzhiyun return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
838*4882a593Smuzhiyun }
839*4882a593Smuzhiyun subsys_initcall(wm831x_dcdc_init);
840*4882a593Smuzhiyun
wm831x_dcdc_exit(void)841*4882a593Smuzhiyun static void __exit wm831x_dcdc_exit(void)
842*4882a593Smuzhiyun {
843*4882a593Smuzhiyun platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
844*4882a593Smuzhiyun }
845*4882a593Smuzhiyun module_exit(wm831x_dcdc_exit);
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun /* Module information */
848*4882a593Smuzhiyun MODULE_AUTHOR("Mark Brown");
849*4882a593Smuzhiyun MODULE_DESCRIPTION("WM831x DC-DC convertor driver");
850*4882a593Smuzhiyun MODULE_LICENSE("GPL");
851*4882a593Smuzhiyun MODULE_ALIAS("platform:wm831x-buckv");
852*4882a593Smuzhiyun MODULE_ALIAS("platform:wm831x-buckp");
853*4882a593Smuzhiyun MODULE_ALIAS("platform:wm831x-boostp");
854*4882a593Smuzhiyun MODULE_ALIAS("platform:wm831x-epe");
855