xref: /OK3568_Linux_fs/kernel/drivers/regulator/wl2868c-regulator.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Author: Shunqing Chen <csq@rock-chips.com>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/err.h>
9*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
10*4882a593Smuzhiyun #include <linux/i2c.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/of.h>
14*4882a593Smuzhiyun #include <linux/of_gpio.h>
15*4882a593Smuzhiyun #include <linux/regmap.h>
16*4882a593Smuzhiyun #include <linux/regulator/driver.h>
17*4882a593Smuzhiyun #include <linux/regulator/machine.h>
18*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define WL2868C_DEVICE_D1		0x00
21*4882a593Smuzhiyun #define WL2868C_DEVICE_D2		0x01
22*4882a593Smuzhiyun #define WL2868C_DISCHARGE_RESISTORS	0x02
23*4882a593Smuzhiyun #define WL2868C_LDO1_VOUT		0x03
24*4882a593Smuzhiyun #define WL2868C_LDO2_VOUT		0x04
25*4882a593Smuzhiyun #define WL2868C_LDO3_VOUT		0x05
26*4882a593Smuzhiyun #define WL2868C_LDO4_VOUT		0x06
27*4882a593Smuzhiyun #define WL2868C_LDO5_VOUT		0x07
28*4882a593Smuzhiyun #define WL2868C_LDO6_VOUT		0x08
29*4882a593Smuzhiyun #define WL2868C_LDO7_VOUT		0x09
30*4882a593Smuzhiyun #define WL2868C_LDO1_LDO2_SEQ		0x0a
31*4882a593Smuzhiyun #define WL2868C_LDO3_LDO4_SEQ		0x0b
32*4882a593Smuzhiyun #define WL2868C_LDO5_LDO6_SEQ		0x0c
33*4882a593Smuzhiyun #define WL2868C_LDO7_SEQ		0x0d
34*4882a593Smuzhiyun #define WL2868C_LDO_EN			0x0e
35*4882a593Smuzhiyun #define WL2868C_SEQ_STATUS		0x0f
36*4882a593Smuzhiyun #define WL2868C_LDO1_STATUS		0x10
37*4882a593Smuzhiyun #define WL2868C_LDO1_OCP_CTL		0x11
38*4882a593Smuzhiyun #define WL2868C_LDO2_STATUS		0x12
39*4882a593Smuzhiyun #define WL2868C_LDO2_OCP_CTL		0x13
40*4882a593Smuzhiyun #define WL2868C_LDO3_STATUS		0x14
41*4882a593Smuzhiyun #define WL2868C_LDO3_OCP_CTL		0x15
42*4882a593Smuzhiyun #define WL2868C_LDO4_STATUS		0x16
43*4882a593Smuzhiyun #define WL2868C_LDO4_OCP_CTL		0x17
44*4882a593Smuzhiyun #define WL2868C_LDO5_STATUS		0x18
45*4882a593Smuzhiyun #define WL2868C_LDO5_OCP_CTL		0x19
46*4882a593Smuzhiyun #define WL2868C_LDO6_STATUS		0x1a
47*4882a593Smuzhiyun #define WL2868C_LDO6_OCP_CTL		0x1b
48*4882a593Smuzhiyun #define WL2868C_LDO7_STATUS		0x1c
49*4882a593Smuzhiyun #define WL2868C_LDO7_OCP_CTL		0x1d
50*4882a593Smuzhiyun #define WL2868C_REPROGRAMMABLE_I2C_ADDR	0x1e
51*4882a593Smuzhiyun #define RESERVED_1			0x1f
52*4882a593Smuzhiyun #define INT_LATCHED_CLR			0x20
53*4882a593Smuzhiyun #define INT_EN_SET			0x21
54*4882a593Smuzhiyun #define INT_LATCHED_STS			0x22
55*4882a593Smuzhiyun #define INT_PENDING_STS			0x23
56*4882a593Smuzhiyun #define UVLO_CTL			0x24
57*4882a593Smuzhiyun #define RESERVED_2			0x25
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun #define WL2868C_VSEL_MASK		0xff
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun enum wl2868c_regulators {
62*4882a593Smuzhiyun 	WL2868C_REGULATOR_LDO1 = 0,
63*4882a593Smuzhiyun 	WL2868C_REGULATOR_LDO2,
64*4882a593Smuzhiyun 	WL2868C_REGULATOR_LDO3,
65*4882a593Smuzhiyun 	WL2868C_REGULATOR_LDO4,
66*4882a593Smuzhiyun 	WL2868C_REGULATOR_LDO5,
67*4882a593Smuzhiyun 	WL2868C_REGULATOR_LDO6,
68*4882a593Smuzhiyun 	WL2868C_REGULATOR_LDO7,
69*4882a593Smuzhiyun 	WL2868C_MAX_REGULATORS,
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun struct wl2868c {
73*4882a593Smuzhiyun 	struct device *dev;
74*4882a593Smuzhiyun 	struct regmap *regmap;
75*4882a593Smuzhiyun 	struct regulator_dev *rdev;
76*4882a593Smuzhiyun 	struct gpio_desc *reset_gpio;
77*4882a593Smuzhiyun 	int min_dropout_uv;
78*4882a593Smuzhiyun 	int ldo_vout[7];
79*4882a593Smuzhiyun 	int ldo_en;
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun static const struct regulator_ops wl2868c_reg_ops = {
83*4882a593Smuzhiyun 	.list_voltage		= regulator_list_voltage_linear,
84*4882a593Smuzhiyun 	.map_voltage		= regulator_map_voltage_linear,
85*4882a593Smuzhiyun 	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
86*4882a593Smuzhiyun 	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
87*4882a593Smuzhiyun 	.enable			= regulator_enable_regmap,
88*4882a593Smuzhiyun 	.disable		= regulator_disable_regmap,
89*4882a593Smuzhiyun 	.is_enabled		= regulator_is_enabled_regmap,
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun #define WL2868C_DESC(_id, _match, _supply, _min, _max, _step, _vreg,	\
93*4882a593Smuzhiyun 	_vmask, _ereg, _emask, _enval, _disval)		\
94*4882a593Smuzhiyun 	{								\
95*4882a593Smuzhiyun 		.name		= (_match),				\
96*4882a593Smuzhiyun 		.supply_name	= (_supply),				\
97*4882a593Smuzhiyun 		.of_match	= of_match_ptr(_match),			\
98*4882a593Smuzhiyun 		.regulators_node = of_match_ptr("regulators"),		\
99*4882a593Smuzhiyun 		.type		= REGULATOR_VOLTAGE,			\
100*4882a593Smuzhiyun 		.id		= (_id),				\
101*4882a593Smuzhiyun 		.n_voltages	= (((_max) - (_min)) / (_step) + 1),	\
102*4882a593Smuzhiyun 		.owner		= THIS_MODULE,				\
103*4882a593Smuzhiyun 		.min_uV		= (_min) * 1000,			\
104*4882a593Smuzhiyun 		.uV_step	= (_step) * 1000,			\
105*4882a593Smuzhiyun 		.vsel_reg	= (_vreg),				\
106*4882a593Smuzhiyun 		.vsel_mask	= (_vmask),				\
107*4882a593Smuzhiyun 		.enable_reg	= (_ereg),				\
108*4882a593Smuzhiyun 		.enable_mask	= (_emask),				\
109*4882a593Smuzhiyun 		.enable_val     = (_enval),				\
110*4882a593Smuzhiyun 		.disable_val     = (_disval),				\
111*4882a593Smuzhiyun 		.ops		= &wl2868c_reg_ops,			\
112*4882a593Smuzhiyun 	}
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun static const struct regulator_desc wl2868c_reg[] = {
115*4882a593Smuzhiyun 	WL2868C_DESC(WL2868C_REGULATOR_LDO1, "WL_LDO1", "ldo1", 496, 2536, 8,
116*4882a593Smuzhiyun 		     WL2868C_LDO1_VOUT, WL2868C_VSEL_MASK, WL2868C_LDO_EN, BIT(0), BIT(0), 0),
117*4882a593Smuzhiyun 	WL2868C_DESC(WL2868C_REGULATOR_LDO2, "WL_LDO2", "ldo2", 496, 2536, 8,
118*4882a593Smuzhiyun 		     WL2868C_LDO2_VOUT, WL2868C_VSEL_MASK, WL2868C_LDO_EN, BIT(1), BIT(1), 0),
119*4882a593Smuzhiyun 	WL2868C_DESC(WL2868C_REGULATOR_LDO3, "WL_LDO3", "ldo3", 1504, 3544, 8,
120*4882a593Smuzhiyun 		     WL2868C_LDO3_VOUT, WL2868C_VSEL_MASK, WL2868C_LDO_EN, BIT(2), BIT(2), 0),
121*4882a593Smuzhiyun 	WL2868C_DESC(WL2868C_REGULATOR_LDO4, "WL_LDO4", "ldo4", 1504, 3544, 8,
122*4882a593Smuzhiyun 		     WL2868C_LDO4_VOUT, WL2868C_VSEL_MASK, WL2868C_LDO_EN, BIT(3), BIT(3), 0),
123*4882a593Smuzhiyun 	WL2868C_DESC(WL2868C_REGULATOR_LDO5, "WL_LDO5", "ldo5", 1504, 3544, 8,
124*4882a593Smuzhiyun 		     WL2868C_LDO5_VOUT, WL2868C_VSEL_MASK, WL2868C_LDO_EN, BIT(4), BIT(4), 0),
125*4882a593Smuzhiyun 	WL2868C_DESC(WL2868C_REGULATOR_LDO6, "WL_LDO6", "ldo6", 1504, 3544, 8,
126*4882a593Smuzhiyun 		     WL2868C_LDO6_VOUT, WL2868C_VSEL_MASK, WL2868C_LDO_EN, BIT(5), BIT(5), 0),
127*4882a593Smuzhiyun 	WL2868C_DESC(WL2868C_REGULATOR_LDO7, "WL_LDO7", "ldo7", 1504, 3544, 8,
128*4882a593Smuzhiyun 		     WL2868C_LDO7_VOUT, WL2868C_VSEL_MASK, WL2868C_LDO_EN, BIT(6), BIT(6), 0),
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun static const struct regmap_range wl2868c_writeable_ranges[] = {
132*4882a593Smuzhiyun 	regmap_reg_range(WL2868C_DISCHARGE_RESISTORS, WL2868C_SEQ_STATUS),
133*4882a593Smuzhiyun 	regmap_reg_range(WL2868C_LDO1_OCP_CTL, WL2868C_LDO1_OCP_CTL),
134*4882a593Smuzhiyun 	regmap_reg_range(WL2868C_LDO2_OCP_CTL, WL2868C_LDO2_OCP_CTL),
135*4882a593Smuzhiyun 	regmap_reg_range(WL2868C_LDO3_OCP_CTL, WL2868C_LDO3_OCP_CTL),
136*4882a593Smuzhiyun 	regmap_reg_range(WL2868C_LDO4_OCP_CTL, WL2868C_LDO4_OCP_CTL),
137*4882a593Smuzhiyun 	regmap_reg_range(WL2868C_LDO5_OCP_CTL, WL2868C_LDO5_OCP_CTL),
138*4882a593Smuzhiyun 	regmap_reg_range(WL2868C_LDO6_OCP_CTL, WL2868C_LDO6_OCP_CTL),
139*4882a593Smuzhiyun 	regmap_reg_range(WL2868C_LDO7_OCP_CTL, WL2868C_REPROGRAMMABLE_I2C_ADDR),
140*4882a593Smuzhiyun 	regmap_reg_range(INT_LATCHED_CLR, INT_LATCHED_CLR),
141*4882a593Smuzhiyun 	regmap_reg_range(INT_EN_SET, INT_EN_SET),
142*4882a593Smuzhiyun 	regmap_reg_range(UVLO_CTL, UVLO_CTL),
143*4882a593Smuzhiyun };
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun static const struct regmap_range wl2868c_readable_ranges[] = {
146*4882a593Smuzhiyun 	regmap_reg_range(WL2868C_DEVICE_D1, RESERVED_2),
147*4882a593Smuzhiyun };
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun static const struct regmap_range wl2868c_volatile_ranges[] = {
150*4882a593Smuzhiyun 	regmap_reg_range(WL2868C_DISCHARGE_RESISTORS, WL2868C_SEQ_STATUS),
151*4882a593Smuzhiyun 	regmap_reg_range(WL2868C_LDO1_OCP_CTL, WL2868C_LDO1_OCP_CTL),
152*4882a593Smuzhiyun 	regmap_reg_range(WL2868C_LDO2_OCP_CTL, WL2868C_LDO2_OCP_CTL),
153*4882a593Smuzhiyun 	regmap_reg_range(WL2868C_LDO3_OCP_CTL, WL2868C_LDO3_OCP_CTL),
154*4882a593Smuzhiyun 	regmap_reg_range(WL2868C_LDO4_OCP_CTL, WL2868C_LDO4_OCP_CTL),
155*4882a593Smuzhiyun 	regmap_reg_range(WL2868C_LDO5_OCP_CTL, WL2868C_LDO5_OCP_CTL),
156*4882a593Smuzhiyun 	regmap_reg_range(WL2868C_LDO6_OCP_CTL, WL2868C_LDO6_OCP_CTL),
157*4882a593Smuzhiyun 	regmap_reg_range(WL2868C_LDO7_OCP_CTL, WL2868C_REPROGRAMMABLE_I2C_ADDR),
158*4882a593Smuzhiyun 	regmap_reg_range(INT_LATCHED_CLR, INT_LATCHED_CLR),
159*4882a593Smuzhiyun 	regmap_reg_range(INT_EN_SET, INT_EN_SET),
160*4882a593Smuzhiyun 	regmap_reg_range(UVLO_CTL, UVLO_CTL),
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun static const struct regmap_access_table wl2868c_writeable_table = {
164*4882a593Smuzhiyun 	.yes_ranges   = wl2868c_writeable_ranges,
165*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(wl2868c_writeable_ranges),
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun static const struct regmap_access_table wl2868c_readable_table = {
169*4882a593Smuzhiyun 	.yes_ranges   = wl2868c_readable_ranges,
170*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(wl2868c_readable_ranges),
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun static const struct regmap_access_table wl2868c_volatile_table = {
174*4882a593Smuzhiyun 	.yes_ranges   = wl2868c_volatile_ranges,
175*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(wl2868c_volatile_ranges),
176*4882a593Smuzhiyun };
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun static const struct regmap_config wl2868c_regmap_config = {
179*4882a593Smuzhiyun 	.reg_bits = 8,
180*4882a593Smuzhiyun 	.val_bits = 8,
181*4882a593Smuzhiyun 	.max_register = RESERVED_2,
182*4882a593Smuzhiyun 	.wr_table = &wl2868c_writeable_table,
183*4882a593Smuzhiyun 	.rd_table = &wl2868c_readable_table,
184*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
185*4882a593Smuzhiyun 	.volatile_table = &wl2868c_volatile_table,
186*4882a593Smuzhiyun };
187*4882a593Smuzhiyun 
wl2868c_reset(struct wl2868c * wl2868c)188*4882a593Smuzhiyun static void wl2868c_reset(struct wl2868c *wl2868c)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun 	gpiod_set_value_cansleep(wl2868c->reset_gpio, 0);
191*4882a593Smuzhiyun 	usleep_range(10000, 11000);
192*4882a593Smuzhiyun 	gpiod_set_value_cansleep(wl2868c->reset_gpio, 1);
193*4882a593Smuzhiyun 	usleep_range(10000, 11000);
194*4882a593Smuzhiyun 	gpiod_set_value_cansleep(wl2868c->reset_gpio, 0);
195*4882a593Smuzhiyun 	usleep_range(10000, 11000);
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun 
wl2868c_i2c_probe(struct i2c_client * client,const struct i2c_device_id * id)198*4882a593Smuzhiyun static int wl2868c_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun 	struct device *dev = &client->dev;
201*4882a593Smuzhiyun 	struct regulator_config config = {};
202*4882a593Smuzhiyun 	struct regulator_dev *rdev;
203*4882a593Smuzhiyun 	const struct regulator_desc *regulators;
204*4882a593Smuzhiyun 	struct wl2868c *wl2868c;
205*4882a593Smuzhiyun 	int ret, i;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	wl2868c = devm_kzalloc(dev, sizeof(struct wl2868c), GFP_KERNEL);
208*4882a593Smuzhiyun 	if (!wl2868c)
209*4882a593Smuzhiyun 		return -ENOMEM;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	wl2868c->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
212*4882a593Smuzhiyun 	if (IS_ERR(wl2868c->reset_gpio)) {
213*4882a593Smuzhiyun 		ret = PTR_ERR(wl2868c->reset_gpio);
214*4882a593Smuzhiyun 		dev_err(dev, "failed to request reset GPIO: %d\n", ret);
215*4882a593Smuzhiyun 		return ret;
216*4882a593Smuzhiyun 	}
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	wl2868c_reset(wl2868c);
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	i2c_set_clientdata(client, wl2868c);
221*4882a593Smuzhiyun 	wl2868c->dev = dev;
222*4882a593Smuzhiyun 	wl2868c->regmap = devm_regmap_init_i2c(client, &wl2868c_regmap_config);
223*4882a593Smuzhiyun 	if (IS_ERR(wl2868c->regmap)) {
224*4882a593Smuzhiyun 		ret = PTR_ERR(wl2868c->regmap);
225*4882a593Smuzhiyun 		dev_err(dev, "Failed to allocate register map: %d\n", ret);
226*4882a593Smuzhiyun 		return ret;
227*4882a593Smuzhiyun 	}
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	config.dev = &client->dev;
230*4882a593Smuzhiyun 	config.regmap = wl2868c->regmap;
231*4882a593Smuzhiyun 	regulators = wl2868c_reg;
232*4882a593Smuzhiyun 	/* Instantiate the regulators */
233*4882a593Smuzhiyun 	for (i = 0; i < WL2868C_MAX_REGULATORS; i++) {
234*4882a593Smuzhiyun 		rdev = devm_regulator_register(&client->dev,
235*4882a593Smuzhiyun 					       &regulators[i], &config);
236*4882a593Smuzhiyun 		if (IS_ERR(rdev)) {
237*4882a593Smuzhiyun 			dev_err(&client->dev,
238*4882a593Smuzhiyun 				"failed to register %d regulator\n", i);
239*4882a593Smuzhiyun 			return PTR_ERR(rdev);
240*4882a593Smuzhiyun 		}
241*4882a593Smuzhiyun 	}
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	return 0;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun 
wl2868c_regulator_shutdown(struct i2c_client * client)246*4882a593Smuzhiyun static void wl2868c_regulator_shutdown(struct i2c_client *client)
247*4882a593Smuzhiyun {
248*4882a593Smuzhiyun 	struct wl2868c *wl2868c = i2c_get_clientdata(client);
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	if (system_state == SYSTEM_POWER_OFF)
251*4882a593Smuzhiyun 		regmap_write(wl2868c->regmap, WL2868C_LDO_EN, 0x80);
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun 
wl2868c_suspend(struct device * dev)254*4882a593Smuzhiyun static int __maybe_unused wl2868c_suspend(struct device *dev)
255*4882a593Smuzhiyun {
256*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
257*4882a593Smuzhiyun 	struct wl2868c *wl2868c = i2c_get_clientdata(client);
258*4882a593Smuzhiyun 	int i;
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun 	regmap_read(wl2868c->regmap, WL2868C_LDO_EN, &wl2868c->ldo_en);
261*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(wl2868c->ldo_vout); i++)
262*4882a593Smuzhiyun 		regmap_read(wl2868c->regmap, WL2868C_LDO1_VOUT + i,
263*4882a593Smuzhiyun 			    &wl2868c->ldo_vout[i]);
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	return 0;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun 
wl2868c_resume(struct device * dev)268*4882a593Smuzhiyun static int __maybe_unused wl2868c_resume(struct device *dev)
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
271*4882a593Smuzhiyun 	struct wl2868c *wl2868c = i2c_get_clientdata(client);
272*4882a593Smuzhiyun 	int i;
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	wl2868c_reset(wl2868c);
275*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(wl2868c->ldo_vout); i++)
276*4882a593Smuzhiyun 		regmap_write(wl2868c->regmap, WL2868C_LDO1_VOUT + i,
277*4882a593Smuzhiyun 			     wl2868c->ldo_vout[i]);
278*4882a593Smuzhiyun 	regmap_write(wl2868c->regmap, WL2868C_LDO_EN, wl2868c->ldo_en);
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	return 0;
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(wl2868c_pm_ops, wl2868c_suspend, wl2868c_resume);
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun static const struct i2c_device_id wl2868c_i2c_id[] = {
286*4882a593Smuzhiyun 	{ "wl2868c", 0 },
287*4882a593Smuzhiyun 	{ }
288*4882a593Smuzhiyun };
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, wl2868c_i2c_id);
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun static const struct of_device_id wl2868c_of_match[] = {
293*4882a593Smuzhiyun 	{ .compatible = "willsemi,wl2868c" },
294*4882a593Smuzhiyun 	{}
295*4882a593Smuzhiyun };
296*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, wl2868c_of_match);
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun static struct i2c_driver wl2868c_i2c_driver = {
299*4882a593Smuzhiyun 	.driver = {
300*4882a593Smuzhiyun 		.name = "wl2868c",
301*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(wl2868c_of_match),
302*4882a593Smuzhiyun 		.pm = &wl2868c_pm_ops,
303*4882a593Smuzhiyun 	},
304*4882a593Smuzhiyun 	.id_table = wl2868c_i2c_id,
305*4882a593Smuzhiyun 	.probe	= wl2868c_i2c_probe,
306*4882a593Smuzhiyun 	.shutdown = wl2868c_regulator_shutdown,
307*4882a593Smuzhiyun };
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun module_i2c_driver(wl2868c_i2c_driver);
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun MODULE_DESCRIPTION("WL2868C regulator driver");
312*4882a593Smuzhiyun MODULE_AUTHOR("Shunqing Chen <csq@rock-chips.com>");
313*4882a593Smuzhiyun MODULE_LICENSE("GPL");
314