1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Split TWL6030 logic from twl-regulator.c:
4*4882a593Smuzhiyun * Copyright (C) 2008 David Brownell
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2016 Nicolae Rosia <nicolae.rosia@gmail.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/string.h>
11*4882a593Smuzhiyun #include <linux/slab.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/err.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/of.h>
16*4882a593Smuzhiyun #include <linux/of_device.h>
17*4882a593Smuzhiyun #include <linux/regulator/driver.h>
18*4882a593Smuzhiyun #include <linux/regulator/machine.h>
19*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
20*4882a593Smuzhiyun #include <linux/mfd/twl.h>
21*4882a593Smuzhiyun #include <linux/delay.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun struct twlreg_info {
24*4882a593Smuzhiyun /* start of regulator's PM_RECEIVER control register bank */
25*4882a593Smuzhiyun u8 base;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* twl resource ID, for resource control state machine */
28*4882a593Smuzhiyun u8 id;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun u8 flags;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* used by regulator core */
33*4882a593Smuzhiyun struct regulator_desc desc;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* chip specific features */
36*4882a593Smuzhiyun unsigned long features;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* data passed from board for external get/set voltage */
39*4882a593Smuzhiyun void *data;
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* LDO control registers ... offset is from the base of its register bank.
44*4882a593Smuzhiyun * The first three registers of all power resource banks help hardware to
45*4882a593Smuzhiyun * manage the various resource groups.
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun /* Common offset in TWL4030/6030 */
48*4882a593Smuzhiyun #define VREG_GRP 0
49*4882a593Smuzhiyun /* TWL6030 register offsets */
50*4882a593Smuzhiyun #define VREG_TRANS 1
51*4882a593Smuzhiyun #define VREG_STATE 2
52*4882a593Smuzhiyun #define VREG_VOLTAGE 3
53*4882a593Smuzhiyun #define VREG_VOLTAGE_SMPS 4
54*4882a593Smuzhiyun /* TWL6030 Misc register offsets */
55*4882a593Smuzhiyun #define VREG_BC_ALL 1
56*4882a593Smuzhiyun #define VREG_BC_REF 2
57*4882a593Smuzhiyun #define VREG_BC_PROC 3
58*4882a593Smuzhiyun #define VREG_BC_CLK_RST 4
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* TWL6030 LDO register values for VREG_VOLTAGE */
61*4882a593Smuzhiyun #define TWL6030_VREG_VOLTAGE_WR_S BIT(7)
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* TWL6030 LDO register values for CFG_STATE */
64*4882a593Smuzhiyun #define TWL6030_CFG_STATE_OFF 0x00
65*4882a593Smuzhiyun #define TWL6030_CFG_STATE_ON 0x01
66*4882a593Smuzhiyun #define TWL6030_CFG_STATE_OFF2 0x02
67*4882a593Smuzhiyun #define TWL6030_CFG_STATE_SLEEP 0x03
68*4882a593Smuzhiyun #define TWL6030_CFG_STATE_GRP_SHIFT 5
69*4882a593Smuzhiyun #define TWL6030_CFG_STATE_APP_SHIFT 2
70*4882a593Smuzhiyun #define TWL6030_CFG_STATE_MASK 0x03
71*4882a593Smuzhiyun #define TWL6030_CFG_STATE_APP_MASK (0x03 << TWL6030_CFG_STATE_APP_SHIFT)
72*4882a593Smuzhiyun #define TWL6030_CFG_STATE_APP(v) (((v) & TWL6030_CFG_STATE_APP_MASK) >>\
73*4882a593Smuzhiyun TWL6030_CFG_STATE_APP_SHIFT)
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Flags for SMPS Voltage reading and LDO reading*/
76*4882a593Smuzhiyun #define SMPS_OFFSET_EN BIT(0)
77*4882a593Smuzhiyun #define SMPS_EXTENDED_EN BIT(1)
78*4882a593Smuzhiyun #define TWL_6030_WARM_RESET BIT(3)
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /* twl6032 SMPS EPROM values */
81*4882a593Smuzhiyun #define TWL6030_SMPS_OFFSET 0xB0
82*4882a593Smuzhiyun #define TWL6030_SMPS_MULT 0xB3
83*4882a593Smuzhiyun #define SMPS_MULTOFFSET_SMPS4 BIT(0)
84*4882a593Smuzhiyun #define SMPS_MULTOFFSET_VIO BIT(1)
85*4882a593Smuzhiyun #define SMPS_MULTOFFSET_SMPS3 BIT(6)
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun static inline int
twlreg_read(struct twlreg_info * info,unsigned slave_subgp,unsigned offset)88*4882a593Smuzhiyun twlreg_read(struct twlreg_info *info, unsigned slave_subgp, unsigned offset)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun u8 value;
91*4882a593Smuzhiyun int status;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun status = twl_i2c_read_u8(slave_subgp,
94*4882a593Smuzhiyun &value, info->base + offset);
95*4882a593Smuzhiyun return (status < 0) ? status : value;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun static inline int
twlreg_write(struct twlreg_info * info,unsigned slave_subgp,unsigned offset,u8 value)99*4882a593Smuzhiyun twlreg_write(struct twlreg_info *info, unsigned slave_subgp, unsigned offset,
100*4882a593Smuzhiyun u8 value)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun return twl_i2c_write_u8(slave_subgp,
103*4882a593Smuzhiyun value, info->base + offset);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /* generic power resource operations, which work on all regulators */
twlreg_grp(struct regulator_dev * rdev)107*4882a593Smuzhiyun static int twlreg_grp(struct regulator_dev *rdev)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun return twlreg_read(rdev_get_drvdata(rdev), TWL_MODULE_PM_RECEIVER,
110*4882a593Smuzhiyun VREG_GRP);
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /*
114*4882a593Smuzhiyun * Enable/disable regulators by joining/leaving the P1 (processor) group.
115*4882a593Smuzhiyun * We assume nobody else is updating the DEV_GRP registers.
116*4882a593Smuzhiyun */
117*4882a593Smuzhiyun /* definition for 6030 family */
118*4882a593Smuzhiyun #define P3_GRP_6030 BIT(2) /* secondary processor, modem, etc */
119*4882a593Smuzhiyun #define P2_GRP_6030 BIT(1) /* "peripherals" */
120*4882a593Smuzhiyun #define P1_GRP_6030 BIT(0) /* CPU/Linux */
121*4882a593Smuzhiyun
twl6030reg_is_enabled(struct regulator_dev * rdev)122*4882a593Smuzhiyun static int twl6030reg_is_enabled(struct regulator_dev *rdev)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun struct twlreg_info *info = rdev_get_drvdata(rdev);
125*4882a593Smuzhiyun int grp = 0, val;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun if (!(twl_class_is_6030() && (info->features & TWL6032_SUBCLASS))) {
128*4882a593Smuzhiyun grp = twlreg_grp(rdev);
129*4882a593Smuzhiyun if (grp < 0)
130*4882a593Smuzhiyun return grp;
131*4882a593Smuzhiyun grp &= P1_GRP_6030;
132*4882a593Smuzhiyun val = twlreg_read(info, TWL_MODULE_PM_RECEIVER, VREG_STATE);
133*4882a593Smuzhiyun val = TWL6030_CFG_STATE_APP(val);
134*4882a593Smuzhiyun } else {
135*4882a593Smuzhiyun val = twlreg_read(info, TWL_MODULE_PM_RECEIVER, VREG_STATE);
136*4882a593Smuzhiyun val &= TWL6030_CFG_STATE_MASK;
137*4882a593Smuzhiyun grp = 1;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun return grp && (val == TWL6030_CFG_STATE_ON);
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun #define PB_I2C_BUSY BIT(0)
144*4882a593Smuzhiyun #define PB_I2C_BWEN BIT(1)
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun
twl6030reg_enable(struct regulator_dev * rdev)147*4882a593Smuzhiyun static int twl6030reg_enable(struct regulator_dev *rdev)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun struct twlreg_info *info = rdev_get_drvdata(rdev);
150*4882a593Smuzhiyun int grp = 0;
151*4882a593Smuzhiyun int ret;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun if (!(twl_class_is_6030() && (info->features & TWL6032_SUBCLASS)))
154*4882a593Smuzhiyun grp = twlreg_grp(rdev);
155*4882a593Smuzhiyun if (grp < 0)
156*4882a593Smuzhiyun return grp;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun ret = twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_STATE,
159*4882a593Smuzhiyun grp << TWL6030_CFG_STATE_GRP_SHIFT |
160*4882a593Smuzhiyun TWL6030_CFG_STATE_ON);
161*4882a593Smuzhiyun return ret;
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun
twl6030reg_disable(struct regulator_dev * rdev)164*4882a593Smuzhiyun static int twl6030reg_disable(struct regulator_dev *rdev)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun struct twlreg_info *info = rdev_get_drvdata(rdev);
167*4882a593Smuzhiyun int grp = 0;
168*4882a593Smuzhiyun int ret;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun if (!(twl_class_is_6030() && (info->features & TWL6032_SUBCLASS)))
171*4882a593Smuzhiyun grp = P1_GRP_6030 | P2_GRP_6030 | P3_GRP_6030;
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun /* For 6030, set the off state for all grps enabled */
174*4882a593Smuzhiyun ret = twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_STATE,
175*4882a593Smuzhiyun (grp) << TWL6030_CFG_STATE_GRP_SHIFT |
176*4882a593Smuzhiyun TWL6030_CFG_STATE_OFF);
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun return ret;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
twl6030reg_get_status(struct regulator_dev * rdev)181*4882a593Smuzhiyun static int twl6030reg_get_status(struct regulator_dev *rdev)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun struct twlreg_info *info = rdev_get_drvdata(rdev);
184*4882a593Smuzhiyun int val;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun val = twlreg_grp(rdev);
187*4882a593Smuzhiyun if (val < 0)
188*4882a593Smuzhiyun return val;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun val = twlreg_read(info, TWL_MODULE_PM_RECEIVER, VREG_STATE);
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun if (info->features & TWL6032_SUBCLASS)
193*4882a593Smuzhiyun val &= TWL6030_CFG_STATE_MASK;
194*4882a593Smuzhiyun else
195*4882a593Smuzhiyun val = TWL6030_CFG_STATE_APP(val);
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun switch (val) {
198*4882a593Smuzhiyun case TWL6030_CFG_STATE_ON:
199*4882a593Smuzhiyun return REGULATOR_STATUS_NORMAL;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun case TWL6030_CFG_STATE_SLEEP:
202*4882a593Smuzhiyun return REGULATOR_STATUS_STANDBY;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun case TWL6030_CFG_STATE_OFF:
205*4882a593Smuzhiyun case TWL6030_CFG_STATE_OFF2:
206*4882a593Smuzhiyun default:
207*4882a593Smuzhiyun break;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun return REGULATOR_STATUS_OFF;
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun
twl6030reg_set_mode(struct regulator_dev * rdev,unsigned mode)213*4882a593Smuzhiyun static int twl6030reg_set_mode(struct regulator_dev *rdev, unsigned mode)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun struct twlreg_info *info = rdev_get_drvdata(rdev);
216*4882a593Smuzhiyun int grp = 0;
217*4882a593Smuzhiyun int val;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun if (!(twl_class_is_6030() && (info->features & TWL6032_SUBCLASS)))
220*4882a593Smuzhiyun grp = twlreg_grp(rdev);
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun if (grp < 0)
223*4882a593Smuzhiyun return grp;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun /* Compose the state register settings */
226*4882a593Smuzhiyun val = grp << TWL6030_CFG_STATE_GRP_SHIFT;
227*4882a593Smuzhiyun /* We can only set the mode through state machine commands... */
228*4882a593Smuzhiyun switch (mode) {
229*4882a593Smuzhiyun case REGULATOR_MODE_NORMAL:
230*4882a593Smuzhiyun val |= TWL6030_CFG_STATE_ON;
231*4882a593Smuzhiyun break;
232*4882a593Smuzhiyun case REGULATOR_MODE_STANDBY:
233*4882a593Smuzhiyun val |= TWL6030_CFG_STATE_SLEEP;
234*4882a593Smuzhiyun break;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun default:
237*4882a593Smuzhiyun return -EINVAL;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun return twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_STATE, val);
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun
twl6030coresmps_set_voltage(struct regulator_dev * rdev,int min_uV,int max_uV,unsigned * selector)243*4882a593Smuzhiyun static int twl6030coresmps_set_voltage(struct regulator_dev *rdev, int min_uV,
244*4882a593Smuzhiyun int max_uV, unsigned *selector)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun return -ENODEV;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
twl6030coresmps_get_voltage(struct regulator_dev * rdev)249*4882a593Smuzhiyun static int twl6030coresmps_get_voltage(struct regulator_dev *rdev)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun return -ENODEV;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun static const struct regulator_ops twl6030coresmps_ops = {
255*4882a593Smuzhiyun .set_voltage = twl6030coresmps_set_voltage,
256*4882a593Smuzhiyun .get_voltage = twl6030coresmps_get_voltage,
257*4882a593Smuzhiyun };
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun static int
twl6030ldo_set_voltage_sel(struct regulator_dev * rdev,unsigned selector)260*4882a593Smuzhiyun twl6030ldo_set_voltage_sel(struct regulator_dev *rdev, unsigned selector)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun struct twlreg_info *info = rdev_get_drvdata(rdev);
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun if (info->flags & TWL_6030_WARM_RESET)
265*4882a593Smuzhiyun selector |= TWL6030_VREG_VOLTAGE_WR_S;
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun return twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_VOLTAGE,
268*4882a593Smuzhiyun selector);
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
twl6030ldo_get_voltage_sel(struct regulator_dev * rdev)271*4882a593Smuzhiyun static int twl6030ldo_get_voltage_sel(struct regulator_dev *rdev)
272*4882a593Smuzhiyun {
273*4882a593Smuzhiyun struct twlreg_info *info = rdev_get_drvdata(rdev);
274*4882a593Smuzhiyun int vsel = twlreg_read(info, TWL_MODULE_PM_RECEIVER, VREG_VOLTAGE);
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun if (info->flags & TWL_6030_WARM_RESET)
277*4882a593Smuzhiyun vsel &= ~TWL6030_VREG_VOLTAGE_WR_S;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun return vsel;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun static const struct regulator_ops twl6030ldo_ops = {
283*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun .set_voltage_sel = twl6030ldo_set_voltage_sel,
286*4882a593Smuzhiyun .get_voltage_sel = twl6030ldo_get_voltage_sel,
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun .enable = twl6030reg_enable,
289*4882a593Smuzhiyun .disable = twl6030reg_disable,
290*4882a593Smuzhiyun .is_enabled = twl6030reg_is_enabled,
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun .set_mode = twl6030reg_set_mode,
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun .get_status = twl6030reg_get_status,
295*4882a593Smuzhiyun };
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun static const struct regulator_ops twl6030fixed_ops = {
298*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun .enable = twl6030reg_enable,
301*4882a593Smuzhiyun .disable = twl6030reg_disable,
302*4882a593Smuzhiyun .is_enabled = twl6030reg_is_enabled,
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun .set_mode = twl6030reg_set_mode,
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun .get_status = twl6030reg_get_status,
307*4882a593Smuzhiyun };
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun /*
310*4882a593Smuzhiyun * SMPS status and control
311*4882a593Smuzhiyun */
312*4882a593Smuzhiyun
twl6030smps_list_voltage(struct regulator_dev * rdev,unsigned index)313*4882a593Smuzhiyun static int twl6030smps_list_voltage(struct regulator_dev *rdev, unsigned index)
314*4882a593Smuzhiyun {
315*4882a593Smuzhiyun struct twlreg_info *info = rdev_get_drvdata(rdev);
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun int voltage = 0;
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun switch (info->flags) {
320*4882a593Smuzhiyun case SMPS_OFFSET_EN:
321*4882a593Smuzhiyun voltage = 100000;
322*4882a593Smuzhiyun fallthrough;
323*4882a593Smuzhiyun case 0:
324*4882a593Smuzhiyun switch (index) {
325*4882a593Smuzhiyun case 0:
326*4882a593Smuzhiyun voltage = 0;
327*4882a593Smuzhiyun break;
328*4882a593Smuzhiyun case 58:
329*4882a593Smuzhiyun voltage = 1350 * 1000;
330*4882a593Smuzhiyun break;
331*4882a593Smuzhiyun case 59:
332*4882a593Smuzhiyun voltage = 1500 * 1000;
333*4882a593Smuzhiyun break;
334*4882a593Smuzhiyun case 60:
335*4882a593Smuzhiyun voltage = 1800 * 1000;
336*4882a593Smuzhiyun break;
337*4882a593Smuzhiyun case 61:
338*4882a593Smuzhiyun voltage = 1900 * 1000;
339*4882a593Smuzhiyun break;
340*4882a593Smuzhiyun case 62:
341*4882a593Smuzhiyun voltage = 2100 * 1000;
342*4882a593Smuzhiyun break;
343*4882a593Smuzhiyun default:
344*4882a593Smuzhiyun voltage += (600000 + (12500 * (index - 1)));
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun break;
347*4882a593Smuzhiyun case SMPS_EXTENDED_EN:
348*4882a593Smuzhiyun switch (index) {
349*4882a593Smuzhiyun case 0:
350*4882a593Smuzhiyun voltage = 0;
351*4882a593Smuzhiyun break;
352*4882a593Smuzhiyun case 58:
353*4882a593Smuzhiyun voltage = 2084 * 1000;
354*4882a593Smuzhiyun break;
355*4882a593Smuzhiyun case 59:
356*4882a593Smuzhiyun voltage = 2315 * 1000;
357*4882a593Smuzhiyun break;
358*4882a593Smuzhiyun case 60:
359*4882a593Smuzhiyun voltage = 2778 * 1000;
360*4882a593Smuzhiyun break;
361*4882a593Smuzhiyun case 61:
362*4882a593Smuzhiyun voltage = 2932 * 1000;
363*4882a593Smuzhiyun break;
364*4882a593Smuzhiyun case 62:
365*4882a593Smuzhiyun voltage = 3241 * 1000;
366*4882a593Smuzhiyun break;
367*4882a593Smuzhiyun default:
368*4882a593Smuzhiyun voltage = (1852000 + (38600 * (index - 1)));
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun break;
371*4882a593Smuzhiyun case SMPS_OFFSET_EN | SMPS_EXTENDED_EN:
372*4882a593Smuzhiyun switch (index) {
373*4882a593Smuzhiyun case 0:
374*4882a593Smuzhiyun voltage = 0;
375*4882a593Smuzhiyun break;
376*4882a593Smuzhiyun case 58:
377*4882a593Smuzhiyun voltage = 4167 * 1000;
378*4882a593Smuzhiyun break;
379*4882a593Smuzhiyun case 59:
380*4882a593Smuzhiyun voltage = 2315 * 1000;
381*4882a593Smuzhiyun break;
382*4882a593Smuzhiyun case 60:
383*4882a593Smuzhiyun voltage = 2778 * 1000;
384*4882a593Smuzhiyun break;
385*4882a593Smuzhiyun case 61:
386*4882a593Smuzhiyun voltage = 2932 * 1000;
387*4882a593Smuzhiyun break;
388*4882a593Smuzhiyun case 62:
389*4882a593Smuzhiyun voltage = 3241 * 1000;
390*4882a593Smuzhiyun break;
391*4882a593Smuzhiyun default:
392*4882a593Smuzhiyun voltage = (2161000 + (38600 * (index - 1)));
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun break;
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun return voltage;
398*4882a593Smuzhiyun }
399*4882a593Smuzhiyun
twl6030smps_map_voltage(struct regulator_dev * rdev,int min_uV,int max_uV)400*4882a593Smuzhiyun static int twl6030smps_map_voltage(struct regulator_dev *rdev, int min_uV,
401*4882a593Smuzhiyun int max_uV)
402*4882a593Smuzhiyun {
403*4882a593Smuzhiyun struct twlreg_info *info = rdev_get_drvdata(rdev);
404*4882a593Smuzhiyun int vsel = 0;
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun switch (info->flags) {
407*4882a593Smuzhiyun case 0:
408*4882a593Smuzhiyun if (min_uV == 0)
409*4882a593Smuzhiyun vsel = 0;
410*4882a593Smuzhiyun else if ((min_uV >= 600000) && (min_uV <= 1300000)) {
411*4882a593Smuzhiyun vsel = DIV_ROUND_UP(min_uV - 600000, 12500);
412*4882a593Smuzhiyun vsel++;
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun /* Values 1..57 for vsel are linear and can be calculated
415*4882a593Smuzhiyun * values 58..62 are non linear.
416*4882a593Smuzhiyun */
417*4882a593Smuzhiyun else if ((min_uV > 1900000) && (min_uV <= 2100000))
418*4882a593Smuzhiyun vsel = 62;
419*4882a593Smuzhiyun else if ((min_uV > 1800000) && (min_uV <= 1900000))
420*4882a593Smuzhiyun vsel = 61;
421*4882a593Smuzhiyun else if ((min_uV > 1500000) && (min_uV <= 1800000))
422*4882a593Smuzhiyun vsel = 60;
423*4882a593Smuzhiyun else if ((min_uV > 1350000) && (min_uV <= 1500000))
424*4882a593Smuzhiyun vsel = 59;
425*4882a593Smuzhiyun else if ((min_uV > 1300000) && (min_uV <= 1350000))
426*4882a593Smuzhiyun vsel = 58;
427*4882a593Smuzhiyun else
428*4882a593Smuzhiyun return -EINVAL;
429*4882a593Smuzhiyun break;
430*4882a593Smuzhiyun case SMPS_OFFSET_EN:
431*4882a593Smuzhiyun if (min_uV == 0)
432*4882a593Smuzhiyun vsel = 0;
433*4882a593Smuzhiyun else if ((min_uV >= 700000) && (min_uV <= 1420000)) {
434*4882a593Smuzhiyun vsel = DIV_ROUND_UP(min_uV - 700000, 12500);
435*4882a593Smuzhiyun vsel++;
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun /* Values 1..57 for vsel are linear and can be calculated
438*4882a593Smuzhiyun * values 58..62 are non linear.
439*4882a593Smuzhiyun */
440*4882a593Smuzhiyun else if ((min_uV > 1900000) && (min_uV <= 2100000))
441*4882a593Smuzhiyun vsel = 62;
442*4882a593Smuzhiyun else if ((min_uV > 1800000) && (min_uV <= 1900000))
443*4882a593Smuzhiyun vsel = 61;
444*4882a593Smuzhiyun else if ((min_uV > 1500000) && (min_uV <= 1800000))
445*4882a593Smuzhiyun vsel = 60;
446*4882a593Smuzhiyun else if ((min_uV > 1350000) && (min_uV <= 1500000))
447*4882a593Smuzhiyun vsel = 59;
448*4882a593Smuzhiyun else
449*4882a593Smuzhiyun return -EINVAL;
450*4882a593Smuzhiyun break;
451*4882a593Smuzhiyun case SMPS_EXTENDED_EN:
452*4882a593Smuzhiyun if (min_uV == 0) {
453*4882a593Smuzhiyun vsel = 0;
454*4882a593Smuzhiyun } else if ((min_uV >= 1852000) && (max_uV <= 4013600)) {
455*4882a593Smuzhiyun vsel = DIV_ROUND_UP(min_uV - 1852000, 38600);
456*4882a593Smuzhiyun vsel++;
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun break;
459*4882a593Smuzhiyun case SMPS_OFFSET_EN|SMPS_EXTENDED_EN:
460*4882a593Smuzhiyun if (min_uV == 0) {
461*4882a593Smuzhiyun vsel = 0;
462*4882a593Smuzhiyun } else if ((min_uV >= 2161000) && (min_uV <= 4321000)) {
463*4882a593Smuzhiyun vsel = DIV_ROUND_UP(min_uV - 2161000, 38600);
464*4882a593Smuzhiyun vsel++;
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun break;
467*4882a593Smuzhiyun }
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun return vsel;
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun
twl6030smps_set_voltage_sel(struct regulator_dev * rdev,unsigned int selector)472*4882a593Smuzhiyun static int twl6030smps_set_voltage_sel(struct regulator_dev *rdev,
473*4882a593Smuzhiyun unsigned int selector)
474*4882a593Smuzhiyun {
475*4882a593Smuzhiyun struct twlreg_info *info = rdev_get_drvdata(rdev);
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun return twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_VOLTAGE_SMPS,
478*4882a593Smuzhiyun selector);
479*4882a593Smuzhiyun }
480*4882a593Smuzhiyun
twl6030smps_get_voltage_sel(struct regulator_dev * rdev)481*4882a593Smuzhiyun static int twl6030smps_get_voltage_sel(struct regulator_dev *rdev)
482*4882a593Smuzhiyun {
483*4882a593Smuzhiyun struct twlreg_info *info = rdev_get_drvdata(rdev);
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun return twlreg_read(info, TWL_MODULE_PM_RECEIVER, VREG_VOLTAGE_SMPS);
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun static const struct regulator_ops twlsmps_ops = {
489*4882a593Smuzhiyun .list_voltage = twl6030smps_list_voltage,
490*4882a593Smuzhiyun .map_voltage = twl6030smps_map_voltage,
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun .set_voltage_sel = twl6030smps_set_voltage_sel,
493*4882a593Smuzhiyun .get_voltage_sel = twl6030smps_get_voltage_sel,
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun .enable = twl6030reg_enable,
496*4882a593Smuzhiyun .disable = twl6030reg_disable,
497*4882a593Smuzhiyun .is_enabled = twl6030reg_is_enabled,
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun .set_mode = twl6030reg_set_mode,
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun .get_status = twl6030reg_get_status,
502*4882a593Smuzhiyun };
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun /*----------------------------------------------------------------------*/
505*4882a593Smuzhiyun static const struct linear_range twl6030ldo_linear_range[] = {
506*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(0, 0, 0, 0),
507*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1000000, 1, 24, 100000),
508*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2750000, 31, 31, 0),
509*4882a593Smuzhiyun };
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun #define TWL6030_ADJUSTABLE_SMPS(label) \
512*4882a593Smuzhiyun static const struct twlreg_info TWL6030_INFO_##label = { \
513*4882a593Smuzhiyun .desc = { \
514*4882a593Smuzhiyun .name = #label, \
515*4882a593Smuzhiyun .id = TWL6030_REG_##label, \
516*4882a593Smuzhiyun .ops = &twl6030coresmps_ops, \
517*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
518*4882a593Smuzhiyun .owner = THIS_MODULE, \
519*4882a593Smuzhiyun }, \
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun #define TWL6030_ADJUSTABLE_LDO(label, offset) \
523*4882a593Smuzhiyun static const struct twlreg_info TWL6030_INFO_##label = { \
524*4882a593Smuzhiyun .base = offset, \
525*4882a593Smuzhiyun .desc = { \
526*4882a593Smuzhiyun .name = #label, \
527*4882a593Smuzhiyun .id = TWL6030_REG_##label, \
528*4882a593Smuzhiyun .n_voltages = 32, \
529*4882a593Smuzhiyun .linear_ranges = twl6030ldo_linear_range, \
530*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(twl6030ldo_linear_range), \
531*4882a593Smuzhiyun .ops = &twl6030ldo_ops, \
532*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
533*4882a593Smuzhiyun .owner = THIS_MODULE, \
534*4882a593Smuzhiyun }, \
535*4882a593Smuzhiyun }
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun #define TWL6032_ADJUSTABLE_LDO(label, offset) \
538*4882a593Smuzhiyun static const struct twlreg_info TWL6032_INFO_##label = { \
539*4882a593Smuzhiyun .base = offset, \
540*4882a593Smuzhiyun .features = TWL6032_SUBCLASS, \
541*4882a593Smuzhiyun .desc = { \
542*4882a593Smuzhiyun .name = #label, \
543*4882a593Smuzhiyun .id = TWL6032_REG_##label, \
544*4882a593Smuzhiyun .n_voltages = 32, \
545*4882a593Smuzhiyun .linear_ranges = twl6030ldo_linear_range, \
546*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(twl6030ldo_linear_range), \
547*4882a593Smuzhiyun .ops = &twl6030ldo_ops, \
548*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
549*4882a593Smuzhiyun .owner = THIS_MODULE, \
550*4882a593Smuzhiyun }, \
551*4882a593Smuzhiyun }
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun #define TWL6030_FIXED_LDO(label, offset, mVolts, turnon_delay) \
554*4882a593Smuzhiyun static const struct twlreg_info TWLFIXED_INFO_##label = { \
555*4882a593Smuzhiyun .base = offset, \
556*4882a593Smuzhiyun .id = 0, \
557*4882a593Smuzhiyun .desc = { \
558*4882a593Smuzhiyun .name = #label, \
559*4882a593Smuzhiyun .id = TWL6030##_REG_##label, \
560*4882a593Smuzhiyun .n_voltages = 1, \
561*4882a593Smuzhiyun .ops = &twl6030fixed_ops, \
562*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
563*4882a593Smuzhiyun .owner = THIS_MODULE, \
564*4882a593Smuzhiyun .min_uV = mVolts * 1000, \
565*4882a593Smuzhiyun .enable_time = turnon_delay, \
566*4882a593Smuzhiyun .of_map_mode = NULL, \
567*4882a593Smuzhiyun }, \
568*4882a593Smuzhiyun }
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun #define TWL6032_ADJUSTABLE_SMPS(label, offset) \
571*4882a593Smuzhiyun static const struct twlreg_info TWLSMPS_INFO_##label = { \
572*4882a593Smuzhiyun .base = offset, \
573*4882a593Smuzhiyun .features = TWL6032_SUBCLASS, \
574*4882a593Smuzhiyun .desc = { \
575*4882a593Smuzhiyun .name = #label, \
576*4882a593Smuzhiyun .id = TWL6032_REG_##label, \
577*4882a593Smuzhiyun .n_voltages = 63, \
578*4882a593Smuzhiyun .ops = &twlsmps_ops, \
579*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
580*4882a593Smuzhiyun .owner = THIS_MODULE, \
581*4882a593Smuzhiyun }, \
582*4882a593Smuzhiyun }
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun /* VUSBCP is managed *only* by the USB subchip */
585*4882a593Smuzhiyun /* 6030 REG with base as PMC Slave Misc : 0x0030 */
586*4882a593Smuzhiyun /* Turnon-delay and remap configuration values for 6030 are not
587*4882a593Smuzhiyun verified since the specification is not public */
588*4882a593Smuzhiyun TWL6030_ADJUSTABLE_SMPS(VDD1);
589*4882a593Smuzhiyun TWL6030_ADJUSTABLE_SMPS(VDD2);
590*4882a593Smuzhiyun TWL6030_ADJUSTABLE_SMPS(VDD3);
591*4882a593Smuzhiyun TWL6030_ADJUSTABLE_LDO(VAUX1_6030, 0x54);
592*4882a593Smuzhiyun TWL6030_ADJUSTABLE_LDO(VAUX2_6030, 0x58);
593*4882a593Smuzhiyun TWL6030_ADJUSTABLE_LDO(VAUX3_6030, 0x5c);
594*4882a593Smuzhiyun TWL6030_ADJUSTABLE_LDO(VMMC, 0x68);
595*4882a593Smuzhiyun TWL6030_ADJUSTABLE_LDO(VPP, 0x6c);
596*4882a593Smuzhiyun TWL6030_ADJUSTABLE_LDO(VUSIM, 0x74);
597*4882a593Smuzhiyun /* 6025 are renamed compared to 6030 versions */
598*4882a593Smuzhiyun TWL6032_ADJUSTABLE_LDO(LDO2, 0x54);
599*4882a593Smuzhiyun TWL6032_ADJUSTABLE_LDO(LDO4, 0x58);
600*4882a593Smuzhiyun TWL6032_ADJUSTABLE_LDO(LDO3, 0x5c);
601*4882a593Smuzhiyun TWL6032_ADJUSTABLE_LDO(LDO5, 0x68);
602*4882a593Smuzhiyun TWL6032_ADJUSTABLE_LDO(LDO1, 0x6c);
603*4882a593Smuzhiyun TWL6032_ADJUSTABLE_LDO(LDO7, 0x74);
604*4882a593Smuzhiyun TWL6032_ADJUSTABLE_LDO(LDO6, 0x60);
605*4882a593Smuzhiyun TWL6032_ADJUSTABLE_LDO(LDOLN, 0x64);
606*4882a593Smuzhiyun TWL6032_ADJUSTABLE_LDO(LDOUSB, 0x70);
607*4882a593Smuzhiyun TWL6030_FIXED_LDO(VANA, 0x50, 2100, 0);
608*4882a593Smuzhiyun TWL6030_FIXED_LDO(VCXIO, 0x60, 1800, 0);
609*4882a593Smuzhiyun TWL6030_FIXED_LDO(VDAC, 0x64, 1800, 0);
610*4882a593Smuzhiyun TWL6030_FIXED_LDO(VUSB, 0x70, 3300, 0);
611*4882a593Smuzhiyun TWL6030_FIXED_LDO(V1V8, 0x16, 1800, 0);
612*4882a593Smuzhiyun TWL6030_FIXED_LDO(V2V1, 0x1c, 2100, 0);
613*4882a593Smuzhiyun TWL6032_ADJUSTABLE_SMPS(SMPS3, 0x34);
614*4882a593Smuzhiyun TWL6032_ADJUSTABLE_SMPS(SMPS4, 0x10);
615*4882a593Smuzhiyun TWL6032_ADJUSTABLE_SMPS(VIO, 0x16);
616*4882a593Smuzhiyun
twl_get_smps_offset(void)617*4882a593Smuzhiyun static u8 twl_get_smps_offset(void)
618*4882a593Smuzhiyun {
619*4882a593Smuzhiyun u8 value;
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &value,
622*4882a593Smuzhiyun TWL6030_SMPS_OFFSET);
623*4882a593Smuzhiyun return value;
624*4882a593Smuzhiyun }
625*4882a593Smuzhiyun
twl_get_smps_mult(void)626*4882a593Smuzhiyun static u8 twl_get_smps_mult(void)
627*4882a593Smuzhiyun {
628*4882a593Smuzhiyun u8 value;
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &value,
631*4882a593Smuzhiyun TWL6030_SMPS_MULT);
632*4882a593Smuzhiyun return value;
633*4882a593Smuzhiyun }
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun #define TWL_OF_MATCH(comp, family, label) \
636*4882a593Smuzhiyun { \
637*4882a593Smuzhiyun .compatible = comp, \
638*4882a593Smuzhiyun .data = &family##_INFO_##label, \
639*4882a593Smuzhiyun }
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun #define TWL6030_OF_MATCH(comp, label) TWL_OF_MATCH(comp, TWL6030, label)
642*4882a593Smuzhiyun #define TWL6032_OF_MATCH(comp, label) TWL_OF_MATCH(comp, TWL6032, label)
643*4882a593Smuzhiyun #define TWLFIXED_OF_MATCH(comp, label) TWL_OF_MATCH(comp, TWLFIXED, label)
644*4882a593Smuzhiyun #define TWLSMPS_OF_MATCH(comp, label) TWL_OF_MATCH(comp, TWLSMPS, label)
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun static const struct of_device_id twl_of_match[] = {
647*4882a593Smuzhiyun TWL6030_OF_MATCH("ti,twl6030-vdd1", VDD1),
648*4882a593Smuzhiyun TWL6030_OF_MATCH("ti,twl6030-vdd2", VDD2),
649*4882a593Smuzhiyun TWL6030_OF_MATCH("ti,twl6030-vdd3", VDD3),
650*4882a593Smuzhiyun TWL6030_OF_MATCH("ti,twl6030-vaux1", VAUX1_6030),
651*4882a593Smuzhiyun TWL6030_OF_MATCH("ti,twl6030-vaux2", VAUX2_6030),
652*4882a593Smuzhiyun TWL6030_OF_MATCH("ti,twl6030-vaux3", VAUX3_6030),
653*4882a593Smuzhiyun TWL6030_OF_MATCH("ti,twl6030-vmmc", VMMC),
654*4882a593Smuzhiyun TWL6030_OF_MATCH("ti,twl6030-vpp", VPP),
655*4882a593Smuzhiyun TWL6030_OF_MATCH("ti,twl6030-vusim", VUSIM),
656*4882a593Smuzhiyun TWL6032_OF_MATCH("ti,twl6032-ldo2", LDO2),
657*4882a593Smuzhiyun TWL6032_OF_MATCH("ti,twl6032-ldo4", LDO4),
658*4882a593Smuzhiyun TWL6032_OF_MATCH("ti,twl6032-ldo3", LDO3),
659*4882a593Smuzhiyun TWL6032_OF_MATCH("ti,twl6032-ldo5", LDO5),
660*4882a593Smuzhiyun TWL6032_OF_MATCH("ti,twl6032-ldo1", LDO1),
661*4882a593Smuzhiyun TWL6032_OF_MATCH("ti,twl6032-ldo7", LDO7),
662*4882a593Smuzhiyun TWL6032_OF_MATCH("ti,twl6032-ldo6", LDO6),
663*4882a593Smuzhiyun TWL6032_OF_MATCH("ti,twl6032-ldoln", LDOLN),
664*4882a593Smuzhiyun TWL6032_OF_MATCH("ti,twl6032-ldousb", LDOUSB),
665*4882a593Smuzhiyun TWLFIXED_OF_MATCH("ti,twl6030-vana", VANA),
666*4882a593Smuzhiyun TWLFIXED_OF_MATCH("ti,twl6030-vcxio", VCXIO),
667*4882a593Smuzhiyun TWLFIXED_OF_MATCH("ti,twl6030-vdac", VDAC),
668*4882a593Smuzhiyun TWLFIXED_OF_MATCH("ti,twl6030-vusb", VUSB),
669*4882a593Smuzhiyun TWLFIXED_OF_MATCH("ti,twl6030-v1v8", V1V8),
670*4882a593Smuzhiyun TWLFIXED_OF_MATCH("ti,twl6030-v2v1", V2V1),
671*4882a593Smuzhiyun TWLSMPS_OF_MATCH("ti,twl6032-smps3", SMPS3),
672*4882a593Smuzhiyun TWLSMPS_OF_MATCH("ti,twl6032-smps4", SMPS4),
673*4882a593Smuzhiyun TWLSMPS_OF_MATCH("ti,twl6032-vio", VIO),
674*4882a593Smuzhiyun {},
675*4882a593Smuzhiyun };
676*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, twl_of_match);
677*4882a593Smuzhiyun
twlreg_probe(struct platform_device * pdev)678*4882a593Smuzhiyun static int twlreg_probe(struct platform_device *pdev)
679*4882a593Smuzhiyun {
680*4882a593Smuzhiyun int id;
681*4882a593Smuzhiyun struct twlreg_info *info;
682*4882a593Smuzhiyun const struct twlreg_info *template;
683*4882a593Smuzhiyun struct regulator_init_data *initdata;
684*4882a593Smuzhiyun struct regulation_constraints *c;
685*4882a593Smuzhiyun struct regulator_dev *rdev;
686*4882a593Smuzhiyun struct regulator_config config = { };
687*4882a593Smuzhiyun struct device_node *np = pdev->dev.of_node;
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun template = of_device_get_match_data(&pdev->dev);
690*4882a593Smuzhiyun if (!template)
691*4882a593Smuzhiyun return -ENODEV;
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun id = template->desc.id;
694*4882a593Smuzhiyun initdata = of_get_regulator_init_data(&pdev->dev, np, &template->desc);
695*4882a593Smuzhiyun if (!initdata)
696*4882a593Smuzhiyun return -EINVAL;
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun info = devm_kmemdup(&pdev->dev, template, sizeof(*info), GFP_KERNEL);
699*4882a593Smuzhiyun if (!info)
700*4882a593Smuzhiyun return -ENOMEM;
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun /* Constrain board-specific capabilities according to what
703*4882a593Smuzhiyun * this driver and the chip itself can actually do.
704*4882a593Smuzhiyun */
705*4882a593Smuzhiyun c = &initdata->constraints;
706*4882a593Smuzhiyun c->valid_modes_mask &= REGULATOR_MODE_NORMAL | REGULATOR_MODE_STANDBY;
707*4882a593Smuzhiyun c->valid_ops_mask &= REGULATOR_CHANGE_VOLTAGE
708*4882a593Smuzhiyun | REGULATOR_CHANGE_MODE
709*4882a593Smuzhiyun | REGULATOR_CHANGE_STATUS;
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun switch (id) {
712*4882a593Smuzhiyun case TWL6032_REG_SMPS3:
713*4882a593Smuzhiyun if (twl_get_smps_mult() & SMPS_MULTOFFSET_SMPS3)
714*4882a593Smuzhiyun info->flags |= SMPS_EXTENDED_EN;
715*4882a593Smuzhiyun if (twl_get_smps_offset() & SMPS_MULTOFFSET_SMPS3)
716*4882a593Smuzhiyun info->flags |= SMPS_OFFSET_EN;
717*4882a593Smuzhiyun break;
718*4882a593Smuzhiyun case TWL6032_REG_SMPS4:
719*4882a593Smuzhiyun if (twl_get_smps_mult() & SMPS_MULTOFFSET_SMPS4)
720*4882a593Smuzhiyun info->flags |= SMPS_EXTENDED_EN;
721*4882a593Smuzhiyun if (twl_get_smps_offset() & SMPS_MULTOFFSET_SMPS4)
722*4882a593Smuzhiyun info->flags |= SMPS_OFFSET_EN;
723*4882a593Smuzhiyun break;
724*4882a593Smuzhiyun case TWL6032_REG_VIO:
725*4882a593Smuzhiyun if (twl_get_smps_mult() & SMPS_MULTOFFSET_VIO)
726*4882a593Smuzhiyun info->flags |= SMPS_EXTENDED_EN;
727*4882a593Smuzhiyun if (twl_get_smps_offset() & SMPS_MULTOFFSET_VIO)
728*4882a593Smuzhiyun info->flags |= SMPS_OFFSET_EN;
729*4882a593Smuzhiyun break;
730*4882a593Smuzhiyun }
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun if (of_get_property(np, "ti,retain-on-reset", NULL))
733*4882a593Smuzhiyun info->flags |= TWL_6030_WARM_RESET;
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun config.dev = &pdev->dev;
736*4882a593Smuzhiyun config.init_data = initdata;
737*4882a593Smuzhiyun config.driver_data = info;
738*4882a593Smuzhiyun config.of_node = np;
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun rdev = devm_regulator_register(&pdev->dev, &info->desc, &config);
741*4882a593Smuzhiyun if (IS_ERR(rdev)) {
742*4882a593Smuzhiyun dev_err(&pdev->dev, "can't register %s, %ld\n",
743*4882a593Smuzhiyun info->desc.name, PTR_ERR(rdev));
744*4882a593Smuzhiyun return PTR_ERR(rdev);
745*4882a593Smuzhiyun }
746*4882a593Smuzhiyun platform_set_drvdata(pdev, rdev);
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun /* NOTE: many regulators support short-circuit IRQs (presentable
749*4882a593Smuzhiyun * as REGULATOR_OVER_CURRENT notifications?) configured via:
750*4882a593Smuzhiyun * - SC_CONFIG
751*4882a593Smuzhiyun * - SC_DETECT1 (vintana2, vmmc1/2, vaux1/2/3/4)
752*4882a593Smuzhiyun * - SC_DETECT2 (vusb, vdac, vio, vdd1/2, vpll2)
753*4882a593Smuzhiyun * - IT_CONFIG
754*4882a593Smuzhiyun */
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun return 0;
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun MODULE_ALIAS("platform:twl6030_reg");
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun static struct platform_driver twlreg_driver = {
762*4882a593Smuzhiyun .probe = twlreg_probe,
763*4882a593Smuzhiyun /* NOTE: short name, to work around driver model truncation of
764*4882a593Smuzhiyun * "twl_regulator.12" (and friends) to "twl_regulator.1".
765*4882a593Smuzhiyun */
766*4882a593Smuzhiyun .driver = {
767*4882a593Smuzhiyun .name = "twl6030_reg",
768*4882a593Smuzhiyun .of_match_table = of_match_ptr(twl_of_match),
769*4882a593Smuzhiyun },
770*4882a593Smuzhiyun };
771*4882a593Smuzhiyun
twlreg_init(void)772*4882a593Smuzhiyun static int __init twlreg_init(void)
773*4882a593Smuzhiyun {
774*4882a593Smuzhiyun return platform_driver_register(&twlreg_driver);
775*4882a593Smuzhiyun }
776*4882a593Smuzhiyun subsys_initcall(twlreg_init);
777*4882a593Smuzhiyun
twlreg_exit(void)778*4882a593Smuzhiyun static void __exit twlreg_exit(void)
779*4882a593Smuzhiyun {
780*4882a593Smuzhiyun platform_driver_unregister(&twlreg_driver);
781*4882a593Smuzhiyun }
782*4882a593Smuzhiyun module_exit(twlreg_exit)
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun MODULE_DESCRIPTION("TWL6030 regulator driver");
785*4882a593Smuzhiyun MODULE_LICENSE("GPL");
786