1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // tps80031-regulator.c -- TI TPS80031 regulator driver.
4*4882a593Smuzhiyun //
5*4882a593Smuzhiyun // Regulator driver for TI TPS80031/TPS80032 Fully Integrated Power
6*4882a593Smuzhiyun // Management with Power Path and Battery Charger.
7*4882a593Smuzhiyun //
8*4882a593Smuzhiyun // Copyright (c) 2012, NVIDIA Corporation.
9*4882a593Smuzhiyun //
10*4882a593Smuzhiyun // Author: Laxman Dewangan <ldewangan@nvidia.com>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/err.h>
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/kernel.h>
16*4882a593Smuzhiyun #include <linux/mfd/tps80031.h>
17*4882a593Smuzhiyun #include <linux/module.h>
18*4882a593Smuzhiyun #include <linux/platform_device.h>
19*4882a593Smuzhiyun #include <linux/regulator/driver.h>
20*4882a593Smuzhiyun #include <linux/regulator/machine.h>
21*4882a593Smuzhiyun #include <linux/slab.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* Flags for DCDC Voltage reading */
24*4882a593Smuzhiyun #define DCDC_OFFSET_EN BIT(0)
25*4882a593Smuzhiyun #define DCDC_EXTENDED_EN BIT(1)
26*4882a593Smuzhiyun #define TRACK_MODE_ENABLE BIT(2)
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define SMPS_MULTOFFSET_VIO BIT(1)
29*4882a593Smuzhiyun #define SMPS_MULTOFFSET_SMPS1 BIT(3)
30*4882a593Smuzhiyun #define SMPS_MULTOFFSET_SMPS2 BIT(4)
31*4882a593Smuzhiyun #define SMPS_MULTOFFSET_SMPS3 BIT(6)
32*4882a593Smuzhiyun #define SMPS_MULTOFFSET_SMPS4 BIT(0)
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define SMPS_CMD_MASK 0xC0
35*4882a593Smuzhiyun #define SMPS_VSEL_MASK 0x3F
36*4882a593Smuzhiyun #define LDO_VSEL_MASK 0x1F
37*4882a593Smuzhiyun #define LDO_TRACK_VSEL_MASK 0x3F
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define MISC2_LDOUSB_IN_VSYS BIT(4)
40*4882a593Smuzhiyun #define MISC2_LDOUSB_IN_PMID BIT(3)
41*4882a593Smuzhiyun #define MISC2_LDOUSB_IN_MASK 0x18
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #define MISC2_LDO3_SEL_VIB_VAL BIT(0)
44*4882a593Smuzhiyun #define MISC2_LDO3_SEL_VIB_MASK 0x1
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #define BOOST_HW_PWR_EN BIT(5)
47*4882a593Smuzhiyun #define BOOST_HW_PWR_EN_MASK BIT(5)
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #define OPA_MODE_EN BIT(6)
50*4882a593Smuzhiyun #define OPA_MODE_EN_MASK BIT(6)
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #define USB_VBUS_CTRL_SET 0x04
53*4882a593Smuzhiyun #define USB_VBUS_CTRL_CLR 0x05
54*4882a593Smuzhiyun #define VBUS_DISCHRG 0x20
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun struct tps80031_regulator_info {
57*4882a593Smuzhiyun /* Regulator register address.*/
58*4882a593Smuzhiyun u8 trans_reg;
59*4882a593Smuzhiyun u8 state_reg;
60*4882a593Smuzhiyun u8 force_reg;
61*4882a593Smuzhiyun u8 volt_reg;
62*4882a593Smuzhiyun u8 volt_id;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /*Power request bits */
65*4882a593Smuzhiyun int preq_bit;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* used by regulator core */
68*4882a593Smuzhiyun struct regulator_desc desc;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun struct tps80031_regulator {
73*4882a593Smuzhiyun struct device *dev;
74*4882a593Smuzhiyun struct tps80031_regulator_info *rinfo;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun u8 device_flags;
77*4882a593Smuzhiyun unsigned int config_flags;
78*4882a593Smuzhiyun unsigned int ext_ctrl_flag;
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
to_tps80031_dev(struct regulator_dev * rdev)81*4882a593Smuzhiyun static inline struct device *to_tps80031_dev(struct regulator_dev *rdev)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun return rdev_get_dev(rdev)->parent->parent;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
tps80031_reg_is_enabled(struct regulator_dev * rdev)86*4882a593Smuzhiyun static int tps80031_reg_is_enabled(struct regulator_dev *rdev)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
89*4882a593Smuzhiyun struct device *parent = to_tps80031_dev(rdev);
90*4882a593Smuzhiyun u8 reg_val;
91*4882a593Smuzhiyun int ret;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun if (ri->ext_ctrl_flag & TPS80031_EXT_PWR_REQ)
94*4882a593Smuzhiyun return true;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun ret = tps80031_read(parent, TPS80031_SLAVE_ID1, ri->rinfo->state_reg,
97*4882a593Smuzhiyun ®_val);
98*4882a593Smuzhiyun if (ret < 0) {
99*4882a593Smuzhiyun dev_err(&rdev->dev, "Reg 0x%02x read failed, err = %d\n",
100*4882a593Smuzhiyun ri->rinfo->state_reg, ret);
101*4882a593Smuzhiyun return ret;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun return (reg_val & TPS80031_STATE_MASK) == TPS80031_STATE_ON;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
tps80031_reg_enable(struct regulator_dev * rdev)106*4882a593Smuzhiyun static int tps80031_reg_enable(struct regulator_dev *rdev)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
109*4882a593Smuzhiyun struct device *parent = to_tps80031_dev(rdev);
110*4882a593Smuzhiyun int ret;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun if (ri->ext_ctrl_flag & TPS80031_EXT_PWR_REQ)
113*4882a593Smuzhiyun return 0;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun ret = tps80031_update(parent, TPS80031_SLAVE_ID1, ri->rinfo->state_reg,
116*4882a593Smuzhiyun TPS80031_STATE_ON, TPS80031_STATE_MASK);
117*4882a593Smuzhiyun if (ret < 0) {
118*4882a593Smuzhiyun dev_err(&rdev->dev, "Reg 0x%02x update failed, err = %d\n",
119*4882a593Smuzhiyun ri->rinfo->state_reg, ret);
120*4882a593Smuzhiyun return ret;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun return ret;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun
tps80031_reg_disable(struct regulator_dev * rdev)125*4882a593Smuzhiyun static int tps80031_reg_disable(struct regulator_dev *rdev)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
128*4882a593Smuzhiyun struct device *parent = to_tps80031_dev(rdev);
129*4882a593Smuzhiyun int ret;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun if (ri->ext_ctrl_flag & TPS80031_EXT_PWR_REQ)
132*4882a593Smuzhiyun return 0;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun ret = tps80031_update(parent, TPS80031_SLAVE_ID1, ri->rinfo->state_reg,
135*4882a593Smuzhiyun TPS80031_STATE_OFF, TPS80031_STATE_MASK);
136*4882a593Smuzhiyun if (ret < 0)
137*4882a593Smuzhiyun dev_err(&rdev->dev, "Reg 0x%02x update failed, err = %d\n",
138*4882a593Smuzhiyun ri->rinfo->state_reg, ret);
139*4882a593Smuzhiyun return ret;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun /* DCDC voltages for the selector of 58 to 63 */
143*4882a593Smuzhiyun static const int tps80031_dcdc_voltages[4][5] = {
144*4882a593Smuzhiyun { 1350, 1500, 1800, 1900, 2100},
145*4882a593Smuzhiyun { 1350, 1500, 1800, 1900, 2100},
146*4882a593Smuzhiyun { 2084, 2315, 2778, 2932, 3241},
147*4882a593Smuzhiyun { 4167, 2315, 2778, 2932, 3241},
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun
tps80031_dcdc_list_voltage(struct regulator_dev * rdev,unsigned sel)150*4882a593Smuzhiyun static int tps80031_dcdc_list_voltage(struct regulator_dev *rdev, unsigned sel)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
153*4882a593Smuzhiyun int volt_index = ri->device_flags & 0x3;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun if (sel == 0)
156*4882a593Smuzhiyun return 0;
157*4882a593Smuzhiyun else if (sel < 58)
158*4882a593Smuzhiyun return regulator_list_voltage_linear(rdev, sel - 1);
159*4882a593Smuzhiyun else
160*4882a593Smuzhiyun return tps80031_dcdc_voltages[volt_index][sel - 58] * 1000;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
tps80031_dcdc_set_voltage_sel(struct regulator_dev * rdev,unsigned vsel)163*4882a593Smuzhiyun static int tps80031_dcdc_set_voltage_sel(struct regulator_dev *rdev,
164*4882a593Smuzhiyun unsigned vsel)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
167*4882a593Smuzhiyun struct device *parent = to_tps80031_dev(rdev);
168*4882a593Smuzhiyun int ret;
169*4882a593Smuzhiyun u8 reg_val;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun if (ri->rinfo->force_reg) {
172*4882a593Smuzhiyun ret = tps80031_read(parent, ri->rinfo->volt_id,
173*4882a593Smuzhiyun ri->rinfo->force_reg, ®_val);
174*4882a593Smuzhiyun if (ret < 0) {
175*4882a593Smuzhiyun dev_err(ri->dev, "reg 0x%02x read failed, e = %d\n",
176*4882a593Smuzhiyun ri->rinfo->force_reg, ret);
177*4882a593Smuzhiyun return ret;
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun if (!(reg_val & SMPS_CMD_MASK)) {
180*4882a593Smuzhiyun ret = tps80031_update(parent, ri->rinfo->volt_id,
181*4882a593Smuzhiyun ri->rinfo->force_reg, vsel, SMPS_VSEL_MASK);
182*4882a593Smuzhiyun if (ret < 0)
183*4882a593Smuzhiyun dev_err(ri->dev,
184*4882a593Smuzhiyun "reg 0x%02x update failed, e = %d\n",
185*4882a593Smuzhiyun ri->rinfo->force_reg, ret);
186*4882a593Smuzhiyun return ret;
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun ret = tps80031_update(parent, ri->rinfo->volt_id,
190*4882a593Smuzhiyun ri->rinfo->volt_reg, vsel, SMPS_VSEL_MASK);
191*4882a593Smuzhiyun if (ret < 0)
192*4882a593Smuzhiyun dev_err(ri->dev, "reg 0x%02x update failed, e = %d\n",
193*4882a593Smuzhiyun ri->rinfo->volt_reg, ret);
194*4882a593Smuzhiyun return ret;
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun
tps80031_dcdc_get_voltage_sel(struct regulator_dev * rdev)197*4882a593Smuzhiyun static int tps80031_dcdc_get_voltage_sel(struct regulator_dev *rdev)
198*4882a593Smuzhiyun {
199*4882a593Smuzhiyun struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
200*4882a593Smuzhiyun struct device *parent = to_tps80031_dev(rdev);
201*4882a593Smuzhiyun uint8_t vsel = 0;
202*4882a593Smuzhiyun int ret;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun if (ri->rinfo->force_reg) {
205*4882a593Smuzhiyun ret = tps80031_read(parent, ri->rinfo->volt_id,
206*4882a593Smuzhiyun ri->rinfo->force_reg, &vsel);
207*4882a593Smuzhiyun if (ret < 0) {
208*4882a593Smuzhiyun dev_err(ri->dev, "reg 0x%02x read failed, e = %d\n",
209*4882a593Smuzhiyun ri->rinfo->force_reg, ret);
210*4882a593Smuzhiyun return ret;
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun if (!(vsel & SMPS_CMD_MASK))
214*4882a593Smuzhiyun return vsel & SMPS_VSEL_MASK;
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun ret = tps80031_read(parent, ri->rinfo->volt_id,
217*4882a593Smuzhiyun ri->rinfo->volt_reg, &vsel);
218*4882a593Smuzhiyun if (ret < 0) {
219*4882a593Smuzhiyun dev_err(ri->dev, "reg 0x%02x read failed, e = %d\n",
220*4882a593Smuzhiyun ri->rinfo->volt_reg, ret);
221*4882a593Smuzhiyun return ret;
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun return vsel & SMPS_VSEL_MASK;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
tps80031_ldo_list_voltage(struct regulator_dev * rdev,unsigned int sel)226*4882a593Smuzhiyun static int tps80031_ldo_list_voltage(struct regulator_dev *rdev,
227*4882a593Smuzhiyun unsigned int sel)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
230*4882a593Smuzhiyun struct device *parent = to_tps80031_dev(rdev);
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun /* Check for valid setting for TPS80031 or TPS80032-ES1.0 */
233*4882a593Smuzhiyun if ((ri->rinfo->desc.id == TPS80031_REGULATOR_LDO2) &&
234*4882a593Smuzhiyun (ri->device_flags & TRACK_MODE_ENABLE)) {
235*4882a593Smuzhiyun unsigned nvsel = (sel) & 0x1F;
236*4882a593Smuzhiyun if (((tps80031_get_chip_info(parent) == TPS80031) ||
237*4882a593Smuzhiyun ((tps80031_get_chip_info(parent) == TPS80032) &&
238*4882a593Smuzhiyun (tps80031_get_pmu_version(parent) == 0x0))) &&
239*4882a593Smuzhiyun ((nvsel == 0x0) || (nvsel >= 0x19 && nvsel <= 0x1F))) {
240*4882a593Smuzhiyun dev_err(ri->dev,
241*4882a593Smuzhiyun "Invalid sel %d in track mode LDO2\n",
242*4882a593Smuzhiyun nvsel);
243*4882a593Smuzhiyun return -EINVAL;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun return regulator_list_voltage_linear(rdev, sel);
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun
tps80031_ldo_map_voltage(struct regulator_dev * rdev,int min_uV,int max_uV)250*4882a593Smuzhiyun static int tps80031_ldo_map_voltage(struct regulator_dev *rdev,
251*4882a593Smuzhiyun int min_uV, int max_uV)
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
254*4882a593Smuzhiyun struct device *parent = to_tps80031_dev(rdev);
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun /* Check for valid setting for TPS80031 or TPS80032-ES1.0 */
257*4882a593Smuzhiyun if ((ri->rinfo->desc.id == TPS80031_REGULATOR_LDO2) &&
258*4882a593Smuzhiyun (ri->device_flags & TRACK_MODE_ENABLE)) {
259*4882a593Smuzhiyun if (((tps80031_get_chip_info(parent) == TPS80031) ||
260*4882a593Smuzhiyun ((tps80031_get_chip_info(parent) == TPS80032) &&
261*4882a593Smuzhiyun (tps80031_get_pmu_version(parent) == 0x0)))) {
262*4882a593Smuzhiyun return regulator_map_voltage_iterate(rdev, min_uV,
263*4882a593Smuzhiyun max_uV);
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun return regulator_map_voltage_linear(rdev, min_uV, max_uV);
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
tps80031_vbus_is_enabled(struct regulator_dev * rdev)270*4882a593Smuzhiyun static int tps80031_vbus_is_enabled(struct regulator_dev *rdev)
271*4882a593Smuzhiyun {
272*4882a593Smuzhiyun struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
273*4882a593Smuzhiyun struct device *parent = to_tps80031_dev(rdev);
274*4882a593Smuzhiyun int ret;
275*4882a593Smuzhiyun uint8_t ctrl1 = 0;
276*4882a593Smuzhiyun uint8_t ctrl3 = 0;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun ret = tps80031_read(parent, TPS80031_SLAVE_ID2,
279*4882a593Smuzhiyun TPS80031_CHARGERUSB_CTRL1, &ctrl1);
280*4882a593Smuzhiyun if (ret < 0) {
281*4882a593Smuzhiyun dev_err(ri->dev, "reg 0x%02x read failed, e = %d\n",
282*4882a593Smuzhiyun TPS80031_CHARGERUSB_CTRL1, ret);
283*4882a593Smuzhiyun return ret;
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun ret = tps80031_read(parent, TPS80031_SLAVE_ID2,
286*4882a593Smuzhiyun TPS80031_CHARGERUSB_CTRL3, &ctrl3);
287*4882a593Smuzhiyun if (ret < 0) {
288*4882a593Smuzhiyun dev_err(ri->dev, "reg 0x%02x read failed, e = %d\n",
289*4882a593Smuzhiyun TPS80031_CHARGERUSB_CTRL3, ret);
290*4882a593Smuzhiyun return ret;
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun if ((ctrl1 & OPA_MODE_EN) && (ctrl3 & BOOST_HW_PWR_EN))
293*4882a593Smuzhiyun return 1;
294*4882a593Smuzhiyun return ret;
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun
tps80031_vbus_enable(struct regulator_dev * rdev)297*4882a593Smuzhiyun static int tps80031_vbus_enable(struct regulator_dev *rdev)
298*4882a593Smuzhiyun {
299*4882a593Smuzhiyun struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
300*4882a593Smuzhiyun struct device *parent = to_tps80031_dev(rdev);
301*4882a593Smuzhiyun int ret;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun ret = tps80031_set_bits(parent, TPS80031_SLAVE_ID2,
304*4882a593Smuzhiyun TPS80031_CHARGERUSB_CTRL1, OPA_MODE_EN);
305*4882a593Smuzhiyun if (ret < 0) {
306*4882a593Smuzhiyun dev_err(ri->dev, "reg 0x%02x read failed, e = %d\n",
307*4882a593Smuzhiyun TPS80031_CHARGERUSB_CTRL1, ret);
308*4882a593Smuzhiyun return ret;
309*4882a593Smuzhiyun }
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun ret = tps80031_set_bits(parent, TPS80031_SLAVE_ID2,
312*4882a593Smuzhiyun TPS80031_CHARGERUSB_CTRL3, BOOST_HW_PWR_EN);
313*4882a593Smuzhiyun if (ret < 0) {
314*4882a593Smuzhiyun dev_err(ri->dev, "reg 0x%02x read failed, e = %d\n",
315*4882a593Smuzhiyun TPS80031_CHARGERUSB_CTRL3, ret);
316*4882a593Smuzhiyun return ret;
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun return ret;
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun
tps80031_vbus_disable(struct regulator_dev * rdev)321*4882a593Smuzhiyun static int tps80031_vbus_disable(struct regulator_dev *rdev)
322*4882a593Smuzhiyun {
323*4882a593Smuzhiyun struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
324*4882a593Smuzhiyun struct device *parent = to_tps80031_dev(rdev);
325*4882a593Smuzhiyun int ret;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun if (ri->config_flags & TPS80031_VBUS_DISCHRG_EN_PDN) {
328*4882a593Smuzhiyun ret = tps80031_write(parent, TPS80031_SLAVE_ID2,
329*4882a593Smuzhiyun USB_VBUS_CTRL_SET, VBUS_DISCHRG);
330*4882a593Smuzhiyun if (ret < 0) {
331*4882a593Smuzhiyun dev_err(ri->dev, "reg 0x%02x write failed, e = %d\n",
332*4882a593Smuzhiyun USB_VBUS_CTRL_SET, ret);
333*4882a593Smuzhiyun return ret;
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun ret = tps80031_clr_bits(parent, TPS80031_SLAVE_ID2,
338*4882a593Smuzhiyun TPS80031_CHARGERUSB_CTRL1, OPA_MODE_EN);
339*4882a593Smuzhiyun if (ret < 0) {
340*4882a593Smuzhiyun dev_err(ri->dev, "reg 0x%02x clearbit failed, e = %d\n",
341*4882a593Smuzhiyun TPS80031_CHARGERUSB_CTRL1, ret);
342*4882a593Smuzhiyun return ret;
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun ret = tps80031_clr_bits(parent, TPS80031_SLAVE_ID2,
346*4882a593Smuzhiyun TPS80031_CHARGERUSB_CTRL3, BOOST_HW_PWR_EN);
347*4882a593Smuzhiyun if (ret < 0) {
348*4882a593Smuzhiyun dev_err(ri->dev, "reg 0x%02x clearbit failed, e = %d\n",
349*4882a593Smuzhiyun TPS80031_CHARGERUSB_CTRL3, ret);
350*4882a593Smuzhiyun return ret;
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun mdelay(DIV_ROUND_UP(ri->rinfo->desc.enable_time, 1000));
354*4882a593Smuzhiyun if (ri->config_flags & TPS80031_VBUS_DISCHRG_EN_PDN) {
355*4882a593Smuzhiyun ret = tps80031_write(parent, TPS80031_SLAVE_ID2,
356*4882a593Smuzhiyun USB_VBUS_CTRL_CLR, VBUS_DISCHRG);
357*4882a593Smuzhiyun if (ret < 0) {
358*4882a593Smuzhiyun dev_err(ri->dev, "reg 0x%02x write failed, e = %d\n",
359*4882a593Smuzhiyun USB_VBUS_CTRL_CLR, ret);
360*4882a593Smuzhiyun return ret;
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun return ret;
364*4882a593Smuzhiyun }
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun static const struct regulator_ops tps80031_dcdc_ops = {
367*4882a593Smuzhiyun .list_voltage = tps80031_dcdc_list_voltage,
368*4882a593Smuzhiyun .set_voltage_sel = tps80031_dcdc_set_voltage_sel,
369*4882a593Smuzhiyun .get_voltage_sel = tps80031_dcdc_get_voltage_sel,
370*4882a593Smuzhiyun .enable = tps80031_reg_enable,
371*4882a593Smuzhiyun .disable = tps80031_reg_disable,
372*4882a593Smuzhiyun .is_enabled = tps80031_reg_is_enabled,
373*4882a593Smuzhiyun };
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun static const struct regulator_ops tps80031_ldo_ops = {
376*4882a593Smuzhiyun .list_voltage = tps80031_ldo_list_voltage,
377*4882a593Smuzhiyun .map_voltage = tps80031_ldo_map_voltage,
378*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
379*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
380*4882a593Smuzhiyun .enable = tps80031_reg_enable,
381*4882a593Smuzhiyun .disable = tps80031_reg_disable,
382*4882a593Smuzhiyun .is_enabled = tps80031_reg_is_enabled,
383*4882a593Smuzhiyun };
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun static const struct regulator_ops tps80031_vbus_sw_ops = {
386*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
387*4882a593Smuzhiyun .enable = tps80031_vbus_enable,
388*4882a593Smuzhiyun .disable = tps80031_vbus_disable,
389*4882a593Smuzhiyun .is_enabled = tps80031_vbus_is_enabled,
390*4882a593Smuzhiyun };
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun static const struct regulator_ops tps80031_vbus_hw_ops = {
393*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
394*4882a593Smuzhiyun };
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun static const struct regulator_ops tps80031_ext_reg_ops = {
397*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
398*4882a593Smuzhiyun .enable = tps80031_reg_enable,
399*4882a593Smuzhiyun .disable = tps80031_reg_disable,
400*4882a593Smuzhiyun .is_enabled = tps80031_reg_is_enabled,
401*4882a593Smuzhiyun };
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun /* Non-exiting default definition for some register */
404*4882a593Smuzhiyun #define TPS80031_SMPS3_CFG_FORCE 0
405*4882a593Smuzhiyun #define TPS80031_SMPS4_CFG_FORCE 0
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun #define TPS80031_VBUS_CFG_TRANS 0
408*4882a593Smuzhiyun #define TPS80031_VBUS_CFG_STATE 0
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun #define TPS80031_REG_SMPS(_id, _volt_id, _pbit) \
411*4882a593Smuzhiyun { \
412*4882a593Smuzhiyun .trans_reg = TPS80031_##_id##_CFG_TRANS, \
413*4882a593Smuzhiyun .state_reg = TPS80031_##_id##_CFG_STATE, \
414*4882a593Smuzhiyun .force_reg = TPS80031_##_id##_CFG_FORCE, \
415*4882a593Smuzhiyun .volt_reg = TPS80031_##_id##_CFG_VOLTAGE, \
416*4882a593Smuzhiyun .volt_id = TPS80031_SLAVE_##_volt_id, \
417*4882a593Smuzhiyun .preq_bit = _pbit, \
418*4882a593Smuzhiyun .desc = { \
419*4882a593Smuzhiyun .name = "tps80031_"#_id, \
420*4882a593Smuzhiyun .id = TPS80031_REGULATOR_##_id, \
421*4882a593Smuzhiyun .n_voltages = 63, \
422*4882a593Smuzhiyun .ops = &tps80031_dcdc_ops, \
423*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
424*4882a593Smuzhiyun .owner = THIS_MODULE, \
425*4882a593Smuzhiyun .enable_time = 500, \
426*4882a593Smuzhiyun }, \
427*4882a593Smuzhiyun }
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun #define TPS80031_REG_LDO(_id, _preq_bit) \
430*4882a593Smuzhiyun { \
431*4882a593Smuzhiyun .trans_reg = TPS80031_##_id##_CFG_TRANS, \
432*4882a593Smuzhiyun .state_reg = TPS80031_##_id##_CFG_STATE, \
433*4882a593Smuzhiyun .volt_reg = TPS80031_##_id##_CFG_VOLTAGE, \
434*4882a593Smuzhiyun .volt_id = TPS80031_SLAVE_ID1, \
435*4882a593Smuzhiyun .preq_bit = _preq_bit, \
436*4882a593Smuzhiyun .desc = { \
437*4882a593Smuzhiyun .owner = THIS_MODULE, \
438*4882a593Smuzhiyun .name = "tps80031_"#_id, \
439*4882a593Smuzhiyun .id = TPS80031_REGULATOR_##_id, \
440*4882a593Smuzhiyun .ops = &tps80031_ldo_ops, \
441*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
442*4882a593Smuzhiyun .min_uV = 1000000, \
443*4882a593Smuzhiyun .uV_step = 100000, \
444*4882a593Smuzhiyun .linear_min_sel = 1, \
445*4882a593Smuzhiyun .n_voltages = 25, \
446*4882a593Smuzhiyun .vsel_reg = TPS80031_##_id##_CFG_VOLTAGE, \
447*4882a593Smuzhiyun .vsel_mask = LDO_VSEL_MASK, \
448*4882a593Smuzhiyun .enable_time = 500, \
449*4882a593Smuzhiyun }, \
450*4882a593Smuzhiyun }
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun #define TPS80031_REG_FIXED(_id, max_mV, _ops, _delay, _pbit) \
453*4882a593Smuzhiyun { \
454*4882a593Smuzhiyun .trans_reg = TPS80031_##_id##_CFG_TRANS, \
455*4882a593Smuzhiyun .state_reg = TPS80031_##_id##_CFG_STATE, \
456*4882a593Smuzhiyun .volt_id = TPS80031_SLAVE_ID1, \
457*4882a593Smuzhiyun .preq_bit = _pbit, \
458*4882a593Smuzhiyun .desc = { \
459*4882a593Smuzhiyun .name = "tps80031_"#_id, \
460*4882a593Smuzhiyun .id = TPS80031_REGULATOR_##_id, \
461*4882a593Smuzhiyun .min_uV = max_mV * 1000, \
462*4882a593Smuzhiyun .n_voltages = 1, \
463*4882a593Smuzhiyun .ops = &_ops, \
464*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
465*4882a593Smuzhiyun .owner = THIS_MODULE, \
466*4882a593Smuzhiyun .enable_time = _delay, \
467*4882a593Smuzhiyun }, \
468*4882a593Smuzhiyun }
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun static struct tps80031_regulator_info tps80031_rinfo[TPS80031_REGULATOR_MAX] = {
471*4882a593Smuzhiyun TPS80031_REG_SMPS(VIO, ID0, 4),
472*4882a593Smuzhiyun TPS80031_REG_SMPS(SMPS1, ID0, 0),
473*4882a593Smuzhiyun TPS80031_REG_SMPS(SMPS2, ID0, 1),
474*4882a593Smuzhiyun TPS80031_REG_SMPS(SMPS3, ID1, 2),
475*4882a593Smuzhiyun TPS80031_REG_SMPS(SMPS4, ID1, 3),
476*4882a593Smuzhiyun TPS80031_REG_LDO(VANA, -1),
477*4882a593Smuzhiyun TPS80031_REG_LDO(LDO1, 8),
478*4882a593Smuzhiyun TPS80031_REG_LDO(LDO2, 9),
479*4882a593Smuzhiyun TPS80031_REG_LDO(LDO3, 10),
480*4882a593Smuzhiyun TPS80031_REG_LDO(LDO4, 11),
481*4882a593Smuzhiyun TPS80031_REG_LDO(LDO5, 12),
482*4882a593Smuzhiyun TPS80031_REG_LDO(LDO6, 13),
483*4882a593Smuzhiyun TPS80031_REG_LDO(LDO7, 14),
484*4882a593Smuzhiyun TPS80031_REG_LDO(LDOLN, 15),
485*4882a593Smuzhiyun TPS80031_REG_LDO(LDOUSB, 5),
486*4882a593Smuzhiyun TPS80031_REG_FIXED(VBUS, 5000, tps80031_vbus_hw_ops, 100000, -1),
487*4882a593Smuzhiyun TPS80031_REG_FIXED(REGEN1, 3300, tps80031_ext_reg_ops, 0, 16),
488*4882a593Smuzhiyun TPS80031_REG_FIXED(REGEN2, 3300, tps80031_ext_reg_ops, 0, 17),
489*4882a593Smuzhiyun TPS80031_REG_FIXED(SYSEN, 3300, tps80031_ext_reg_ops, 0, 18),
490*4882a593Smuzhiyun };
491*4882a593Smuzhiyun
tps80031_power_req_config(struct device * parent,struct tps80031_regulator * ri,struct tps80031_regulator_platform_data * tps80031_pdata)492*4882a593Smuzhiyun static int tps80031_power_req_config(struct device *parent,
493*4882a593Smuzhiyun struct tps80031_regulator *ri,
494*4882a593Smuzhiyun struct tps80031_regulator_platform_data *tps80031_pdata)
495*4882a593Smuzhiyun {
496*4882a593Smuzhiyun int ret = 0;
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun if (ri->rinfo->preq_bit < 0)
499*4882a593Smuzhiyun goto skip_pwr_req_config;
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun ret = tps80031_ext_power_req_config(parent, ri->ext_ctrl_flag,
502*4882a593Smuzhiyun ri->rinfo->preq_bit, ri->rinfo->state_reg,
503*4882a593Smuzhiyun ri->rinfo->trans_reg);
504*4882a593Smuzhiyun if (ret < 0) {
505*4882a593Smuzhiyun dev_err(ri->dev, "ext powerreq config failed, err = %d\n", ret);
506*4882a593Smuzhiyun return ret;
507*4882a593Smuzhiyun }
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun skip_pwr_req_config:
510*4882a593Smuzhiyun if (tps80031_pdata->ext_ctrl_flag & TPS80031_PWR_ON_ON_SLEEP) {
511*4882a593Smuzhiyun ret = tps80031_update(parent, TPS80031_SLAVE_ID1,
512*4882a593Smuzhiyun ri->rinfo->trans_reg, TPS80031_TRANS_SLEEP_ON,
513*4882a593Smuzhiyun TPS80031_TRANS_SLEEP_MASK);
514*4882a593Smuzhiyun if (ret < 0) {
515*4882a593Smuzhiyun dev_err(ri->dev, "Reg 0x%02x update failed, e %d\n",
516*4882a593Smuzhiyun ri->rinfo->trans_reg, ret);
517*4882a593Smuzhiyun return ret;
518*4882a593Smuzhiyun }
519*4882a593Smuzhiyun }
520*4882a593Smuzhiyun return ret;
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun
tps80031_regulator_config(struct device * parent,struct tps80031_regulator * ri,struct tps80031_regulator_platform_data * tps80031_pdata)523*4882a593Smuzhiyun static int tps80031_regulator_config(struct device *parent,
524*4882a593Smuzhiyun struct tps80031_regulator *ri,
525*4882a593Smuzhiyun struct tps80031_regulator_platform_data *tps80031_pdata)
526*4882a593Smuzhiyun {
527*4882a593Smuzhiyun int ret = 0;
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun switch (ri->rinfo->desc.id) {
530*4882a593Smuzhiyun case TPS80031_REGULATOR_LDOUSB:
531*4882a593Smuzhiyun if (ri->config_flags & (TPS80031_USBLDO_INPUT_VSYS |
532*4882a593Smuzhiyun TPS80031_USBLDO_INPUT_PMID)) {
533*4882a593Smuzhiyun unsigned val;
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun if (ri->config_flags & TPS80031_USBLDO_INPUT_VSYS)
536*4882a593Smuzhiyun val = MISC2_LDOUSB_IN_VSYS;
537*4882a593Smuzhiyun else
538*4882a593Smuzhiyun val = MISC2_LDOUSB_IN_PMID;
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun ret = tps80031_update(parent, TPS80031_SLAVE_ID1,
541*4882a593Smuzhiyun TPS80031_MISC2, val,
542*4882a593Smuzhiyun MISC2_LDOUSB_IN_MASK);
543*4882a593Smuzhiyun if (ret < 0) {
544*4882a593Smuzhiyun dev_err(ri->dev,
545*4882a593Smuzhiyun "LDOUSB config failed, e= %d\n", ret);
546*4882a593Smuzhiyun return ret;
547*4882a593Smuzhiyun }
548*4882a593Smuzhiyun }
549*4882a593Smuzhiyun break;
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun case TPS80031_REGULATOR_LDO3:
552*4882a593Smuzhiyun if (ri->config_flags & TPS80031_LDO3_OUTPUT_VIB) {
553*4882a593Smuzhiyun ret = tps80031_update(parent, TPS80031_SLAVE_ID1,
554*4882a593Smuzhiyun TPS80031_MISC2, MISC2_LDO3_SEL_VIB_VAL,
555*4882a593Smuzhiyun MISC2_LDO3_SEL_VIB_MASK);
556*4882a593Smuzhiyun if (ret < 0) {
557*4882a593Smuzhiyun dev_err(ri->dev,
558*4882a593Smuzhiyun "LDO3 config failed, e = %d\n", ret);
559*4882a593Smuzhiyun return ret;
560*4882a593Smuzhiyun }
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun break;
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun case TPS80031_REGULATOR_VBUS:
565*4882a593Smuzhiyun /* Provide SW control Ops if VBUS is SW control */
566*4882a593Smuzhiyun if (!(ri->config_flags & TPS80031_VBUS_SW_ONLY))
567*4882a593Smuzhiyun ri->rinfo->desc.ops = &tps80031_vbus_sw_ops;
568*4882a593Smuzhiyun break;
569*4882a593Smuzhiyun default:
570*4882a593Smuzhiyun break;
571*4882a593Smuzhiyun }
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun /* Configure Active state to ON, SLEEP to OFF and OFF_state to OFF */
574*4882a593Smuzhiyun ret = tps80031_update(parent, TPS80031_SLAVE_ID1, ri->rinfo->trans_reg,
575*4882a593Smuzhiyun TPS80031_TRANS_ACTIVE_ON | TPS80031_TRANS_SLEEP_OFF |
576*4882a593Smuzhiyun TPS80031_TRANS_OFF_OFF, TPS80031_TRANS_ACTIVE_MASK |
577*4882a593Smuzhiyun TPS80031_TRANS_SLEEP_MASK | TPS80031_TRANS_OFF_MASK);
578*4882a593Smuzhiyun if (ret < 0) {
579*4882a593Smuzhiyun dev_err(ri->dev, "trans reg update failed, e %d\n", ret);
580*4882a593Smuzhiyun return ret;
581*4882a593Smuzhiyun }
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun return ret;
584*4882a593Smuzhiyun }
585*4882a593Smuzhiyun
check_smps_mode_mult(struct device * parent,struct tps80031_regulator * ri)586*4882a593Smuzhiyun static int check_smps_mode_mult(struct device *parent,
587*4882a593Smuzhiyun struct tps80031_regulator *ri)
588*4882a593Smuzhiyun {
589*4882a593Smuzhiyun int mult_offset;
590*4882a593Smuzhiyun int ret;
591*4882a593Smuzhiyun u8 smps_offset;
592*4882a593Smuzhiyun u8 smps_mult;
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun ret = tps80031_read(parent, TPS80031_SLAVE_ID1,
595*4882a593Smuzhiyun TPS80031_SMPS_OFFSET, &smps_offset);
596*4882a593Smuzhiyun if (ret < 0) {
597*4882a593Smuzhiyun dev_err(parent, "Error in reading smps offset register\n");
598*4882a593Smuzhiyun return ret;
599*4882a593Smuzhiyun }
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun ret = tps80031_read(parent, TPS80031_SLAVE_ID1,
602*4882a593Smuzhiyun TPS80031_SMPS_MULT, &smps_mult);
603*4882a593Smuzhiyun if (ret < 0) {
604*4882a593Smuzhiyun dev_err(parent, "Error in reading smps mult register\n");
605*4882a593Smuzhiyun return ret;
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun switch (ri->rinfo->desc.id) {
609*4882a593Smuzhiyun case TPS80031_REGULATOR_VIO:
610*4882a593Smuzhiyun mult_offset = SMPS_MULTOFFSET_VIO;
611*4882a593Smuzhiyun break;
612*4882a593Smuzhiyun case TPS80031_REGULATOR_SMPS1:
613*4882a593Smuzhiyun mult_offset = SMPS_MULTOFFSET_SMPS1;
614*4882a593Smuzhiyun break;
615*4882a593Smuzhiyun case TPS80031_REGULATOR_SMPS2:
616*4882a593Smuzhiyun mult_offset = SMPS_MULTOFFSET_SMPS2;
617*4882a593Smuzhiyun break;
618*4882a593Smuzhiyun case TPS80031_REGULATOR_SMPS3:
619*4882a593Smuzhiyun mult_offset = SMPS_MULTOFFSET_SMPS3;
620*4882a593Smuzhiyun break;
621*4882a593Smuzhiyun case TPS80031_REGULATOR_SMPS4:
622*4882a593Smuzhiyun mult_offset = SMPS_MULTOFFSET_SMPS4;
623*4882a593Smuzhiyun break;
624*4882a593Smuzhiyun case TPS80031_REGULATOR_LDO2:
625*4882a593Smuzhiyun ri->device_flags = smps_mult & BIT(5) ? TRACK_MODE_ENABLE : 0;
626*4882a593Smuzhiyun /* TRACK mode the ldo2 varies from 600mV to 1300mV */
627*4882a593Smuzhiyun if (ri->device_flags & TRACK_MODE_ENABLE) {
628*4882a593Smuzhiyun ri->rinfo->desc.min_uV = 600000;
629*4882a593Smuzhiyun ri->rinfo->desc.uV_step = 12500;
630*4882a593Smuzhiyun ri->rinfo->desc.n_voltages = 57;
631*4882a593Smuzhiyun ri->rinfo->desc.vsel_mask = LDO_TRACK_VSEL_MASK;
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun return 0;
634*4882a593Smuzhiyun default:
635*4882a593Smuzhiyun return 0;
636*4882a593Smuzhiyun }
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun ri->device_flags = (smps_offset & mult_offset) ? DCDC_OFFSET_EN : 0;
639*4882a593Smuzhiyun ri->device_flags |= (smps_mult & mult_offset) ? DCDC_EXTENDED_EN : 0;
640*4882a593Smuzhiyun switch (ri->device_flags) {
641*4882a593Smuzhiyun case 0:
642*4882a593Smuzhiyun ri->rinfo->desc.min_uV = 607700;
643*4882a593Smuzhiyun ri->rinfo->desc.uV_step = 12660;
644*4882a593Smuzhiyun break;
645*4882a593Smuzhiyun case DCDC_OFFSET_EN:
646*4882a593Smuzhiyun ri->rinfo->desc.min_uV = 700000;
647*4882a593Smuzhiyun ri->rinfo->desc.uV_step = 12500;
648*4882a593Smuzhiyun break;
649*4882a593Smuzhiyun case DCDC_EXTENDED_EN:
650*4882a593Smuzhiyun ri->rinfo->desc.min_uV = 1852000;
651*4882a593Smuzhiyun ri->rinfo->desc.uV_step = 38600;
652*4882a593Smuzhiyun break;
653*4882a593Smuzhiyun case DCDC_OFFSET_EN | DCDC_EXTENDED_EN:
654*4882a593Smuzhiyun ri->rinfo->desc.min_uV = 2161000;
655*4882a593Smuzhiyun ri->rinfo->desc.uV_step = 38600;
656*4882a593Smuzhiyun break;
657*4882a593Smuzhiyun }
658*4882a593Smuzhiyun return 0;
659*4882a593Smuzhiyun }
660*4882a593Smuzhiyun
tps80031_regulator_probe(struct platform_device * pdev)661*4882a593Smuzhiyun static int tps80031_regulator_probe(struct platform_device *pdev)
662*4882a593Smuzhiyun {
663*4882a593Smuzhiyun struct tps80031_platform_data *pdata;
664*4882a593Smuzhiyun struct tps80031_regulator_platform_data *tps_pdata;
665*4882a593Smuzhiyun struct tps80031_regulator *ri;
666*4882a593Smuzhiyun struct tps80031_regulator *pmic;
667*4882a593Smuzhiyun struct regulator_dev *rdev;
668*4882a593Smuzhiyun struct regulator_config config = { };
669*4882a593Smuzhiyun struct tps80031 *tps80031_mfd = dev_get_drvdata(pdev->dev.parent);
670*4882a593Smuzhiyun int ret;
671*4882a593Smuzhiyun int num;
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun pdata = dev_get_platdata(pdev->dev.parent);
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun if (!pdata) {
676*4882a593Smuzhiyun dev_err(&pdev->dev, "No platform data\n");
677*4882a593Smuzhiyun return -EINVAL;
678*4882a593Smuzhiyun }
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun pmic = devm_kcalloc(&pdev->dev,
681*4882a593Smuzhiyun TPS80031_REGULATOR_MAX, sizeof(*pmic), GFP_KERNEL);
682*4882a593Smuzhiyun if (!pmic)
683*4882a593Smuzhiyun return -ENOMEM;
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun for (num = 0; num < TPS80031_REGULATOR_MAX; ++num) {
686*4882a593Smuzhiyun tps_pdata = pdata->regulator_pdata[num];
687*4882a593Smuzhiyun ri = &pmic[num];
688*4882a593Smuzhiyun ri->rinfo = &tps80031_rinfo[num];
689*4882a593Smuzhiyun ri->dev = &pdev->dev;
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun check_smps_mode_mult(pdev->dev.parent, ri);
692*4882a593Smuzhiyun config.dev = &pdev->dev;
693*4882a593Smuzhiyun config.init_data = NULL;
694*4882a593Smuzhiyun config.driver_data = ri;
695*4882a593Smuzhiyun config.regmap = tps80031_mfd->regmap[ri->rinfo->volt_id];
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun if (tps_pdata) {
698*4882a593Smuzhiyun config.init_data = tps_pdata->reg_init_data;
699*4882a593Smuzhiyun ri->config_flags = tps_pdata->config_flags;
700*4882a593Smuzhiyun ri->ext_ctrl_flag = tps_pdata->ext_ctrl_flag;
701*4882a593Smuzhiyun ret = tps80031_regulator_config(pdev->dev.parent,
702*4882a593Smuzhiyun ri, tps_pdata);
703*4882a593Smuzhiyun if (ret < 0) {
704*4882a593Smuzhiyun dev_err(&pdev->dev,
705*4882a593Smuzhiyun "regulator config failed, e %d\n", ret);
706*4882a593Smuzhiyun return ret;
707*4882a593Smuzhiyun }
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun ret = tps80031_power_req_config(pdev->dev.parent,
710*4882a593Smuzhiyun ri, tps_pdata);
711*4882a593Smuzhiyun if (ret < 0) {
712*4882a593Smuzhiyun dev_err(&pdev->dev,
713*4882a593Smuzhiyun "pwr_req config failed, err %d\n", ret);
714*4882a593Smuzhiyun return ret;
715*4882a593Smuzhiyun }
716*4882a593Smuzhiyun }
717*4882a593Smuzhiyun rdev = devm_regulator_register(&pdev->dev, &ri->rinfo->desc,
718*4882a593Smuzhiyun &config);
719*4882a593Smuzhiyun if (IS_ERR(rdev)) {
720*4882a593Smuzhiyun dev_err(&pdev->dev,
721*4882a593Smuzhiyun "register regulator failed %s\n",
722*4882a593Smuzhiyun ri->rinfo->desc.name);
723*4882a593Smuzhiyun return PTR_ERR(rdev);
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun }
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun platform_set_drvdata(pdev, pmic);
728*4882a593Smuzhiyun return 0;
729*4882a593Smuzhiyun }
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun static struct platform_driver tps80031_regulator_driver = {
732*4882a593Smuzhiyun .driver = {
733*4882a593Smuzhiyun .name = "tps80031-pmic",
734*4882a593Smuzhiyun },
735*4882a593Smuzhiyun .probe = tps80031_regulator_probe,
736*4882a593Smuzhiyun };
737*4882a593Smuzhiyun
tps80031_regulator_init(void)738*4882a593Smuzhiyun static int __init tps80031_regulator_init(void)
739*4882a593Smuzhiyun {
740*4882a593Smuzhiyun return platform_driver_register(&tps80031_regulator_driver);
741*4882a593Smuzhiyun }
742*4882a593Smuzhiyun subsys_initcall(tps80031_regulator_init);
743*4882a593Smuzhiyun
tps80031_regulator_exit(void)744*4882a593Smuzhiyun static void __exit tps80031_regulator_exit(void)
745*4882a593Smuzhiyun {
746*4882a593Smuzhiyun platform_driver_unregister(&tps80031_regulator_driver);
747*4882a593Smuzhiyun }
748*4882a593Smuzhiyun module_exit(tps80031_regulator_exit);
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun MODULE_ALIAS("platform:tps80031-regulator");
751*4882a593Smuzhiyun MODULE_DESCRIPTION("Regulator Driver for TI TPS80031/TPS80032 PMIC");
752*4882a593Smuzhiyun MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
753*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
754