1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * tps65218-regulator.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Regulator driver for TPS65218 PMIC
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
9*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License version 2 as
10*4882a593Smuzhiyun * published by the Free Software Foundation.
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13*4882a593Smuzhiyun * kind, whether expressed or implied; without even the implied warranty
14*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15*4882a593Smuzhiyun * GNU General Public License version 2 for more details.
16*4882a593Smuzhiyun */
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <linux/kernel.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <linux/device.h>
21*4882a593Smuzhiyun #include <linux/init.h>
22*4882a593Smuzhiyun #include <linux/err.h>
23*4882a593Smuzhiyun #include <linux/platform_device.h>
24*4882a593Smuzhiyun #include <linux/of_device.h>
25*4882a593Smuzhiyun #include <linux/regmap.h>
26*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
27*4882a593Smuzhiyun #include <linux/regulator/driver.h>
28*4882a593Smuzhiyun #include <linux/regulator/machine.h>
29*4882a593Smuzhiyun #include <linux/mfd/tps65218.h>
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define TPS65218_REGULATOR(_name, _of, _id, _type, _ops, _n, _vr, _vm, _er, \
32*4882a593Smuzhiyun _em, _cr, _cm, _lr, _nlr, _delay, _fuv, _sr, _sm, \
33*4882a593Smuzhiyun _ct, _ncl) \
34*4882a593Smuzhiyun { \
35*4882a593Smuzhiyun .name = _name, \
36*4882a593Smuzhiyun .of_match = _of, \
37*4882a593Smuzhiyun .id = _id, \
38*4882a593Smuzhiyun .ops = &_ops, \
39*4882a593Smuzhiyun .n_voltages = _n, \
40*4882a593Smuzhiyun .type = _type, \
41*4882a593Smuzhiyun .owner = THIS_MODULE, \
42*4882a593Smuzhiyun .vsel_reg = _vr, \
43*4882a593Smuzhiyun .vsel_mask = _vm, \
44*4882a593Smuzhiyun .csel_reg = _cr, \
45*4882a593Smuzhiyun .csel_mask = _cm, \
46*4882a593Smuzhiyun .curr_table = _ct, \
47*4882a593Smuzhiyun .n_current_limits = _ncl, \
48*4882a593Smuzhiyun .enable_reg = _er, \
49*4882a593Smuzhiyun .enable_mask = _em, \
50*4882a593Smuzhiyun .volt_table = NULL, \
51*4882a593Smuzhiyun .linear_ranges = _lr, \
52*4882a593Smuzhiyun .n_linear_ranges = _nlr, \
53*4882a593Smuzhiyun .ramp_delay = _delay, \
54*4882a593Smuzhiyun .fixed_uV = _fuv, \
55*4882a593Smuzhiyun .bypass_reg = _sr, \
56*4882a593Smuzhiyun .bypass_mask = _sm, \
57*4882a593Smuzhiyun } \
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static const struct linear_range dcdc1_dcdc2_ranges[] = {
60*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(850000, 0x0, 0x32, 10000),
61*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1375000, 0x33, 0x3f, 25000),
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun static const struct linear_range ldo1_dcdc3_ranges[] = {
65*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(900000, 0x0, 0x1a, 25000),
66*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1600000, 0x1b, 0x3f, 50000),
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun static const struct linear_range dcdc4_ranges[] = {
70*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1175000, 0x0, 0xf, 25000),
71*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1600000, 0x10, 0x34, 50000),
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun
tps65218_pmic_set_voltage_sel(struct regulator_dev * dev,unsigned selector)74*4882a593Smuzhiyun static int tps65218_pmic_set_voltage_sel(struct regulator_dev *dev,
75*4882a593Smuzhiyun unsigned selector)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun int ret;
78*4882a593Smuzhiyun struct tps65218 *tps = rdev_get_drvdata(dev);
79*4882a593Smuzhiyun unsigned int rid = rdev_get_id(dev);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* Set the voltage based on vsel value and write protect level is 2 */
82*4882a593Smuzhiyun ret = tps65218_set_bits(tps, dev->desc->vsel_reg, dev->desc->vsel_mask,
83*4882a593Smuzhiyun selector, TPS65218_PROTECT_L1);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* Set GO bit for DCDC1/2 to initiate voltage transistion */
86*4882a593Smuzhiyun switch (rid) {
87*4882a593Smuzhiyun case TPS65218_DCDC_1:
88*4882a593Smuzhiyun case TPS65218_DCDC_2:
89*4882a593Smuzhiyun ret = tps65218_set_bits(tps, TPS65218_REG_CONTRL_SLEW_RATE,
90*4882a593Smuzhiyun TPS65218_SLEW_RATE_GO,
91*4882a593Smuzhiyun TPS65218_SLEW_RATE_GO,
92*4882a593Smuzhiyun TPS65218_PROTECT_L1);
93*4882a593Smuzhiyun break;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return ret;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
tps65218_pmic_enable(struct regulator_dev * dev)99*4882a593Smuzhiyun static int tps65218_pmic_enable(struct regulator_dev *dev)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun struct tps65218 *tps = rdev_get_drvdata(dev);
102*4882a593Smuzhiyun int rid = rdev_get_id(dev);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun if (rid < TPS65218_DCDC_1 || rid > TPS65218_LDO_1)
105*4882a593Smuzhiyun return -EINVAL;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* Enable the regulator and password protection is level 1 */
108*4882a593Smuzhiyun return tps65218_set_bits(tps, dev->desc->enable_reg,
109*4882a593Smuzhiyun dev->desc->enable_mask, dev->desc->enable_mask,
110*4882a593Smuzhiyun TPS65218_PROTECT_L1);
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
tps65218_pmic_disable(struct regulator_dev * dev)113*4882a593Smuzhiyun static int tps65218_pmic_disable(struct regulator_dev *dev)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun struct tps65218 *tps = rdev_get_drvdata(dev);
116*4882a593Smuzhiyun int rid = rdev_get_id(dev);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun if (rid < TPS65218_DCDC_1 || rid > TPS65218_LDO_1)
119*4882a593Smuzhiyun return -EINVAL;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /* Disable the regulator and password protection is level 1 */
122*4882a593Smuzhiyun return tps65218_clear_bits(tps, dev->desc->enable_reg,
123*4882a593Smuzhiyun dev->desc->enable_mask, TPS65218_PROTECT_L1);
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
tps65218_pmic_set_suspend_enable(struct regulator_dev * dev)126*4882a593Smuzhiyun static int tps65218_pmic_set_suspend_enable(struct regulator_dev *dev)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun struct tps65218 *tps = rdev_get_drvdata(dev);
129*4882a593Smuzhiyun unsigned int rid = rdev_get_id(dev);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun if (rid > TPS65218_LDO_1)
132*4882a593Smuzhiyun return -EINVAL;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun return tps65218_clear_bits(tps, dev->desc->bypass_reg,
135*4882a593Smuzhiyun dev->desc->bypass_mask,
136*4882a593Smuzhiyun TPS65218_PROTECT_L1);
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
tps65218_pmic_set_suspend_disable(struct regulator_dev * dev)139*4882a593Smuzhiyun static int tps65218_pmic_set_suspend_disable(struct regulator_dev *dev)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun struct tps65218 *tps = rdev_get_drvdata(dev);
142*4882a593Smuzhiyun unsigned int rid = rdev_get_id(dev);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun if (rid > TPS65218_LDO_1)
145*4882a593Smuzhiyun return -EINVAL;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun /*
148*4882a593Smuzhiyun * Certain revisions of TPS65218 will need to have DCDC3 regulator
149*4882a593Smuzhiyun * enabled always, otherwise an immediate system reboot will occur
150*4882a593Smuzhiyun * during poweroff.
151*4882a593Smuzhiyun */
152*4882a593Smuzhiyun if (rid == TPS65218_DCDC_3 && tps->rev == TPS65218_REV_2_1)
153*4882a593Smuzhiyun return 0;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun if (!tps->strobes[rid]) {
156*4882a593Smuzhiyun if (rid == TPS65218_DCDC_3)
157*4882a593Smuzhiyun tps->strobes[rid] = 3;
158*4882a593Smuzhiyun else
159*4882a593Smuzhiyun return -EINVAL;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun return tps65218_set_bits(tps, dev->desc->bypass_reg,
163*4882a593Smuzhiyun dev->desc->bypass_mask,
164*4882a593Smuzhiyun tps->strobes[rid], TPS65218_PROTECT_L1);
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun /* Operations permitted on DCDC1, DCDC2 */
168*4882a593Smuzhiyun static const struct regulator_ops tps65218_dcdc12_ops = {
169*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
170*4882a593Smuzhiyun .enable = tps65218_pmic_enable,
171*4882a593Smuzhiyun .disable = tps65218_pmic_disable,
172*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
173*4882a593Smuzhiyun .set_voltage_sel = tps65218_pmic_set_voltage_sel,
174*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
175*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
176*4882a593Smuzhiyun .set_voltage_time_sel = regulator_set_voltage_time_sel,
177*4882a593Smuzhiyun .set_suspend_enable = tps65218_pmic_set_suspend_enable,
178*4882a593Smuzhiyun .set_suspend_disable = tps65218_pmic_set_suspend_disable,
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun /* Operations permitted on DCDC3, DCDC4 and LDO1 */
182*4882a593Smuzhiyun static const struct regulator_ops tps65218_ldo1_dcdc34_ops = {
183*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
184*4882a593Smuzhiyun .enable = tps65218_pmic_enable,
185*4882a593Smuzhiyun .disable = tps65218_pmic_disable,
186*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
187*4882a593Smuzhiyun .set_voltage_sel = tps65218_pmic_set_voltage_sel,
188*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
189*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
190*4882a593Smuzhiyun .set_suspend_enable = tps65218_pmic_set_suspend_enable,
191*4882a593Smuzhiyun .set_suspend_disable = tps65218_pmic_set_suspend_disable,
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun static const unsigned int ls3_currents[] = { 100000, 200000, 500000, 1000000 };
195*4882a593Smuzhiyun
tps65218_pmic_set_input_current_lim(struct regulator_dev * dev,int lim_uA)196*4882a593Smuzhiyun static int tps65218_pmic_set_input_current_lim(struct regulator_dev *dev,
197*4882a593Smuzhiyun int lim_uA)
198*4882a593Smuzhiyun {
199*4882a593Smuzhiyun unsigned int index = 0;
200*4882a593Smuzhiyun unsigned int num_currents = ARRAY_SIZE(ls3_currents);
201*4882a593Smuzhiyun struct tps65218 *tps = rdev_get_drvdata(dev);
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun while (index < num_currents && ls3_currents[index] != lim_uA)
204*4882a593Smuzhiyun index++;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun if (index == num_currents)
207*4882a593Smuzhiyun return -EINVAL;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun return tps65218_set_bits(tps, dev->desc->csel_reg, dev->desc->csel_mask,
210*4882a593Smuzhiyun index << __builtin_ctz(dev->desc->csel_mask),
211*4882a593Smuzhiyun TPS65218_PROTECT_L1);
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
tps65218_pmic_set_current_limit(struct regulator_dev * dev,int min_uA,int max_uA)214*4882a593Smuzhiyun static int tps65218_pmic_set_current_limit(struct regulator_dev *dev,
215*4882a593Smuzhiyun int min_uA, int max_uA)
216*4882a593Smuzhiyun {
217*4882a593Smuzhiyun int index = 0;
218*4882a593Smuzhiyun unsigned int num_currents = ARRAY_SIZE(ls3_currents);
219*4882a593Smuzhiyun struct tps65218 *tps = rdev_get_drvdata(dev);
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun while (index < num_currents && ls3_currents[index] <= max_uA)
222*4882a593Smuzhiyun index++;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun index--;
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun if (index < 0 || ls3_currents[index] < min_uA)
227*4882a593Smuzhiyun return -EINVAL;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun return tps65218_set_bits(tps, dev->desc->csel_reg, dev->desc->csel_mask,
230*4882a593Smuzhiyun index << __builtin_ctz(dev->desc->csel_mask),
231*4882a593Smuzhiyun TPS65218_PROTECT_L1);
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun static const struct regulator_ops tps65218_ls23_ops = {
235*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
236*4882a593Smuzhiyun .enable = tps65218_pmic_enable,
237*4882a593Smuzhiyun .disable = tps65218_pmic_disable,
238*4882a593Smuzhiyun .set_input_current_limit = tps65218_pmic_set_input_current_lim,
239*4882a593Smuzhiyun .set_current_limit = tps65218_pmic_set_current_limit,
240*4882a593Smuzhiyun .get_current_limit = regulator_get_current_limit_regmap,
241*4882a593Smuzhiyun };
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun /* Operations permitted on DCDC5, DCDC6 */
244*4882a593Smuzhiyun static const struct regulator_ops tps65218_dcdc56_pmic_ops = {
245*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
246*4882a593Smuzhiyun .enable = tps65218_pmic_enable,
247*4882a593Smuzhiyun .disable = tps65218_pmic_disable,
248*4882a593Smuzhiyun .set_suspend_enable = tps65218_pmic_set_suspend_enable,
249*4882a593Smuzhiyun .set_suspend_disable = tps65218_pmic_set_suspend_disable,
250*4882a593Smuzhiyun };
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun static const struct regulator_desc regulators[] = {
253*4882a593Smuzhiyun TPS65218_REGULATOR("DCDC1", "regulator-dcdc1", TPS65218_DCDC_1,
254*4882a593Smuzhiyun REGULATOR_VOLTAGE, tps65218_dcdc12_ops, 64,
255*4882a593Smuzhiyun TPS65218_REG_CONTROL_DCDC1,
256*4882a593Smuzhiyun TPS65218_CONTROL_DCDC1_MASK, TPS65218_REG_ENABLE1,
257*4882a593Smuzhiyun TPS65218_ENABLE1_DC1_EN, 0, 0, dcdc1_dcdc2_ranges,
258*4882a593Smuzhiyun 2, 4000, 0, TPS65218_REG_SEQ3,
259*4882a593Smuzhiyun TPS65218_SEQ3_DC1_SEQ_MASK, NULL, 0),
260*4882a593Smuzhiyun TPS65218_REGULATOR("DCDC2", "regulator-dcdc2", TPS65218_DCDC_2,
261*4882a593Smuzhiyun REGULATOR_VOLTAGE, tps65218_dcdc12_ops, 64,
262*4882a593Smuzhiyun TPS65218_REG_CONTROL_DCDC2,
263*4882a593Smuzhiyun TPS65218_CONTROL_DCDC2_MASK, TPS65218_REG_ENABLE1,
264*4882a593Smuzhiyun TPS65218_ENABLE1_DC2_EN, 0, 0, dcdc1_dcdc2_ranges,
265*4882a593Smuzhiyun 2, 4000, 0, TPS65218_REG_SEQ3,
266*4882a593Smuzhiyun TPS65218_SEQ3_DC2_SEQ_MASK, NULL, 0),
267*4882a593Smuzhiyun TPS65218_REGULATOR("DCDC3", "regulator-dcdc3", TPS65218_DCDC_3,
268*4882a593Smuzhiyun REGULATOR_VOLTAGE, tps65218_ldo1_dcdc34_ops, 64,
269*4882a593Smuzhiyun TPS65218_REG_CONTROL_DCDC3,
270*4882a593Smuzhiyun TPS65218_CONTROL_DCDC3_MASK, TPS65218_REG_ENABLE1,
271*4882a593Smuzhiyun TPS65218_ENABLE1_DC3_EN, 0, 0, ldo1_dcdc3_ranges, 2,
272*4882a593Smuzhiyun 0, 0, TPS65218_REG_SEQ4, TPS65218_SEQ4_DC3_SEQ_MASK,
273*4882a593Smuzhiyun NULL, 0),
274*4882a593Smuzhiyun TPS65218_REGULATOR("DCDC4", "regulator-dcdc4", TPS65218_DCDC_4,
275*4882a593Smuzhiyun REGULATOR_VOLTAGE, tps65218_ldo1_dcdc34_ops, 53,
276*4882a593Smuzhiyun TPS65218_REG_CONTROL_DCDC4,
277*4882a593Smuzhiyun TPS65218_CONTROL_DCDC4_MASK, TPS65218_REG_ENABLE1,
278*4882a593Smuzhiyun TPS65218_ENABLE1_DC4_EN, 0, 0, dcdc4_ranges, 2,
279*4882a593Smuzhiyun 0, 0, TPS65218_REG_SEQ4, TPS65218_SEQ4_DC4_SEQ_MASK,
280*4882a593Smuzhiyun NULL, 0),
281*4882a593Smuzhiyun TPS65218_REGULATOR("DCDC5", "regulator-dcdc5", TPS65218_DCDC_5,
282*4882a593Smuzhiyun REGULATOR_VOLTAGE, tps65218_dcdc56_pmic_ops, 1, -1,
283*4882a593Smuzhiyun -1, TPS65218_REG_ENABLE1, TPS65218_ENABLE1_DC5_EN, 0,
284*4882a593Smuzhiyun 0, NULL, 0, 0, 1000000, TPS65218_REG_SEQ5,
285*4882a593Smuzhiyun TPS65218_SEQ5_DC5_SEQ_MASK, NULL, 0),
286*4882a593Smuzhiyun TPS65218_REGULATOR("DCDC6", "regulator-dcdc6", TPS65218_DCDC_6,
287*4882a593Smuzhiyun REGULATOR_VOLTAGE, tps65218_dcdc56_pmic_ops, 1, -1,
288*4882a593Smuzhiyun -1, TPS65218_REG_ENABLE1, TPS65218_ENABLE1_DC6_EN, 0,
289*4882a593Smuzhiyun 0, NULL, 0, 0, 1800000, TPS65218_REG_SEQ5,
290*4882a593Smuzhiyun TPS65218_SEQ5_DC6_SEQ_MASK, NULL, 0),
291*4882a593Smuzhiyun TPS65218_REGULATOR("LDO1", "regulator-ldo1", TPS65218_LDO_1,
292*4882a593Smuzhiyun REGULATOR_VOLTAGE, tps65218_ldo1_dcdc34_ops, 64,
293*4882a593Smuzhiyun TPS65218_REG_CONTROL_LDO1,
294*4882a593Smuzhiyun TPS65218_CONTROL_LDO1_MASK, TPS65218_REG_ENABLE2,
295*4882a593Smuzhiyun TPS65218_ENABLE2_LDO1_EN, 0, 0, ldo1_dcdc3_ranges,
296*4882a593Smuzhiyun 2, 0, 0, TPS65218_REG_SEQ6,
297*4882a593Smuzhiyun TPS65218_SEQ6_LDO1_SEQ_MASK, NULL, 0),
298*4882a593Smuzhiyun TPS65218_REGULATOR("LS2", "regulator-ls2", TPS65218_LS_2,
299*4882a593Smuzhiyun REGULATOR_CURRENT, tps65218_ls23_ops, 0, 0, 0,
300*4882a593Smuzhiyun TPS65218_REG_ENABLE2, TPS65218_ENABLE2_LS2_EN,
301*4882a593Smuzhiyun TPS65218_REG_CONFIG2, TPS65218_CONFIG2_LS2ILIM_MASK,
302*4882a593Smuzhiyun NULL, 0, 0, 0, 0, 0, ls3_currents,
303*4882a593Smuzhiyun ARRAY_SIZE(ls3_currents)),
304*4882a593Smuzhiyun TPS65218_REGULATOR("LS3", "regulator-ls3", TPS65218_LS_3,
305*4882a593Smuzhiyun REGULATOR_CURRENT, tps65218_ls23_ops, 0, 0, 0,
306*4882a593Smuzhiyun TPS65218_REG_ENABLE2, TPS65218_ENABLE2_LS3_EN,
307*4882a593Smuzhiyun TPS65218_REG_CONFIG2, TPS65218_CONFIG2_LS3ILIM_MASK,
308*4882a593Smuzhiyun NULL, 0, 0, 0, 0, 0, ls3_currents,
309*4882a593Smuzhiyun ARRAY_SIZE(ls3_currents)),
310*4882a593Smuzhiyun };
311*4882a593Smuzhiyun
tps65218_regulator_probe(struct platform_device * pdev)312*4882a593Smuzhiyun static int tps65218_regulator_probe(struct platform_device *pdev)
313*4882a593Smuzhiyun {
314*4882a593Smuzhiyun struct tps65218 *tps = dev_get_drvdata(pdev->dev.parent);
315*4882a593Smuzhiyun struct regulator_dev *rdev;
316*4882a593Smuzhiyun struct regulator_config config = { };
317*4882a593Smuzhiyun int i, ret;
318*4882a593Smuzhiyun unsigned int val;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun config.dev = &pdev->dev;
321*4882a593Smuzhiyun config.dev->of_node = tps->dev->of_node;
322*4882a593Smuzhiyun config.driver_data = tps;
323*4882a593Smuzhiyun config.regmap = tps->regmap;
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun /* Allocate memory for strobes */
326*4882a593Smuzhiyun tps->strobes = devm_kcalloc(&pdev->dev,
327*4882a593Smuzhiyun TPS65218_NUM_REGULATOR, sizeof(u8),
328*4882a593Smuzhiyun GFP_KERNEL);
329*4882a593Smuzhiyun if (!tps->strobes)
330*4882a593Smuzhiyun return -ENOMEM;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(regulators); i++) {
333*4882a593Smuzhiyun rdev = devm_regulator_register(&pdev->dev, ®ulators[i],
334*4882a593Smuzhiyun &config);
335*4882a593Smuzhiyun if (IS_ERR(rdev)) {
336*4882a593Smuzhiyun dev_err(tps->dev, "failed to register %s regulator\n",
337*4882a593Smuzhiyun pdev->name);
338*4882a593Smuzhiyun return PTR_ERR(rdev);
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun ret = regmap_read(tps->regmap, regulators[i].bypass_reg, &val);
342*4882a593Smuzhiyun if (ret)
343*4882a593Smuzhiyun return ret;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun tps->strobes[i] = val & regulators[i].bypass_mask;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun return 0;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun static const struct platform_device_id tps65218_regulator_id_table[] = {
352*4882a593Smuzhiyun { "tps65218-regulator", },
353*4882a593Smuzhiyun { /* sentinel */ }
354*4882a593Smuzhiyun };
355*4882a593Smuzhiyun MODULE_DEVICE_TABLE(platform, tps65218_regulator_id_table);
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun static struct platform_driver tps65218_regulator_driver = {
358*4882a593Smuzhiyun .driver = {
359*4882a593Smuzhiyun .name = "tps65218-pmic",
360*4882a593Smuzhiyun },
361*4882a593Smuzhiyun .probe = tps65218_regulator_probe,
362*4882a593Smuzhiyun .id_table = tps65218_regulator_id_table,
363*4882a593Smuzhiyun };
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun module_platform_driver(tps65218_regulator_driver);
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun MODULE_AUTHOR("J Keerthy <j-keerthy@ti.com>");
368*4882a593Smuzhiyun MODULE_DESCRIPTION("TPS65218 voltage regulator driver");
369*4882a593Smuzhiyun MODULE_ALIAS("platform:tps65218-pmic");
370*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
371