xref: /OK3568_Linux_fs/kernel/drivers/regulator/stm32-vrefbuf.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) STMicroelectronics 2017
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Author: Fabrice Gasnier <fabrice.gasnier@st.com>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/bitfield.h>
9*4882a593Smuzhiyun #include <linux/clk.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/iopoll.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/of_device.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/regulator/driver.h>
16*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
17*4882a593Smuzhiyun #include <linux/pm_runtime.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun /* STM32 VREFBUF registers */
20*4882a593Smuzhiyun #define STM32_VREFBUF_CSR		0x00
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /* STM32 VREFBUF CSR bitfields */
23*4882a593Smuzhiyun #define STM32_VRS			GENMASK(6, 4)
24*4882a593Smuzhiyun #define STM32_VRR			BIT(3)
25*4882a593Smuzhiyun #define STM32_HIZ			BIT(1)
26*4882a593Smuzhiyun #define STM32_ENVR			BIT(0)
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define STM32_VREFBUF_AUTO_SUSPEND_DELAY_MS	10
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun struct stm32_vrefbuf {
31*4882a593Smuzhiyun 	void __iomem *base;
32*4882a593Smuzhiyun 	struct clk *clk;
33*4882a593Smuzhiyun 	struct device *dev;
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun static const unsigned int stm32_vrefbuf_voltages[] = {
37*4882a593Smuzhiyun 	/* Matches resp. VRS = 000b, 001b, 010b, 011b */
38*4882a593Smuzhiyun 	2500000, 2048000, 1800000, 1500000,
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun 
stm32_vrefbuf_enable(struct regulator_dev * rdev)41*4882a593Smuzhiyun static int stm32_vrefbuf_enable(struct regulator_dev *rdev)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun 	struct stm32_vrefbuf *priv = rdev_get_drvdata(rdev);
44*4882a593Smuzhiyun 	u32 val;
45*4882a593Smuzhiyun 	int ret;
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun 	ret = pm_runtime_get_sync(priv->dev);
48*4882a593Smuzhiyun 	if (ret < 0) {
49*4882a593Smuzhiyun 		pm_runtime_put_noidle(priv->dev);
50*4882a593Smuzhiyun 		return ret;
51*4882a593Smuzhiyun 	}
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 	val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
54*4882a593Smuzhiyun 	val = (val & ~STM32_HIZ) | STM32_ENVR;
55*4882a593Smuzhiyun 	writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	/*
58*4882a593Smuzhiyun 	 * Vrefbuf startup time depends on external capacitor: wait here for
59*4882a593Smuzhiyun 	 * VRR to be set. That means output has reached expected value.
60*4882a593Smuzhiyun 	 * ~650us sleep should be enough for caps up to 1.5uF. Use 10ms as
61*4882a593Smuzhiyun 	 * arbitrary timeout.
62*4882a593Smuzhiyun 	 */
63*4882a593Smuzhiyun 	ret = readl_poll_timeout(priv->base + STM32_VREFBUF_CSR, val,
64*4882a593Smuzhiyun 				 val & STM32_VRR, 650, 10000);
65*4882a593Smuzhiyun 	if (ret) {
66*4882a593Smuzhiyun 		dev_err(&rdev->dev, "stm32 vrefbuf timed out!\n");
67*4882a593Smuzhiyun 		val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
68*4882a593Smuzhiyun 		val = (val & ~STM32_ENVR) | STM32_HIZ;
69*4882a593Smuzhiyun 		writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
70*4882a593Smuzhiyun 	}
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	pm_runtime_mark_last_busy(priv->dev);
73*4882a593Smuzhiyun 	pm_runtime_put_autosuspend(priv->dev);
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 	return ret;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun 
stm32_vrefbuf_disable(struct regulator_dev * rdev)78*4882a593Smuzhiyun static int stm32_vrefbuf_disable(struct regulator_dev *rdev)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun 	struct stm32_vrefbuf *priv = rdev_get_drvdata(rdev);
81*4882a593Smuzhiyun 	u32 val;
82*4882a593Smuzhiyun 	int ret;
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	ret = pm_runtime_get_sync(priv->dev);
85*4882a593Smuzhiyun 	if (ret < 0) {
86*4882a593Smuzhiyun 		pm_runtime_put_noidle(priv->dev);
87*4882a593Smuzhiyun 		return ret;
88*4882a593Smuzhiyun 	}
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
91*4882a593Smuzhiyun 	val &= ~STM32_ENVR;
92*4882a593Smuzhiyun 	writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	pm_runtime_mark_last_busy(priv->dev);
95*4882a593Smuzhiyun 	pm_runtime_put_autosuspend(priv->dev);
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	return 0;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun 
stm32_vrefbuf_is_enabled(struct regulator_dev * rdev)100*4882a593Smuzhiyun static int stm32_vrefbuf_is_enabled(struct regulator_dev *rdev)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun 	struct stm32_vrefbuf *priv = rdev_get_drvdata(rdev);
103*4882a593Smuzhiyun 	int ret;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	ret = pm_runtime_get_sync(priv->dev);
106*4882a593Smuzhiyun 	if (ret < 0) {
107*4882a593Smuzhiyun 		pm_runtime_put_noidle(priv->dev);
108*4882a593Smuzhiyun 		return ret;
109*4882a593Smuzhiyun 	}
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	ret = readl_relaxed(priv->base + STM32_VREFBUF_CSR) & STM32_ENVR;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	pm_runtime_mark_last_busy(priv->dev);
114*4882a593Smuzhiyun 	pm_runtime_put_autosuspend(priv->dev);
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	return ret;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun 
stm32_vrefbuf_set_voltage_sel(struct regulator_dev * rdev,unsigned sel)119*4882a593Smuzhiyun static int stm32_vrefbuf_set_voltage_sel(struct regulator_dev *rdev,
120*4882a593Smuzhiyun 					 unsigned sel)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun 	struct stm32_vrefbuf *priv = rdev_get_drvdata(rdev);
123*4882a593Smuzhiyun 	u32 val;
124*4882a593Smuzhiyun 	int ret;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	ret = pm_runtime_get_sync(priv->dev);
127*4882a593Smuzhiyun 	if (ret < 0) {
128*4882a593Smuzhiyun 		pm_runtime_put_noidle(priv->dev);
129*4882a593Smuzhiyun 		return ret;
130*4882a593Smuzhiyun 	}
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
133*4882a593Smuzhiyun 	val = (val & ~STM32_VRS) | FIELD_PREP(STM32_VRS, sel);
134*4882a593Smuzhiyun 	writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	pm_runtime_mark_last_busy(priv->dev);
137*4882a593Smuzhiyun 	pm_runtime_put_autosuspend(priv->dev);
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	return 0;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun 
stm32_vrefbuf_get_voltage_sel(struct regulator_dev * rdev)142*4882a593Smuzhiyun static int stm32_vrefbuf_get_voltage_sel(struct regulator_dev *rdev)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun 	struct stm32_vrefbuf *priv = rdev_get_drvdata(rdev);
145*4882a593Smuzhiyun 	u32 val;
146*4882a593Smuzhiyun 	int ret;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	ret = pm_runtime_get_sync(priv->dev);
149*4882a593Smuzhiyun 	if (ret < 0) {
150*4882a593Smuzhiyun 		pm_runtime_put_noidle(priv->dev);
151*4882a593Smuzhiyun 		return ret;
152*4882a593Smuzhiyun 	}
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
155*4882a593Smuzhiyun 	ret = FIELD_GET(STM32_VRS, val);
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	pm_runtime_mark_last_busy(priv->dev);
158*4882a593Smuzhiyun 	pm_runtime_put_autosuspend(priv->dev);
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	return ret;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun static const struct regulator_ops stm32_vrefbuf_volt_ops = {
164*4882a593Smuzhiyun 	.enable		= stm32_vrefbuf_enable,
165*4882a593Smuzhiyun 	.disable	= stm32_vrefbuf_disable,
166*4882a593Smuzhiyun 	.is_enabled	= stm32_vrefbuf_is_enabled,
167*4882a593Smuzhiyun 	.get_voltage_sel = stm32_vrefbuf_get_voltage_sel,
168*4882a593Smuzhiyun 	.set_voltage_sel = stm32_vrefbuf_set_voltage_sel,
169*4882a593Smuzhiyun 	.list_voltage	= regulator_list_voltage_table,
170*4882a593Smuzhiyun };
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun static const struct regulator_desc stm32_vrefbuf_regu = {
173*4882a593Smuzhiyun 	.name = "vref",
174*4882a593Smuzhiyun 	.supply_name = "vdda",
175*4882a593Smuzhiyun 	.volt_table = stm32_vrefbuf_voltages,
176*4882a593Smuzhiyun 	.n_voltages = ARRAY_SIZE(stm32_vrefbuf_voltages),
177*4882a593Smuzhiyun 	.ops = &stm32_vrefbuf_volt_ops,
178*4882a593Smuzhiyun 	.off_on_delay = 1000,
179*4882a593Smuzhiyun 	.type = REGULATOR_VOLTAGE,
180*4882a593Smuzhiyun 	.owner = THIS_MODULE,
181*4882a593Smuzhiyun };
182*4882a593Smuzhiyun 
stm32_vrefbuf_probe(struct platform_device * pdev)183*4882a593Smuzhiyun static int stm32_vrefbuf_probe(struct platform_device *pdev)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun 	struct stm32_vrefbuf *priv;
186*4882a593Smuzhiyun 	struct regulator_config config = { };
187*4882a593Smuzhiyun 	struct regulator_dev *rdev;
188*4882a593Smuzhiyun 	int ret;
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
191*4882a593Smuzhiyun 	if (!priv)
192*4882a593Smuzhiyun 		return -ENOMEM;
193*4882a593Smuzhiyun 	priv->dev = &pdev->dev;
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	priv->base = devm_platform_ioremap_resource(pdev, 0);
196*4882a593Smuzhiyun 	if (IS_ERR(priv->base))
197*4882a593Smuzhiyun 		return PTR_ERR(priv->base);
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	priv->clk = devm_clk_get(&pdev->dev, NULL);
200*4882a593Smuzhiyun 	if (IS_ERR(priv->clk))
201*4882a593Smuzhiyun 		return PTR_ERR(priv->clk);
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	pm_runtime_get_noresume(&pdev->dev);
204*4882a593Smuzhiyun 	pm_runtime_set_active(&pdev->dev);
205*4882a593Smuzhiyun 	pm_runtime_set_autosuspend_delay(&pdev->dev,
206*4882a593Smuzhiyun 					 STM32_VREFBUF_AUTO_SUSPEND_DELAY_MS);
207*4882a593Smuzhiyun 	pm_runtime_use_autosuspend(&pdev->dev);
208*4882a593Smuzhiyun 	pm_runtime_enable(&pdev->dev);
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	ret = clk_prepare_enable(priv->clk);
211*4882a593Smuzhiyun 	if (ret) {
212*4882a593Smuzhiyun 		dev_err(&pdev->dev, "clk prepare failed with error %d\n", ret);
213*4882a593Smuzhiyun 		goto err_pm_stop;
214*4882a593Smuzhiyun 	}
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	config.dev = &pdev->dev;
217*4882a593Smuzhiyun 	config.driver_data = priv;
218*4882a593Smuzhiyun 	config.of_node = pdev->dev.of_node;
219*4882a593Smuzhiyun 	config.init_data = of_get_regulator_init_data(&pdev->dev,
220*4882a593Smuzhiyun 						      pdev->dev.of_node,
221*4882a593Smuzhiyun 						      &stm32_vrefbuf_regu);
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	rdev = regulator_register(&stm32_vrefbuf_regu, &config);
224*4882a593Smuzhiyun 	if (IS_ERR(rdev)) {
225*4882a593Smuzhiyun 		ret = PTR_ERR(rdev);
226*4882a593Smuzhiyun 		dev_err(&pdev->dev, "register failed with error %d\n", ret);
227*4882a593Smuzhiyun 		goto err_clk_dis;
228*4882a593Smuzhiyun 	}
229*4882a593Smuzhiyun 	platform_set_drvdata(pdev, rdev);
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	pm_runtime_mark_last_busy(&pdev->dev);
232*4882a593Smuzhiyun 	pm_runtime_put_autosuspend(&pdev->dev);
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	return 0;
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun err_clk_dis:
237*4882a593Smuzhiyun 	clk_disable_unprepare(priv->clk);
238*4882a593Smuzhiyun err_pm_stop:
239*4882a593Smuzhiyun 	pm_runtime_disable(&pdev->dev);
240*4882a593Smuzhiyun 	pm_runtime_set_suspended(&pdev->dev);
241*4882a593Smuzhiyun 	pm_runtime_put_noidle(&pdev->dev);
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	return ret;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun 
stm32_vrefbuf_remove(struct platform_device * pdev)246*4882a593Smuzhiyun static int stm32_vrefbuf_remove(struct platform_device *pdev)
247*4882a593Smuzhiyun {
248*4882a593Smuzhiyun 	struct regulator_dev *rdev = platform_get_drvdata(pdev);
249*4882a593Smuzhiyun 	struct stm32_vrefbuf *priv = rdev_get_drvdata(rdev);
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	pm_runtime_get_sync(&pdev->dev);
252*4882a593Smuzhiyun 	regulator_unregister(rdev);
253*4882a593Smuzhiyun 	clk_disable_unprepare(priv->clk);
254*4882a593Smuzhiyun 	pm_runtime_disable(&pdev->dev);
255*4882a593Smuzhiyun 	pm_runtime_set_suspended(&pdev->dev);
256*4882a593Smuzhiyun 	pm_runtime_put_noidle(&pdev->dev);
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 	return 0;
259*4882a593Smuzhiyun };
260*4882a593Smuzhiyun 
stm32_vrefbuf_runtime_suspend(struct device * dev)261*4882a593Smuzhiyun static int __maybe_unused stm32_vrefbuf_runtime_suspend(struct device *dev)
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun 	struct regulator_dev *rdev = dev_get_drvdata(dev);
264*4882a593Smuzhiyun 	struct stm32_vrefbuf *priv = rdev_get_drvdata(rdev);
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	clk_disable_unprepare(priv->clk);
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	return 0;
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun 
stm32_vrefbuf_runtime_resume(struct device * dev)271*4882a593Smuzhiyun static int __maybe_unused stm32_vrefbuf_runtime_resume(struct device *dev)
272*4882a593Smuzhiyun {
273*4882a593Smuzhiyun 	struct regulator_dev *rdev = dev_get_drvdata(dev);
274*4882a593Smuzhiyun 	struct stm32_vrefbuf *priv = rdev_get_drvdata(rdev);
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	return clk_prepare_enable(priv->clk);
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun static const struct dev_pm_ops stm32_vrefbuf_pm_ops = {
280*4882a593Smuzhiyun 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
281*4882a593Smuzhiyun 				pm_runtime_force_resume)
282*4882a593Smuzhiyun 	SET_RUNTIME_PM_OPS(stm32_vrefbuf_runtime_suspend,
283*4882a593Smuzhiyun 			   stm32_vrefbuf_runtime_resume,
284*4882a593Smuzhiyun 			   NULL)
285*4882a593Smuzhiyun };
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun static const struct of_device_id __maybe_unused stm32_vrefbuf_of_match[] = {
288*4882a593Smuzhiyun 	{ .compatible = "st,stm32-vrefbuf", },
289*4882a593Smuzhiyun 	{},
290*4882a593Smuzhiyun };
291*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, stm32_vrefbuf_of_match);
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun static struct platform_driver stm32_vrefbuf_driver = {
294*4882a593Smuzhiyun 	.probe = stm32_vrefbuf_probe,
295*4882a593Smuzhiyun 	.remove = stm32_vrefbuf_remove,
296*4882a593Smuzhiyun 	.driver = {
297*4882a593Smuzhiyun 		.name  = "stm32-vrefbuf",
298*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(stm32_vrefbuf_of_match),
299*4882a593Smuzhiyun 		.pm = &stm32_vrefbuf_pm_ops,
300*4882a593Smuzhiyun 	},
301*4882a593Smuzhiyun };
302*4882a593Smuzhiyun module_platform_driver(stm32_vrefbuf_driver);
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
305*4882a593Smuzhiyun MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
306*4882a593Smuzhiyun MODULE_DESCRIPTION("STMicroelectronics STM32 VREFBUF driver");
307*4882a593Smuzhiyun MODULE_ALIAS("platform:stm32-vrefbuf");
308