1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // Copyright (C) STMicroelectronics 2019
3*4882a593Smuzhiyun // Authors: Gabriel Fernandez <gabriel.fernandez@st.com>
4*4882a593Smuzhiyun // Pascal Paillet <p.paillet@st.com>.
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/io.h>
7*4882a593Smuzhiyun #include <linux/iopoll.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/of_address.h>
10*4882a593Smuzhiyun #include <linux/of_device.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/regulator/driver.h>
13*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /*
16*4882a593Smuzhiyun * Registers description
17*4882a593Smuzhiyun */
18*4882a593Smuzhiyun #define REG_PWR_CR3 0x0C
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define USB_3_3_EN BIT(24)
21*4882a593Smuzhiyun #define USB_3_3_RDY BIT(26)
22*4882a593Smuzhiyun #define REG_1_8_EN BIT(28)
23*4882a593Smuzhiyun #define REG_1_8_RDY BIT(29)
24*4882a593Smuzhiyun #define REG_1_1_EN BIT(30)
25*4882a593Smuzhiyun #define REG_1_1_RDY BIT(31)
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* list of supported regulators */
28*4882a593Smuzhiyun enum {
29*4882a593Smuzhiyun PWR_REG11,
30*4882a593Smuzhiyun PWR_REG18,
31*4882a593Smuzhiyun PWR_USB33,
32*4882a593Smuzhiyun STM32PWR_REG_NUM_REGS
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static u32 ready_mask_table[STM32PWR_REG_NUM_REGS] = {
36*4882a593Smuzhiyun [PWR_REG11] = REG_1_1_RDY,
37*4882a593Smuzhiyun [PWR_REG18] = REG_1_8_RDY,
38*4882a593Smuzhiyun [PWR_USB33] = USB_3_3_RDY,
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun struct stm32_pwr_reg {
42*4882a593Smuzhiyun void __iomem *base;
43*4882a593Smuzhiyun u32 ready_mask;
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
stm32_pwr_reg_is_ready(struct regulator_dev * rdev)46*4882a593Smuzhiyun static int stm32_pwr_reg_is_ready(struct regulator_dev *rdev)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
49*4882a593Smuzhiyun u32 val;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun val = readl_relaxed(priv->base + REG_PWR_CR3);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun return (val & priv->ready_mask);
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
stm32_pwr_reg_is_enabled(struct regulator_dev * rdev)56*4882a593Smuzhiyun static int stm32_pwr_reg_is_enabled(struct regulator_dev *rdev)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
59*4882a593Smuzhiyun u32 val;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun val = readl_relaxed(priv->base + REG_PWR_CR3);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun return (val & rdev->desc->enable_mask);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
stm32_pwr_reg_enable(struct regulator_dev * rdev)66*4882a593Smuzhiyun static int stm32_pwr_reg_enable(struct regulator_dev *rdev)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
69*4882a593Smuzhiyun int ret;
70*4882a593Smuzhiyun u32 val;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun val = readl_relaxed(priv->base + REG_PWR_CR3);
73*4882a593Smuzhiyun val |= rdev->desc->enable_mask;
74*4882a593Smuzhiyun writel_relaxed(val, priv->base + REG_PWR_CR3);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /* use an arbitrary timeout of 20ms */
77*4882a593Smuzhiyun ret = readx_poll_timeout(stm32_pwr_reg_is_ready, rdev, val, val,
78*4882a593Smuzhiyun 100, 20 * 1000);
79*4882a593Smuzhiyun if (ret)
80*4882a593Smuzhiyun dev_err(&rdev->dev, "regulator enable timed out!\n");
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun return ret;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
stm32_pwr_reg_disable(struct regulator_dev * rdev)85*4882a593Smuzhiyun static int stm32_pwr_reg_disable(struct regulator_dev *rdev)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
88*4882a593Smuzhiyun int ret;
89*4882a593Smuzhiyun u32 val;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun val = readl_relaxed(priv->base + REG_PWR_CR3);
92*4882a593Smuzhiyun val &= ~rdev->desc->enable_mask;
93*4882a593Smuzhiyun writel_relaxed(val, priv->base + REG_PWR_CR3);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* use an arbitrary timeout of 20ms */
96*4882a593Smuzhiyun ret = readx_poll_timeout(stm32_pwr_reg_is_ready, rdev, val, !val,
97*4882a593Smuzhiyun 100, 20 * 1000);
98*4882a593Smuzhiyun if (ret)
99*4882a593Smuzhiyun dev_err(&rdev->dev, "regulator disable timed out!\n");
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun return ret;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun static const struct regulator_ops stm32_pwr_reg_ops = {
105*4882a593Smuzhiyun .enable = stm32_pwr_reg_enable,
106*4882a593Smuzhiyun .disable = stm32_pwr_reg_disable,
107*4882a593Smuzhiyun .is_enabled = stm32_pwr_reg_is_enabled,
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun #define PWR_REG(_id, _name, _volt, _en, _supply) \
111*4882a593Smuzhiyun [_id] = { \
112*4882a593Smuzhiyun .id = _id, \
113*4882a593Smuzhiyun .name = _name, \
114*4882a593Smuzhiyun .of_match = of_match_ptr(_name), \
115*4882a593Smuzhiyun .n_voltages = 1, \
116*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
117*4882a593Smuzhiyun .fixed_uV = _volt, \
118*4882a593Smuzhiyun .ops = &stm32_pwr_reg_ops, \
119*4882a593Smuzhiyun .enable_mask = _en, \
120*4882a593Smuzhiyun .owner = THIS_MODULE, \
121*4882a593Smuzhiyun .supply_name = _supply, \
122*4882a593Smuzhiyun } \
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun static const struct regulator_desc stm32_pwr_desc[] = {
125*4882a593Smuzhiyun PWR_REG(PWR_REG11, "reg11", 1100000, REG_1_1_EN, "vdd"),
126*4882a593Smuzhiyun PWR_REG(PWR_REG18, "reg18", 1800000, REG_1_8_EN, "vdd"),
127*4882a593Smuzhiyun PWR_REG(PWR_USB33, "usb33", 3300000, USB_3_3_EN, "vdd_3v3_usbfs"),
128*4882a593Smuzhiyun };
129*4882a593Smuzhiyun
stm32_pwr_regulator_probe(struct platform_device * pdev)130*4882a593Smuzhiyun static int stm32_pwr_regulator_probe(struct platform_device *pdev)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun struct device_node *np = pdev->dev.of_node;
133*4882a593Smuzhiyun struct stm32_pwr_reg *priv;
134*4882a593Smuzhiyun void __iomem *base;
135*4882a593Smuzhiyun struct regulator_dev *rdev;
136*4882a593Smuzhiyun struct regulator_config config = { };
137*4882a593Smuzhiyun int i, ret = 0;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun base = of_iomap(np, 0);
140*4882a593Smuzhiyun if (!base) {
141*4882a593Smuzhiyun dev_err(&pdev->dev, "Unable to map IO memory\n");
142*4882a593Smuzhiyun return -ENOMEM;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun config.dev = &pdev->dev;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun for (i = 0; i < STM32PWR_REG_NUM_REGS; i++) {
148*4882a593Smuzhiyun priv = devm_kzalloc(&pdev->dev, sizeof(struct stm32_pwr_reg),
149*4882a593Smuzhiyun GFP_KERNEL);
150*4882a593Smuzhiyun if (!priv)
151*4882a593Smuzhiyun return -ENOMEM;
152*4882a593Smuzhiyun priv->base = base;
153*4882a593Smuzhiyun priv->ready_mask = ready_mask_table[i];
154*4882a593Smuzhiyun config.driver_data = priv;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun rdev = devm_regulator_register(&pdev->dev,
157*4882a593Smuzhiyun &stm32_pwr_desc[i],
158*4882a593Smuzhiyun &config);
159*4882a593Smuzhiyun if (IS_ERR(rdev)) {
160*4882a593Smuzhiyun ret = PTR_ERR(rdev);
161*4882a593Smuzhiyun dev_err(&pdev->dev,
162*4882a593Smuzhiyun "Failed to register regulator: %d\n", ret);
163*4882a593Smuzhiyun break;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun return ret;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun static const struct of_device_id __maybe_unused stm32_pwr_of_match[] = {
170*4882a593Smuzhiyun { .compatible = "st,stm32mp1,pwr-reg", },
171*4882a593Smuzhiyun {},
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, stm32_pwr_of_match);
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun static struct platform_driver stm32_pwr_driver = {
176*4882a593Smuzhiyun .probe = stm32_pwr_regulator_probe,
177*4882a593Smuzhiyun .driver = {
178*4882a593Smuzhiyun .name = "stm32-pwr-regulator",
179*4882a593Smuzhiyun .of_match_table = of_match_ptr(stm32_pwr_of_match),
180*4882a593Smuzhiyun },
181*4882a593Smuzhiyun };
182*4882a593Smuzhiyun module_platform_driver(stm32_pwr_driver);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun MODULE_DESCRIPTION("STM32MP1 PWR voltage regulator driver");
185*4882a593Smuzhiyun MODULE_AUTHOR("Pascal Paillet <p.paillet@st.com>");
186*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
187