1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * SLG51000 High PSRR, Multi-Output Regulators 4*4882a593Smuzhiyun * Copyright (C) 2019 Dialog Semiconductor 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Author: Eric Jeong <eric.jeong.opensource@diasemi.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __SLG51000_REGISTERS_H__ 10*4882a593Smuzhiyun #define __SLG51000_REGISTERS_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Registers */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define SLG51000_SYSCTL_PATN_ID_B0 0x1105 15*4882a593Smuzhiyun #define SLG51000_SYSCTL_PATN_ID_B1 0x1106 16*4882a593Smuzhiyun #define SLG51000_SYSCTL_PATN_ID_B2 0x1107 17*4882a593Smuzhiyun #define SLG51000_SYSCTL_SYS_CONF_A 0x1109 18*4882a593Smuzhiyun #define SLG51000_SYSCTL_SYS_CONF_D 0x110c 19*4882a593Smuzhiyun #define SLG51000_SYSCTL_MATRIX_CONF_A 0x110d 20*4882a593Smuzhiyun #define SLG51000_SYSCTL_MATRIX_CONF_B 0x110e 21*4882a593Smuzhiyun #define SLG51000_SYSCTL_REFGEN_CONF_C 0x1111 22*4882a593Smuzhiyun #define SLG51000_SYSCTL_UVLO_CONF_A 0x1112 23*4882a593Smuzhiyun #define SLG51000_SYSCTL_FAULT_LOG1 0x1115 24*4882a593Smuzhiyun #define SLG51000_SYSCTL_EVENT 0x1116 25*4882a593Smuzhiyun #define SLG51000_SYSCTL_STATUS 0x1117 26*4882a593Smuzhiyun #define SLG51000_SYSCTL_IRQ_MASK 0x1118 27*4882a593Smuzhiyun #define SLG51000_IO_GPIO1_CONF 0x1500 28*4882a593Smuzhiyun #define SLG51000_IO_GPIO2_CONF 0x1501 29*4882a593Smuzhiyun #define SLG51000_IO_GPIO3_CONF 0x1502 30*4882a593Smuzhiyun #define SLG51000_IO_GPIO4_CONF 0x1503 31*4882a593Smuzhiyun #define SLG51000_IO_GPIO5_CONF 0x1504 32*4882a593Smuzhiyun #define SLG51000_IO_GPIO6_CONF 0x1505 33*4882a593Smuzhiyun #define SLG51000_IO_GPIO_STATUS 0x1506 34*4882a593Smuzhiyun #define SLG51000_LUTARRAY_LUT_VAL_0 0x1600 35*4882a593Smuzhiyun #define SLG51000_LUTARRAY_LUT_VAL_1 0x1601 36*4882a593Smuzhiyun #define SLG51000_LUTARRAY_LUT_VAL_2 0x1602 37*4882a593Smuzhiyun #define SLG51000_LUTARRAY_LUT_VAL_3 0x1603 38*4882a593Smuzhiyun #define SLG51000_LUTARRAY_LUT_VAL_4 0x1604 39*4882a593Smuzhiyun #define SLG51000_LUTARRAY_LUT_VAL_5 0x1605 40*4882a593Smuzhiyun #define SLG51000_LUTARRAY_LUT_VAL_6 0x1606 41*4882a593Smuzhiyun #define SLG51000_LUTARRAY_LUT_VAL_7 0x1607 42*4882a593Smuzhiyun #define SLG51000_LUTARRAY_LUT_VAL_8 0x1608 43*4882a593Smuzhiyun #define SLG51000_LUTARRAY_LUT_VAL_9 0x1609 44*4882a593Smuzhiyun #define SLG51000_LUTARRAY_LUT_VAL_10 0x160a 45*4882a593Smuzhiyun #define SLG51000_LUTARRAY_LUT_VAL_11 0x160b 46*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_0 0x1700 47*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_1 0x1701 48*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_2 0x1702 49*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_3 0x1703 50*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_4 0x1704 51*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_5 0x1705 52*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_6 0x1706 53*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_7 0x1707 54*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_8 0x1708 55*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_9 0x1709 56*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_10 0x170a 57*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_11 0x170b 58*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_12 0x170c 59*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_13 0x170d 60*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_14 0x170e 61*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_15 0x170f 62*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_16 0x1710 63*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_17 0x1711 64*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_18 0x1712 65*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_19 0x1713 66*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_20 0x1714 67*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_21 0x1715 68*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_22 0x1716 69*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_23 0x1717 70*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_24 0x1718 71*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_25 0x1719 72*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_26 0x171a 73*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_27 0x171b 74*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_28 0x171c 75*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_29 0x171d 76*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_30 0x171e 77*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_31 0x171f 78*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_32 0x1720 79*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_33 0x1721 80*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_34 0x1722 81*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_35 0x1723 82*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_36 0x1724 83*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_37 0x1725 84*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_38 0x1726 85*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_39 0x1727 86*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_40 0x1728 87*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_41 0x1729 88*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_42 0x172a 89*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_43 0x172b 90*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_44 0x172c 91*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_45 0x172d 92*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_46 0x172e 93*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_47 0x172f 94*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_48 0x1730 95*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_49 0x1731 96*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_50 0x1732 97*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_51 0x1733 98*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_52 0x1734 99*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_53 0x1735 100*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_54 0x1736 101*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_55 0x1737 102*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_56 0x1738 103*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_57 0x1739 104*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_58 0x173a 105*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_59 0x173b 106*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_60 0x173c 107*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_61 0x173d 108*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_62 0x173e 109*4882a593Smuzhiyun #define SLG51000_MUXARRAY_INPUT_SEL_63 0x173f 110*4882a593Smuzhiyun #define SLG51000_PWRSEQ_RESOURCE_EN_0 0x1900 111*4882a593Smuzhiyun #define SLG51000_PWRSEQ_RESOURCE_EN_1 0x1901 112*4882a593Smuzhiyun #define SLG51000_PWRSEQ_RESOURCE_EN_2 0x1902 113*4882a593Smuzhiyun #define SLG51000_PWRSEQ_RESOURCE_EN_3 0x1903 114*4882a593Smuzhiyun #define SLG51000_PWRSEQ_RESOURCE_EN_4 0x1904 115*4882a593Smuzhiyun #define SLG51000_PWRSEQ_RESOURCE_EN_5 0x1905 116*4882a593Smuzhiyun #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP0 0x1906 117*4882a593Smuzhiyun #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN0 0x1907 118*4882a593Smuzhiyun #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP1 0x1908 119*4882a593Smuzhiyun #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN1 0x1909 120*4882a593Smuzhiyun #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP2 0x190a 121*4882a593Smuzhiyun #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN2 0x190b 122*4882a593Smuzhiyun #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP3 0x190c 123*4882a593Smuzhiyun #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN3 0x190d 124*4882a593Smuzhiyun #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP4 0x190e 125*4882a593Smuzhiyun #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN4 0x190f 126*4882a593Smuzhiyun #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP5 0x1910 127*4882a593Smuzhiyun #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN5 0x1911 128*4882a593Smuzhiyun #define SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_A 0x1912 129*4882a593Smuzhiyun #define SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_B 0x1913 130*4882a593Smuzhiyun #define SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_C 0x1914 131*4882a593Smuzhiyun #define SLG51000_PWRSEQ_INPUT_SENSE_CONF_A 0x1915 132*4882a593Smuzhiyun #define SLG51000_PWRSEQ_INPUT_SENSE_CONF_B 0x1916 133*4882a593Smuzhiyun #define SLG51000_LDO1_VSEL 0x2000 134*4882a593Smuzhiyun #define SLG51000_LDO1_MINV 0x2060 135*4882a593Smuzhiyun #define SLG51000_LDO1_MAXV 0x2061 136*4882a593Smuzhiyun #define SLG51000_LDO1_MISC1 0x2064 137*4882a593Smuzhiyun #define SLG51000_LDO1_VSEL_ACTUAL 0x2065 138*4882a593Smuzhiyun #define SLG51000_LDO1_EVENT 0x20c0 139*4882a593Smuzhiyun #define SLG51000_LDO1_STATUS 0x20c1 140*4882a593Smuzhiyun #define SLG51000_LDO1_IRQ_MASK 0x20c2 141*4882a593Smuzhiyun #define SLG51000_LDO2_VSEL 0x2200 142*4882a593Smuzhiyun #define SLG51000_LDO2_MINV 0x2260 143*4882a593Smuzhiyun #define SLG51000_LDO2_MAXV 0x2261 144*4882a593Smuzhiyun #define SLG51000_LDO2_MISC1 0x2264 145*4882a593Smuzhiyun #define SLG51000_LDO2_VSEL_ACTUAL 0x2265 146*4882a593Smuzhiyun #define SLG51000_LDO2_EVENT 0x22c0 147*4882a593Smuzhiyun #define SLG51000_LDO2_STATUS 0x22c1 148*4882a593Smuzhiyun #define SLG51000_LDO2_IRQ_MASK 0x22c2 149*4882a593Smuzhiyun #define SLG51000_LDO3_VSEL 0x2300 150*4882a593Smuzhiyun #define SLG51000_LDO3_MINV 0x2360 151*4882a593Smuzhiyun #define SLG51000_LDO3_MAXV 0x2361 152*4882a593Smuzhiyun #define SLG51000_LDO3_CONF1 0x2364 153*4882a593Smuzhiyun #define SLG51000_LDO3_CONF2 0x2365 154*4882a593Smuzhiyun #define SLG51000_LDO3_VSEL_ACTUAL 0x2366 155*4882a593Smuzhiyun #define SLG51000_LDO3_EVENT 0x23c0 156*4882a593Smuzhiyun #define SLG51000_LDO3_STATUS 0x23c1 157*4882a593Smuzhiyun #define SLG51000_LDO3_IRQ_MASK 0x23c2 158*4882a593Smuzhiyun #define SLG51000_LDO4_VSEL 0x2500 159*4882a593Smuzhiyun #define SLG51000_LDO4_MINV 0x2560 160*4882a593Smuzhiyun #define SLG51000_LDO4_MAXV 0x2561 161*4882a593Smuzhiyun #define SLG51000_LDO4_CONF1 0x2564 162*4882a593Smuzhiyun #define SLG51000_LDO4_CONF2 0x2565 163*4882a593Smuzhiyun #define SLG51000_LDO4_VSEL_ACTUAL 0x2566 164*4882a593Smuzhiyun #define SLG51000_LDO4_EVENT 0x25c0 165*4882a593Smuzhiyun #define SLG51000_LDO4_STATUS 0x25c1 166*4882a593Smuzhiyun #define SLG51000_LDO4_IRQ_MASK 0x25c2 167*4882a593Smuzhiyun #define SLG51000_LDO5_VSEL 0x2700 168*4882a593Smuzhiyun #define SLG51000_LDO5_MINV 0x2760 169*4882a593Smuzhiyun #define SLG51000_LDO5_MAXV 0x2761 170*4882a593Smuzhiyun #define SLG51000_LDO5_TRIM2 0x2763 171*4882a593Smuzhiyun #define SLG51000_LDO5_CONF1 0x2765 172*4882a593Smuzhiyun #define SLG51000_LDO5_CONF2 0x2766 173*4882a593Smuzhiyun #define SLG51000_LDO5_VSEL_ACTUAL 0x2767 174*4882a593Smuzhiyun #define SLG51000_LDO5_EVENT 0x27c0 175*4882a593Smuzhiyun #define SLG51000_LDO5_STATUS 0x27c1 176*4882a593Smuzhiyun #define SLG51000_LDO5_IRQ_MASK 0x27c2 177*4882a593Smuzhiyun #define SLG51000_LDO6_VSEL 0x2900 178*4882a593Smuzhiyun #define SLG51000_LDO6_MINV 0x2960 179*4882a593Smuzhiyun #define SLG51000_LDO6_MAXV 0x2961 180*4882a593Smuzhiyun #define SLG51000_LDO6_TRIM2 0x2963 181*4882a593Smuzhiyun #define SLG51000_LDO6_CONF1 0x2965 182*4882a593Smuzhiyun #define SLG51000_LDO6_CONF2 0x2966 183*4882a593Smuzhiyun #define SLG51000_LDO6_VSEL_ACTUAL 0x2967 184*4882a593Smuzhiyun #define SLG51000_LDO6_EVENT 0x29c0 185*4882a593Smuzhiyun #define SLG51000_LDO6_STATUS 0x29c1 186*4882a593Smuzhiyun #define SLG51000_LDO6_IRQ_MASK 0x29c2 187*4882a593Smuzhiyun #define SLG51000_LDO7_VSEL 0x3100 188*4882a593Smuzhiyun #define SLG51000_LDO7_MINV 0x3160 189*4882a593Smuzhiyun #define SLG51000_LDO7_MAXV 0x3161 190*4882a593Smuzhiyun #define SLG51000_LDO7_CONF1 0x3164 191*4882a593Smuzhiyun #define SLG51000_LDO7_CONF2 0x3165 192*4882a593Smuzhiyun #define SLG51000_LDO7_VSEL_ACTUAL 0x3166 193*4882a593Smuzhiyun #define SLG51000_LDO7_EVENT 0x31c0 194*4882a593Smuzhiyun #define SLG51000_LDO7_STATUS 0x31c1 195*4882a593Smuzhiyun #define SLG51000_LDO7_IRQ_MASK 0x31c2 196*4882a593Smuzhiyun #define SLG51000_OTP_EVENT 0x782b 197*4882a593Smuzhiyun #define SLG51000_OTP_IRQ_MASK 0x782d 198*4882a593Smuzhiyun #define SLG51000_OTP_LOCK_OTP_PROG 0x78fe 199*4882a593Smuzhiyun #define SLG51000_OTP_LOCK_CTRL 0x78ff 200*4882a593Smuzhiyun #define SLG51000_LOCK_GLOBAL_LOCK_CTRL1 0x8000 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun /* Register Bit Fields */ 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun /* SLG51000_SYSCTL_PATTERN_ID_BYTE0 = 0x1105 */ 205*4882a593Smuzhiyun #define SLG51000_PATTERN_ID_BYTE0_SHIFT 0 206*4882a593Smuzhiyun #define SLG51000_PATTERN_ID_BYTE0_MASK (0xff << 0) 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun /* SLG51000_SYSCTL_PATTERN_ID_BYTE1 = 0x1106 */ 209*4882a593Smuzhiyun #define SLG51000_PATTERN_ID_BYTE1_SHIFT 0 210*4882a593Smuzhiyun #define SLG51000_PATTERN_ID_BYTE1_MASK (0xff << 0) 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun /* SLG51000_SYSCTL_PATTERN_ID_BYTE2 = 0x1107 */ 213*4882a593Smuzhiyun #define SLG51000_PATTERN_ID_BYTE2_SHIFT 0 214*4882a593Smuzhiyun #define SLG51000_PATTERN_ID_BYTE2_MASK (0xff << 0) 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun /* SLG51000_SYSCTL_SYS_CONF_A = 0x1109 */ 217*4882a593Smuzhiyun #define SLG51000_I2C_ADDRESS_SHIFT 0 218*4882a593Smuzhiyun #define SLG51000_I2C_ADDRESS_MASK (0x7f << 0) 219*4882a593Smuzhiyun #define SLG51000_I2C_DISABLE_SHIFT 7 220*4882a593Smuzhiyun #define SLG51000_I2C_DISABLE_MASK (0x01 << 7) 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun /* SLG51000_SYSCTL_SYS_CONF_D = 0x110c */ 223*4882a593Smuzhiyun #define SLG51000_CS_T_DEB_SHIFT 6 224*4882a593Smuzhiyun #define SLG51000_CS_T_DEB_MASK (0x03 << 6) 225*4882a593Smuzhiyun #define SLG51000_I2C_CLR_MODE_SHIFT 5 226*4882a593Smuzhiyun #define SLG51000_I2C_CLR_MODE_MASK (0x01 << 5) 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun /* SLG51000_SYSCTL_MATRIX_CTRL_CONF_A = 0x110d */ 229*4882a593Smuzhiyun #define SLG51000_RESOURCE_CTRL_SHIFT 0 230*4882a593Smuzhiyun #define SLG51000_RESOURCE_CTRL_MASK (0xff << 0) 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun /* SLG51000_SYSCTL_MATRIX_CTRL_CONF_B = 0x110e */ 233*4882a593Smuzhiyun #define SLG51000_MATRIX_EVENT_SENSE_SHIFT 0 234*4882a593Smuzhiyun #define SLG51000_MATRIX_EVENT_SENSE_MASK (0x07 << 0) 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun /* SLG51000_SYSCTL_REFGEN_CONF_C = 0x1111 */ 237*4882a593Smuzhiyun #define SLG51000_REFGEN_SEL_TEMP_WARN_DEBOUNCE_SHIFT 2 238*4882a593Smuzhiyun #define SLG51000_REFGEN_SEL_TEMP_WARN_DEBOUNCE_MASK (0x03 << 2) 239*4882a593Smuzhiyun #define SLG51000_REFGEN_SEL_TEMP_WARN_THR_SHIFT 0 240*4882a593Smuzhiyun #define SLG51000_REFGEN_SEL_TEMP_WARN_THR_MASK (0x03 << 0) 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun /* SLG51000_SYSCTL_UVLO_CONF_A = 0x1112 */ 243*4882a593Smuzhiyun #define SLG51000_VMON_UVLO_SEL_THR_SHIFT 0 244*4882a593Smuzhiyun #define SLG51000_VMON_UVLO_SEL_THR_MASK (0x1f << 0) 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun /* SLG51000_SYSCTL_FAULT_LOG1 = 0x1115 */ 247*4882a593Smuzhiyun #define SLG51000_FLT_POR_SHIFT 5 248*4882a593Smuzhiyun #define SLG51000_FLT_POR_MASK (0x01 << 5) 249*4882a593Smuzhiyun #define SLG51000_FLT_RST_SHIFT 4 250*4882a593Smuzhiyun #define SLG51000_FLT_RST_MASK (0x01 << 4) 251*4882a593Smuzhiyun #define SLG51000_FLT_POWER_SEQ_CRASH_REQ_SHIFT 2 252*4882a593Smuzhiyun #define SLG51000_FLT_POWER_SEQ_CRASH_REQ_MASK (0x01 << 2) 253*4882a593Smuzhiyun #define SLG51000_FLT_OVER_TEMP_SHIFT 1 254*4882a593Smuzhiyun #define SLG51000_FLT_OVER_TEMP_MASK (0x01 << 1) 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun /* SLG51000_SYSCTL_EVENT = 0x1116 */ 257*4882a593Smuzhiyun #define SLG51000_EVT_MATRIX_SHIFT 1 258*4882a593Smuzhiyun #define SLG51000_EVT_MATRIX_MASK (0x01 << 1) 259*4882a593Smuzhiyun #define SLG51000_EVT_HIGH_TEMP_WARN_SHIFT 0 260*4882a593Smuzhiyun #define SLG51000_EVT_HIGH_TEMP_WARN_MASK (0x01 << 0) 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun /* SLG51000_SYSCTL_STATUS = 0x1117 */ 263*4882a593Smuzhiyun #define SLG51000_STA_MATRIX_SHIFT 1 264*4882a593Smuzhiyun #define SLG51000_STA_MATRIX_MASK (0x01 << 1) 265*4882a593Smuzhiyun #define SLG51000_STA_HIGH_TEMP_WARN_SHIFT 0 266*4882a593Smuzhiyun #define SLG51000_STA_HIGH_TEMP_WARN_MASK (0x01 << 0) 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun /* SLG51000_SYSCTL_IRQ_MASK = 0x1118 */ 269*4882a593Smuzhiyun #define SLG51000_IRQ_MATRIX_SHIFT 1 270*4882a593Smuzhiyun #define SLG51000_IRQ_MATRIX_MASK (0x01 << 1) 271*4882a593Smuzhiyun #define SLG51000_IRQ_HIGH_TEMP_WARN_SHIFT 0 272*4882a593Smuzhiyun #define SLG51000_IRQ_HIGH_TEMP_WARN_MASK (0x01 << 0) 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun /* SLG51000_IO_GPIO1_CONF ~ SLG51000_IO_GPIO5_CONF = 275*4882a593Smuzhiyun * 0x1500, 0x1501, 0x1502, 0x1503, 0x1504 276*4882a593Smuzhiyun */ 277*4882a593Smuzhiyun #define SLG51000_GPIO_DIR_SHIFT 7 278*4882a593Smuzhiyun #define SLG51000_GPIO_DIR_MASK (0x01 << 7) 279*4882a593Smuzhiyun #define SLG51000_GPIO_SENS_SHIFT 5 280*4882a593Smuzhiyun #define SLG51000_GPIO_SENS_MASK (0x03 << 5) 281*4882a593Smuzhiyun #define SLG51000_GPIO_INVERT_SHIFT 4 282*4882a593Smuzhiyun #define SLG51000_GPIO_INVERT_MASK (0x01 << 4) 283*4882a593Smuzhiyun #define SLG51000_GPIO_BYP_SHIFT 3 284*4882a593Smuzhiyun #define SLG51000_GPIO_BYP_MASK (0x01 << 3) 285*4882a593Smuzhiyun #define SLG51000_GPIO_T_DEB_SHIFT 1 286*4882a593Smuzhiyun #define SLG51000_GPIO_T_DEB_MASK (0x03 << 1) 287*4882a593Smuzhiyun #define SLG51000_GPIO_LEVEL_SHIFT 0 288*4882a593Smuzhiyun #define SLG51000_GPIO_LEVEL_MASK (0x01 << 0) 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun /* SLG51000_IO_GPIO6_CONF = 0x1505 */ 291*4882a593Smuzhiyun #define SLG51000_GPIO6_SENS_SHIFT 5 292*4882a593Smuzhiyun #define SLG51000_GPIO6_SENS_MASK (0x03 << 5) 293*4882a593Smuzhiyun #define SLG51000_GPIO6_INVERT_SHIFT 4 294*4882a593Smuzhiyun #define SLG51000_GPIO6_INVERT_MASK (0x01 << 4) 295*4882a593Smuzhiyun #define SLG51000_GPIO6_T_DEB_SHIFT 1 296*4882a593Smuzhiyun #define SLG51000_GPIO6_T_DEB_MASK (0x03 << 1) 297*4882a593Smuzhiyun #define SLG51000_GPIO6_LEVEL_SHIFT 0 298*4882a593Smuzhiyun #define SLG51000_GPIO6_LEVEL_MASK (0x01 << 0) 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun /* SLG51000_IO_GPIO_STATUS = 0x1506 */ 301*4882a593Smuzhiyun #define SLG51000_GPIO6_STATUS_SHIFT 5 302*4882a593Smuzhiyun #define SLG51000_GPIO6_STATUS_MASK (0x01 << 5) 303*4882a593Smuzhiyun #define SLG51000_GPIO5_STATUS_SHIFT 4 304*4882a593Smuzhiyun #define SLG51000_GPIO5_STATUS_MASK (0x01 << 4) 305*4882a593Smuzhiyun #define SLG51000_GPIO4_STATUS_SHIFT 3 306*4882a593Smuzhiyun #define SLG51000_GPIO4_STATUS_MASK (0x01 << 3) 307*4882a593Smuzhiyun #define SLG51000_GPIO3_STATUS_SHIFT 2 308*4882a593Smuzhiyun #define SLG51000_GPIO3_STATUS_MASK (0x01 << 2) 309*4882a593Smuzhiyun #define SLG51000_GPIO2_STATUS_SHIFT 1 310*4882a593Smuzhiyun #define SLG51000_GPIO2_STATUS_MASK (0x01 << 1) 311*4882a593Smuzhiyun #define SLG51000_GPIO1_STATUS_SHIFT 0 312*4882a593Smuzhiyun #define SLG51000_GPIO1_STATUS_MASK (0x01 << 0) 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun /* SLG51000_LUTARRAY_LUT_VAL_0 ~ SLG51000_LUTARRAY_LUT_VAL_11 315*4882a593Smuzhiyun * 0x1600, 0x1601, 0x1602, 0x1603, 0x1604, 0x1605, 316*4882a593Smuzhiyun * 0x1606, 0x1607, 0x1608, 0x1609, 0x160a, 0x160b 317*4882a593Smuzhiyun */ 318*4882a593Smuzhiyun #define SLG51000_LUT_VAL_SHIFT 0 319*4882a593Smuzhiyun #define SLG51000_LUT_VAL_MASK (0xff << 0) 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun /* SLG51000_MUXARRAY_INPUT_SEL_0 ~ SLG51000_MUXARRAY_INPUT_SEL_63 322*4882a593Smuzhiyun * 0x1700, 0x1701, 0x1702, 0x1703, 0x1704, 0x1705, 323*4882a593Smuzhiyun * 0x1706, 0x1707, 0x1708, 0x1709, 0x170a, 0x170b, 324*4882a593Smuzhiyun * 0x170c, 0x170d, 0x170e, 0x170f, 0x1710, 0x1711, 325*4882a593Smuzhiyun * 0x1712, 0x1713, 0x1714, 0x1715, 0x1716, 0x1717, 326*4882a593Smuzhiyun * 0x1718, 0x1719, 0x171a, 0x171b, 0x171c, 0x171d, 327*4882a593Smuzhiyun * 0x171e, 0x171f, 0x1720, 0x1721, 0x1722, 0x1723, 328*4882a593Smuzhiyun * 0x1724, 0x1725, 0x1726, 0x1727, 0x1728, 0x1729, 329*4882a593Smuzhiyun * 0x173a, 0x173b, 0x173c, 0x173d, 0x173e, 0x173f, 330*4882a593Smuzhiyun */ 331*4882a593Smuzhiyun #define SLG51000_INPUT_SEL_SHIFT 0 332*4882a593Smuzhiyun #define SLG51000_INPUT_SEL_MASK (0x3f << 0) 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun /* SLG51000_PWRSEQ_RESOURCE_EN_0 ~ SLG51000_PWRSEQ_RESOURCE_EN_5 335*4882a593Smuzhiyun * 0x1900, 0x1901, 0x1902, 0x1903, 0x1904, 0x1905 336*4882a593Smuzhiyun */ 337*4882a593Smuzhiyun #define SLG51000_RESOURCE_EN_DOWN0_SHIFT 4 338*4882a593Smuzhiyun #define SLG51000_RESOURCE_EN_DOWN0_MASK (0x07 << 4) 339*4882a593Smuzhiyun #define SLG51000_RESOURCE_EN_UP0_SHIFT 0 340*4882a593Smuzhiyun #define SLG51000_RESOURCE_EN_UP0_MASK (0x07 << 0) 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun /* SLG51000_PWRSEQ_SLOT_TIME_MIN_UP0 ~ SLG51000_PWRSEQ_SLOT_TIME_MIN_UP5 343*4882a593Smuzhiyun * 0x1906, 0x1908, 0x190a, 0x190c, 0x190e, 0x1910 344*4882a593Smuzhiyun */ 345*4882a593Smuzhiyun #define SLG51000_SLOT_TIME_MIN_UP_SHIFT 0 346*4882a593Smuzhiyun #define SLG51000_SLOT_TIME_MIN_UP_MASK (0xff << 0) 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun /* SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN0 ~ SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN5 349*4882a593Smuzhiyun * 0x1907, 0x1909, 0x190b, 0x190d, 0x190f, 0x1911 350*4882a593Smuzhiyun */ 351*4882a593Smuzhiyun #define SLG51000_SLOT_TIME_MIN_DOWN_SHIFT 0 352*4882a593Smuzhiyun #define SLG51000_SLOT_TIME_MIN_DOWN_MASK (0xff << 0) 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun /* SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_A ~ SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_C 355*4882a593Smuzhiyun * 0x1912, 0x1913, 0x1914 356*4882a593Smuzhiyun */ 357*4882a593Smuzhiyun #define SLG51000_SLOT_TIME_MAX_DOWN1_SHIFT 6 358*4882a593Smuzhiyun #define SLG51000_SLOT_TIME_MAX_DOWN1_MASK (0x03 << 6) 359*4882a593Smuzhiyun #define SLG51000_SLOT_TIME_MAX_UP1_SHIFT 4 360*4882a593Smuzhiyun #define SLG51000_SLOT_TIME_MAX_UP1_MASK (0x03 << 4) 361*4882a593Smuzhiyun #define SLG51000_SLOT_TIME_MAX_DOWN0_SHIFT 2 362*4882a593Smuzhiyun #define SLG51000_SLOT_TIME_MAX_DOWN0_MASK (0x03 << 2) 363*4882a593Smuzhiyun #define SLG51000_SLOT_TIME_MAX_UP0_SHIFT 0 364*4882a593Smuzhiyun #define SLG51000_SLOT_TIME_MAX_UP0_MASK (0x03 << 0) 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun /* SLG51000_PWRSEQ_INPUT_SENSE_CONF_A = 0x1915 */ 367*4882a593Smuzhiyun #define SLG51000_TRIG_UP_SENSE_SHIFT 6 368*4882a593Smuzhiyun #define SLG51000_TRIG_UP_SENSE_MASK (0x01 << 6) 369*4882a593Smuzhiyun #define SLG51000_UP_EN_SENSE5_SHIFT 5 370*4882a593Smuzhiyun #define SLG51000_UP_EN_SENSE5_MASK (0x01 << 5) 371*4882a593Smuzhiyun #define SLG51000_UP_EN_SENSE4_SHIFT 4 372*4882a593Smuzhiyun #define SLG51000_UP_EN_SENSE4_MASK (0x01 << 4) 373*4882a593Smuzhiyun #define SLG51000_UP_EN_SENSE3_SHIFT 3 374*4882a593Smuzhiyun #define SLG51000_UP_EN_SENSE3_MASK (0x01 << 3) 375*4882a593Smuzhiyun #define SLG51000_UP_EN_SENSE2_SHIFT 2 376*4882a593Smuzhiyun #define SLG51000_UP_EN_SENSE2_MASK (0x01 << 2) 377*4882a593Smuzhiyun #define SLG51000_UP_EN_SENSE1_SHIFT 1 378*4882a593Smuzhiyun #define SLG51000_UP_EN_SENSE1_MASK (0x01 << 1) 379*4882a593Smuzhiyun #define SLG51000_UP_EN_SENSE0_SHIFT 0 380*4882a593Smuzhiyun #define SLG51000_UP_EN_SENSE0_MASK (0x01 << 0) 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun /* SLG51000_PWRSEQ_INPUT_SENSE_CONF_B = 0x1916 */ 383*4882a593Smuzhiyun #define SLG51000_CRASH_DETECT_SENSE_SHIFT 7 384*4882a593Smuzhiyun #define SLG51000_CRASH_DETECT_SENSE_MASK (0x01 << 7) 385*4882a593Smuzhiyun #define SLG51000_TRIG_DOWN_SENSE_SHIFT 6 386*4882a593Smuzhiyun #define SLG51000_TRIG_DOWN_SENSE_MASK (0x01 << 6) 387*4882a593Smuzhiyun #define SLG51000_DOWN_EN_SENSE5_SHIFT 5 388*4882a593Smuzhiyun #define SLG51000_DOWN_EN_SENSE5_MASK (0x01 << 5) 389*4882a593Smuzhiyun #define SLG51000_DOWN_EN_SENSE4_SHIFT 4 390*4882a593Smuzhiyun #define SLG51000_DOWN_EN_SENSE4_MASK (0x01 << 4) 391*4882a593Smuzhiyun #define SLG51000_DOWN_EN_SENSE3_SHIFT 3 392*4882a593Smuzhiyun #define SLG51000_DOWN_EN_SENSE3_MASK (0x01 << 3) 393*4882a593Smuzhiyun #define SLG51000_DOWN_EN_SENSE2_SHIFT 2 394*4882a593Smuzhiyun #define SLG51000_DOWN_EN_SENSE2_MASK (0x01 << 2) 395*4882a593Smuzhiyun #define SLG51000_DOWN_EN_SENSE1_SHIFT 1 396*4882a593Smuzhiyun #define SLG51000_DOWN_EN_SENSE1_MASK (0x01 << 1) 397*4882a593Smuzhiyun #define SLG51000_DOWN_EN_SENSE0_SHIFT 0 398*4882a593Smuzhiyun #define SLG51000_DOWN_EN_SENSE0_MASK (0x01 << 0) 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun /* SLG51000_LDO1_VSEL ~ SLG51000_LDO7_VSEL = 401*4882a593Smuzhiyun * 0x2000, 0x2200, 0x2300, 0x2500, 0x2700, 0x2900, 0x3100 402*4882a593Smuzhiyun */ 403*4882a593Smuzhiyun #define SLG51000_VSEL_SHIFT 0 404*4882a593Smuzhiyun #define SLG51000_VSEL_MASK (0xff << 0) 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun /* SLG51000_LDO1_MINV ~ SLG51000_LDO7_MINV = 407*4882a593Smuzhiyun * 0x2060, 0x2260, 0x2360, 0x2560, 0x2760, 0x2960, 0x3160 408*4882a593Smuzhiyun */ 409*4882a593Smuzhiyun #define SLG51000_MINV_SHIFT 0 410*4882a593Smuzhiyun #define SLG51000_MINV_MASK (0xff << 0) 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun /* SLG51000_LDO1_MAXV ~ SLG51000_LDO7_MAXV = 413*4882a593Smuzhiyun * 0x2061, 0x2261, 0x2361, 0x2561, 0x2761, 0x2961, 0x3161 414*4882a593Smuzhiyun */ 415*4882a593Smuzhiyun #define SLG51000_MAXV_SHIFT 0 416*4882a593Smuzhiyun #define SLG51000_MAXV_MASK (0xff << 0) 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun /* SLG51000_LDO1_MISC1 = 0x2064, SLG51000_LDO2_MISC1 = 0x2264 */ 419*4882a593Smuzhiyun #define SLG51000_SEL_VRANGE_SHIFT 0 420*4882a593Smuzhiyun #define SLG51000_SEL_VRANGE_MASK (0x01 << 0) 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun /* SLG51000_LDO1_VSEL_ACTUAL ~ SLG51000_LDO7_VSEL_ACTUAL = 423*4882a593Smuzhiyun * 0x2065, 0x2265, 0x2366, 0x2566, 0x2767, 0x2967, 0x3166 424*4882a593Smuzhiyun */ 425*4882a593Smuzhiyun #define SLG51000_VSEL_ACTUAL_SHIFT 0 426*4882a593Smuzhiyun #define SLG51000_VSEL_ACTUAL_MASK (0xff << 0) 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun /* SLG51000_LDO1_EVENT ~ SLG51000_LDO7_EVENT = 429*4882a593Smuzhiyun * 0x20c0, 0x22c0, 0x23c0, 0x25c0, 0x27c0, 0x29c0, 0x31c0 430*4882a593Smuzhiyun */ 431*4882a593Smuzhiyun #define SLG51000_EVT_ILIM_FLAG_SHIFT 0 432*4882a593Smuzhiyun #define SLG51000_EVT_ILIM_FLAG_MASK (0x01 << 0) 433*4882a593Smuzhiyun #define SLG51000_EVT_VOUT_OK_FLAG_SHIFT 1 434*4882a593Smuzhiyun #define SLG51000_EVT_VOUT_OK_FLAG_MASK (0x01 << 1) 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun /* SLG51000_LDO1_STATUS ~ SLG51000_LDO7_STATUS = 437*4882a593Smuzhiyun * 0x20c1, 0x22c1, 0x23c1, 0x25c1, 0x27c1, 0x29c1, 0x31c1 438*4882a593Smuzhiyun */ 439*4882a593Smuzhiyun #define SLG51000_STA_ILIM_FLAG_SHIFT 0 440*4882a593Smuzhiyun #define SLG51000_STA_ILIM_FLAG_MASK (0x01 << 0) 441*4882a593Smuzhiyun #define SLG51000_STA_VOUT_OK_FLAG_SHIFT 1 442*4882a593Smuzhiyun #define SLG51000_STA_VOUT_OK_FLAG_MASK (0x01 << 1) 443*4882a593Smuzhiyun 444*4882a593Smuzhiyun /* SLG51000_LDO1_IRQ_MASK ~ SLG51000_LDO7_IRQ_MASK = 445*4882a593Smuzhiyun * 0x20c2, 0x22c2, 0x23c2, 0x25c2, 0x27c2, 0x29c2, 0x31c2 446*4882a593Smuzhiyun */ 447*4882a593Smuzhiyun #define SLG51000_IRQ_ILIM_FLAG_SHIFT 0 448*4882a593Smuzhiyun #define SLG51000_IRQ_ILIM_FLAG_MASK (0x01 << 0) 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun /* SLG51000_LDO3_CONF1 ~ SLG51000_LDO7_CONF1 = 451*4882a593Smuzhiyun * 0x2364, 0x2564, 0x2765, 0x2965, 0x3164 452*4882a593Smuzhiyun */ 453*4882a593Smuzhiyun #define SLG51000_SEL_START_ILIM_SHIFT 0 454*4882a593Smuzhiyun #define SLG51000_SEL_START_ILIM_MASK (0x7f << 0) 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun /* SLG51000_LDO3_CONF2 ~ SLG51000_LDO7_CONF2 = 457*4882a593Smuzhiyun * 0x2365, 0x2565, 0x2766, 0x2966, 0x3165 458*4882a593Smuzhiyun */ 459*4882a593Smuzhiyun #define SLG51000_SEL_FUNC_ILIM_SHIFT 0 460*4882a593Smuzhiyun #define SLG51000_SEL_FUNC_ILIM_MASK (0x7f << 0) 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun /* SLG51000_LDO5_TRIM2 = 0x2763, SLG51000_LDO6_TRIM2 = 0x2963 */ 463*4882a593Smuzhiyun #define SLG51000_SEL_BYP_SLEW_RATE_SHIFT 2 464*4882a593Smuzhiyun #define SLG51000_SEL_BYP_SLEW_RATE_MASK (0x03 << 2) 465*4882a593Smuzhiyun #define SLG51000_SEL_BYP_VGATE_SHIFT 1 466*4882a593Smuzhiyun #define SLG51000_SEL_BYP_VGATE_MASK (0x01 << 1) 467*4882a593Smuzhiyun #define SLG51000_SEL_BYP_MODE_SHIFT 0 468*4882a593Smuzhiyun #define SLG51000_SEL_BYP_MODE_MASK (0x01 << 0) 469*4882a593Smuzhiyun 470*4882a593Smuzhiyun /* SLG51000_OTP_EVENT = 0x782b */ 471*4882a593Smuzhiyun #define SLG51000_EVT_CRC_SHIFT 0 472*4882a593Smuzhiyun #define SLG51000_EVT_CRC_MASK (0x01 << 0) 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun /* SLG51000_OTP_IRQ_MASK = 0x782d */ 475*4882a593Smuzhiyun #define SLG51000_IRQ_CRC_SHIFT 0 476*4882a593Smuzhiyun #define SLG51000_IRQ_CRC_MASK (0x01 << 0) 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun /* SLG51000_OTP_LOCK_OTP_PROG = 0x78fe */ 479*4882a593Smuzhiyun #define SLG51000_LOCK_OTP_PROG_SHIFT 0 480*4882a593Smuzhiyun #define SLG51000_LOCK_OTP_PROG_MASK (0x01 << 0) 481*4882a593Smuzhiyun 482*4882a593Smuzhiyun /* SLG51000_OTP_LOCK_CTRL = 0x78ff */ 483*4882a593Smuzhiyun #define SLG51000_LOCK_DFT_SHIFT 1 484*4882a593Smuzhiyun #define SLG51000_LOCK_DFT_MASK (0x01 << 1) 485*4882a593Smuzhiyun #define SLG51000_LOCK_RWT_SHIFT 0 486*4882a593Smuzhiyun #define SLG51000_LOCK_RWT_MASK (0x01 << 0) 487*4882a593Smuzhiyun 488*4882a593Smuzhiyun /* SLG51000_LOCK_GLOBAL_LOCK_CTRL1 = 0x8000 */ 489*4882a593Smuzhiyun #define SLG51000_LDO7_LOCK_SHIFT 7 490*4882a593Smuzhiyun #define SLG51000_LDO7_LOCK_MASK (0x01 << 7) 491*4882a593Smuzhiyun #define SLG51000_LDO6_LOCK_SHIFT 6 492*4882a593Smuzhiyun #define SLG51000_LDO6_LOCK_MASK (0x01 << 6) 493*4882a593Smuzhiyun #define SLG51000_LDO5_LOCK_SHIFT 5 494*4882a593Smuzhiyun #define SLG51000_LDO5_LOCK_MASK (0x01 << 5) 495*4882a593Smuzhiyun #define SLG51000_LDO4_LOCK_SHIFT 4 496*4882a593Smuzhiyun #define SLG51000_LDO4_LOCK_MASK (0x01 << 4) 497*4882a593Smuzhiyun #define SLG51000_LDO3_LOCK_SHIFT 3 498*4882a593Smuzhiyun #define SLG51000_LDO3_LOCK_MASK (0x01 << 3) 499*4882a593Smuzhiyun #define SLG51000_LDO2_LOCK_SHIFT 2 500*4882a593Smuzhiyun #define SLG51000_LDO2_LOCK_MASK (0x01 << 2) 501*4882a593Smuzhiyun #define SLG51000_LDO1_LOCK_SHIFT 1 502*4882a593Smuzhiyun #define SLG51000_LDO1_LOCK_MASK (0x01 << 1) 503*4882a593Smuzhiyun 504*4882a593Smuzhiyun #endif /* __SLG51000_REGISTERS_H__ */ 505*4882a593Smuzhiyun 506