1*4882a593Smuzhiyun //SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2017 Spreadtrum Communications Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/module.h>
7*4882a593Smuzhiyun #include <linux/of.h>
8*4882a593Smuzhiyun #include <linux/platform_device.h>
9*4882a593Smuzhiyun #include <linux/regmap.h>
10*4882a593Smuzhiyun #include <linux/regulator/driver.h>
11*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /*
14*4882a593Smuzhiyun * SC2731 regulator lock register
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun #define SC2731_PWR_WR_PROT 0xf0c
17*4882a593Smuzhiyun #define SC2731_WR_UNLOCK_VALUE 0x6e7f
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /*
20*4882a593Smuzhiyun * SC2731 enable register
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun #define SC2731_POWER_PD_SW 0xc28
23*4882a593Smuzhiyun #define SC2731_LDO_CAMA0_PD 0xcfc
24*4882a593Smuzhiyun #define SC2731_LDO_CAMA1_PD 0xd04
25*4882a593Smuzhiyun #define SC2731_LDO_CAMMOT_PD 0xd0c
26*4882a593Smuzhiyun #define SC2731_LDO_VLDO_PD 0xd6c
27*4882a593Smuzhiyun #define SC2731_LDO_EMMCCORE_PD 0xd2c
28*4882a593Smuzhiyun #define SC2731_LDO_SDCORE_PD 0xd74
29*4882a593Smuzhiyun #define SC2731_LDO_SDIO_PD 0xd70
30*4882a593Smuzhiyun #define SC2731_LDO_WIFIPA_PD 0xd4c
31*4882a593Smuzhiyun #define SC2731_LDO_USB33_PD 0xd5c
32*4882a593Smuzhiyun #define SC2731_LDO_CAMD0_PD 0xd7c
33*4882a593Smuzhiyun #define SC2731_LDO_CAMD1_PD 0xd84
34*4882a593Smuzhiyun #define SC2731_LDO_CON_PD 0xd8c
35*4882a593Smuzhiyun #define SC2731_LDO_CAMIO_PD 0xd94
36*4882a593Smuzhiyun #define SC2731_LDO_SRAM_PD 0xd78
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /*
39*4882a593Smuzhiyun * SC2731 enable mask
40*4882a593Smuzhiyun */
41*4882a593Smuzhiyun #define SC2731_DCDC_CPU0_PD_MASK BIT(4)
42*4882a593Smuzhiyun #define SC2731_DCDC_CPU1_PD_MASK BIT(3)
43*4882a593Smuzhiyun #define SC2731_DCDC_RF_PD_MASK BIT(11)
44*4882a593Smuzhiyun #define SC2731_LDO_CAMA0_PD_MASK BIT(0)
45*4882a593Smuzhiyun #define SC2731_LDO_CAMA1_PD_MASK BIT(0)
46*4882a593Smuzhiyun #define SC2731_LDO_CAMMOT_PD_MASK BIT(0)
47*4882a593Smuzhiyun #define SC2731_LDO_VLDO_PD_MASK BIT(0)
48*4882a593Smuzhiyun #define SC2731_LDO_EMMCCORE_PD_MASK BIT(0)
49*4882a593Smuzhiyun #define SC2731_LDO_SDCORE_PD_MASK BIT(0)
50*4882a593Smuzhiyun #define SC2731_LDO_SDIO_PD_MASK BIT(0)
51*4882a593Smuzhiyun #define SC2731_LDO_WIFIPA_PD_MASK BIT(0)
52*4882a593Smuzhiyun #define SC2731_LDO_USB33_PD_MASK BIT(0)
53*4882a593Smuzhiyun #define SC2731_LDO_CAMD0_PD_MASK BIT(0)
54*4882a593Smuzhiyun #define SC2731_LDO_CAMD1_PD_MASK BIT(0)
55*4882a593Smuzhiyun #define SC2731_LDO_CON_PD_MASK BIT(0)
56*4882a593Smuzhiyun #define SC2731_LDO_CAMIO_PD_MASK BIT(0)
57*4882a593Smuzhiyun #define SC2731_LDO_SRAM_PD_MASK BIT(0)
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /*
60*4882a593Smuzhiyun * SC2731 vsel register
61*4882a593Smuzhiyun */
62*4882a593Smuzhiyun #define SC2731_DCDC_CPU0_VOL 0xc54
63*4882a593Smuzhiyun #define SC2731_DCDC_CPU1_VOL 0xc64
64*4882a593Smuzhiyun #define SC2731_DCDC_RF_VOL 0xcb8
65*4882a593Smuzhiyun #define SC2731_LDO_CAMA0_VOL 0xd00
66*4882a593Smuzhiyun #define SC2731_LDO_CAMA1_VOL 0xd08
67*4882a593Smuzhiyun #define SC2731_LDO_CAMMOT_VOL 0xd10
68*4882a593Smuzhiyun #define SC2731_LDO_VLDO_VOL 0xd28
69*4882a593Smuzhiyun #define SC2731_LDO_EMMCCORE_VOL 0xd30
70*4882a593Smuzhiyun #define SC2731_LDO_SDCORE_VOL 0xd38
71*4882a593Smuzhiyun #define SC2731_LDO_SDIO_VOL 0xd40
72*4882a593Smuzhiyun #define SC2731_LDO_WIFIPA_VOL 0xd50
73*4882a593Smuzhiyun #define SC2731_LDO_USB33_VOL 0xd60
74*4882a593Smuzhiyun #define SC2731_LDO_CAMD0_VOL 0xd80
75*4882a593Smuzhiyun #define SC2731_LDO_CAMD1_VOL 0xd88
76*4882a593Smuzhiyun #define SC2731_LDO_CON_VOL 0xd90
77*4882a593Smuzhiyun #define SC2731_LDO_CAMIO_VOL 0xd98
78*4882a593Smuzhiyun #define SC2731_LDO_SRAM_VOL 0xdB0
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /*
81*4882a593Smuzhiyun * SC2731 vsel register mask
82*4882a593Smuzhiyun */
83*4882a593Smuzhiyun #define SC2731_DCDC_CPU0_VOL_MASK GENMASK(8, 0)
84*4882a593Smuzhiyun #define SC2731_DCDC_CPU1_VOL_MASK GENMASK(8, 0)
85*4882a593Smuzhiyun #define SC2731_DCDC_RF_VOL_MASK GENMASK(8, 0)
86*4882a593Smuzhiyun #define SC2731_LDO_CAMA0_VOL_MASK GENMASK(7, 0)
87*4882a593Smuzhiyun #define SC2731_LDO_CAMA1_VOL_MASK GENMASK(7, 0)
88*4882a593Smuzhiyun #define SC2731_LDO_CAMMOT_VOL_MASK GENMASK(7, 0)
89*4882a593Smuzhiyun #define SC2731_LDO_VLDO_VOL_MASK GENMASK(7, 0)
90*4882a593Smuzhiyun #define SC2731_LDO_EMMCCORE_VOL_MASK GENMASK(7, 0)
91*4882a593Smuzhiyun #define SC2731_LDO_SDCORE_VOL_MASK GENMASK(7, 0)
92*4882a593Smuzhiyun #define SC2731_LDO_SDIO_VOL_MASK GENMASK(7, 0)
93*4882a593Smuzhiyun #define SC2731_LDO_WIFIPA_VOL_MASK GENMASK(7, 0)
94*4882a593Smuzhiyun #define SC2731_LDO_USB33_VOL_MASK GENMASK(7, 0)
95*4882a593Smuzhiyun #define SC2731_LDO_CAMD0_VOL_MASK GENMASK(6, 0)
96*4882a593Smuzhiyun #define SC2731_LDO_CAMD1_VOL_MASK GENMASK(6, 0)
97*4882a593Smuzhiyun #define SC2731_LDO_CON_VOL_MASK GENMASK(6, 0)
98*4882a593Smuzhiyun #define SC2731_LDO_CAMIO_VOL_MASK GENMASK(6, 0)
99*4882a593Smuzhiyun #define SC2731_LDO_SRAM_VOL_MASK GENMASK(6, 0)
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun enum sc2731_regulator_id {
102*4882a593Smuzhiyun SC2731_BUCK_CPU0,
103*4882a593Smuzhiyun SC2731_BUCK_CPU1,
104*4882a593Smuzhiyun SC2731_BUCK_RF,
105*4882a593Smuzhiyun SC2731_LDO_CAMA0,
106*4882a593Smuzhiyun SC2731_LDO_CAMA1,
107*4882a593Smuzhiyun SC2731_LDO_CAMMOT,
108*4882a593Smuzhiyun SC2731_LDO_VLDO,
109*4882a593Smuzhiyun SC2731_LDO_EMMCCORE,
110*4882a593Smuzhiyun SC2731_LDO_SDCORE,
111*4882a593Smuzhiyun SC2731_LDO_SDIO,
112*4882a593Smuzhiyun SC2731_LDO_WIFIPA,
113*4882a593Smuzhiyun SC2731_LDO_USB33,
114*4882a593Smuzhiyun SC2731_LDO_CAMD0,
115*4882a593Smuzhiyun SC2731_LDO_CAMD1,
116*4882a593Smuzhiyun SC2731_LDO_CON,
117*4882a593Smuzhiyun SC2731_LDO_CAMIO,
118*4882a593Smuzhiyun SC2731_LDO_SRAM,
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun static const struct regulator_ops sc2731_regu_linear_ops = {
122*4882a593Smuzhiyun .enable = regulator_enable_regmap,
123*4882a593Smuzhiyun .disable = regulator_disable_regmap,
124*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
125*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
126*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
127*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
128*4882a593Smuzhiyun };
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun #define SC2731_REGU_LINEAR(_id, en_reg, en_mask, vreg, vmask, \
131*4882a593Smuzhiyun vstep, vmin, vmax) { \
132*4882a593Smuzhiyun .name = #_id, \
133*4882a593Smuzhiyun .of_match = of_match_ptr(#_id), \
134*4882a593Smuzhiyun .ops = &sc2731_regu_linear_ops, \
135*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
136*4882a593Smuzhiyun .id = SC2731_##_id, \
137*4882a593Smuzhiyun .owner = THIS_MODULE, \
138*4882a593Smuzhiyun .min_uV = vmin, \
139*4882a593Smuzhiyun .n_voltages = ((vmax) - (vmin)) / (vstep) + 1, \
140*4882a593Smuzhiyun .uV_step = vstep, \
141*4882a593Smuzhiyun .enable_is_inverted = true, \
142*4882a593Smuzhiyun .enable_val = 0, \
143*4882a593Smuzhiyun .enable_reg = en_reg, \
144*4882a593Smuzhiyun .enable_mask = en_mask, \
145*4882a593Smuzhiyun .vsel_reg = vreg, \
146*4882a593Smuzhiyun .vsel_mask = vmask, \
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun static const struct regulator_desc regulators[] = {
150*4882a593Smuzhiyun SC2731_REGU_LINEAR(BUCK_CPU0, SC2731_POWER_PD_SW,
151*4882a593Smuzhiyun SC2731_DCDC_CPU0_PD_MASK, SC2731_DCDC_CPU0_VOL,
152*4882a593Smuzhiyun SC2731_DCDC_CPU0_VOL_MASK, 3125, 400000, 1996875),
153*4882a593Smuzhiyun SC2731_REGU_LINEAR(BUCK_CPU1, SC2731_POWER_PD_SW,
154*4882a593Smuzhiyun SC2731_DCDC_CPU1_PD_MASK, SC2731_DCDC_CPU1_VOL,
155*4882a593Smuzhiyun SC2731_DCDC_CPU1_VOL_MASK, 3125, 400000, 1996875),
156*4882a593Smuzhiyun SC2731_REGU_LINEAR(BUCK_RF, SC2731_POWER_PD_SW, SC2731_DCDC_RF_PD_MASK,
157*4882a593Smuzhiyun SC2731_DCDC_RF_VOL, SC2731_DCDC_RF_VOL_MASK,
158*4882a593Smuzhiyun 3125, 600000, 2196875),
159*4882a593Smuzhiyun SC2731_REGU_LINEAR(LDO_CAMA0, SC2731_LDO_CAMA0_PD,
160*4882a593Smuzhiyun SC2731_LDO_CAMA0_PD_MASK, SC2731_LDO_CAMA0_VOL,
161*4882a593Smuzhiyun SC2731_LDO_CAMA0_VOL_MASK, 10000, 1200000, 3750000),
162*4882a593Smuzhiyun SC2731_REGU_LINEAR(LDO_CAMA1, SC2731_LDO_CAMA1_PD,
163*4882a593Smuzhiyun SC2731_LDO_CAMA1_PD_MASK, SC2731_LDO_CAMA1_VOL,
164*4882a593Smuzhiyun SC2731_LDO_CAMA1_VOL_MASK, 10000, 1200000, 3750000),
165*4882a593Smuzhiyun SC2731_REGU_LINEAR(LDO_CAMMOT, SC2731_LDO_CAMMOT_PD,
166*4882a593Smuzhiyun SC2731_LDO_CAMMOT_PD_MASK, SC2731_LDO_CAMMOT_VOL,
167*4882a593Smuzhiyun SC2731_LDO_CAMMOT_VOL_MASK, 10000, 1200000, 3750000),
168*4882a593Smuzhiyun SC2731_REGU_LINEAR(LDO_VLDO, SC2731_LDO_VLDO_PD,
169*4882a593Smuzhiyun SC2731_LDO_VLDO_PD_MASK, SC2731_LDO_VLDO_VOL,
170*4882a593Smuzhiyun SC2731_LDO_VLDO_VOL_MASK, 10000, 1200000, 3750000),
171*4882a593Smuzhiyun SC2731_REGU_LINEAR(LDO_EMMCCORE, SC2731_LDO_EMMCCORE_PD,
172*4882a593Smuzhiyun SC2731_LDO_EMMCCORE_PD_MASK, SC2731_LDO_EMMCCORE_VOL,
173*4882a593Smuzhiyun SC2731_LDO_EMMCCORE_VOL_MASK, 10000, 1200000,
174*4882a593Smuzhiyun 3750000),
175*4882a593Smuzhiyun SC2731_REGU_LINEAR(LDO_SDCORE, SC2731_LDO_SDCORE_PD,
176*4882a593Smuzhiyun SC2731_LDO_SDCORE_PD_MASK, SC2731_LDO_SDCORE_VOL,
177*4882a593Smuzhiyun SC2731_LDO_SDCORE_VOL_MASK, 10000, 1200000, 3750000),
178*4882a593Smuzhiyun SC2731_REGU_LINEAR(LDO_SDIO, SC2731_LDO_SDIO_PD,
179*4882a593Smuzhiyun SC2731_LDO_SDIO_PD_MASK, SC2731_LDO_SDIO_VOL,
180*4882a593Smuzhiyun SC2731_LDO_SDIO_VOL_MASK, 10000, 1200000, 3750000),
181*4882a593Smuzhiyun SC2731_REGU_LINEAR(LDO_WIFIPA, SC2731_LDO_WIFIPA_PD,
182*4882a593Smuzhiyun SC2731_LDO_WIFIPA_PD_MASK, SC2731_LDO_WIFIPA_VOL,
183*4882a593Smuzhiyun SC2731_LDO_WIFIPA_VOL_MASK, 10000, 1200000, 3750000),
184*4882a593Smuzhiyun SC2731_REGU_LINEAR(LDO_USB33, SC2731_LDO_USB33_PD,
185*4882a593Smuzhiyun SC2731_LDO_USB33_PD_MASK, SC2731_LDO_USB33_VOL,
186*4882a593Smuzhiyun SC2731_LDO_USB33_VOL_MASK, 10000, 1200000, 3750000),
187*4882a593Smuzhiyun SC2731_REGU_LINEAR(LDO_CAMD0, SC2731_LDO_CAMD0_PD,
188*4882a593Smuzhiyun SC2731_LDO_CAMD0_PD_MASK, SC2731_LDO_CAMD0_VOL,
189*4882a593Smuzhiyun SC2731_LDO_CAMD0_VOL_MASK, 6250, 1000000, 1793750),
190*4882a593Smuzhiyun SC2731_REGU_LINEAR(LDO_CAMD1, SC2731_LDO_CAMD1_PD,
191*4882a593Smuzhiyun SC2731_LDO_CAMD1_PD_MASK, SC2731_LDO_CAMD1_VOL,
192*4882a593Smuzhiyun SC2731_LDO_CAMD1_VOL_MASK, 6250, 1000000, 1793750),
193*4882a593Smuzhiyun SC2731_REGU_LINEAR(LDO_CON, SC2731_LDO_CON_PD,
194*4882a593Smuzhiyun SC2731_LDO_CON_PD_MASK, SC2731_LDO_CON_VOL,
195*4882a593Smuzhiyun SC2731_LDO_CON_VOL_MASK, 6250, 1000000, 1793750),
196*4882a593Smuzhiyun SC2731_REGU_LINEAR(LDO_CAMIO, SC2731_LDO_CAMIO_PD,
197*4882a593Smuzhiyun SC2731_LDO_CAMIO_PD_MASK, SC2731_LDO_CAMIO_VOL,
198*4882a593Smuzhiyun SC2731_LDO_CAMIO_VOL_MASK, 6250, 1000000, 1793750),
199*4882a593Smuzhiyun SC2731_REGU_LINEAR(LDO_SRAM, SC2731_LDO_SRAM_PD,
200*4882a593Smuzhiyun SC2731_LDO_SRAM_PD_MASK, SC2731_LDO_SRAM_VOL,
201*4882a593Smuzhiyun SC2731_LDO_SRAM_VOL_MASK, 6250, 1000000, 1793750),
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun
sc2731_regulator_unlock(struct regmap * regmap)204*4882a593Smuzhiyun static int sc2731_regulator_unlock(struct regmap *regmap)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun return regmap_write(regmap, SC2731_PWR_WR_PROT,
207*4882a593Smuzhiyun SC2731_WR_UNLOCK_VALUE);
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
sc2731_regulator_probe(struct platform_device * pdev)210*4882a593Smuzhiyun static int sc2731_regulator_probe(struct platform_device *pdev)
211*4882a593Smuzhiyun {
212*4882a593Smuzhiyun int i, ret;
213*4882a593Smuzhiyun struct regmap *regmap;
214*4882a593Smuzhiyun struct regulator_config config = { };
215*4882a593Smuzhiyun struct regulator_dev *rdev;
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun regmap = dev_get_regmap(pdev->dev.parent, NULL);
218*4882a593Smuzhiyun if (!regmap) {
219*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to get regmap.\n");
220*4882a593Smuzhiyun return -ENODEV;
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun ret = sc2731_regulator_unlock(regmap);
224*4882a593Smuzhiyun if (ret) {
225*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to release regulator lock\n");
226*4882a593Smuzhiyun return ret;
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun config.dev = &pdev->dev;
230*4882a593Smuzhiyun config.regmap = regmap;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(regulators); i++) {
233*4882a593Smuzhiyun rdev = devm_regulator_register(&pdev->dev, ®ulators[i],
234*4882a593Smuzhiyun &config);
235*4882a593Smuzhiyun if (IS_ERR(rdev)) {
236*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to register regulator %s\n",
237*4882a593Smuzhiyun regulators[i].name);
238*4882a593Smuzhiyun return PTR_ERR(rdev);
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun return 0;
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun static struct platform_driver sc2731_regulator_driver = {
246*4882a593Smuzhiyun .driver = {
247*4882a593Smuzhiyun .name = "sc27xx-regulator",
248*4882a593Smuzhiyun },
249*4882a593Smuzhiyun .probe = sc2731_regulator_probe,
250*4882a593Smuzhiyun };
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun module_platform_driver(sc2731_regulator_driver);
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun MODULE_AUTHOR("Chen Junhui <erick.chen@spreadtrum.com>");
255*4882a593Smuzhiyun MODULE_DESCRIPTION("Spreadtrum SC2731 regulator driver");
256*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
257