xref: /OK3568_Linux_fs/kernel/drivers/regulator/s2mps11.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (c) 2012-2014 Samsung Electronics Co., Ltd
4*4882a593Smuzhiyun //              http://www.samsung.com
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <linux/bug.h>
7*4882a593Smuzhiyun #include <linux/err.h>
8*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
9*4882a593Smuzhiyun #include <linux/slab.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/regulator/driver.h>
15*4882a593Smuzhiyun #include <linux/regulator/machine.h>
16*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
17*4882a593Smuzhiyun #include <linux/mfd/samsung/core.h>
18*4882a593Smuzhiyun #include <linux/mfd/samsung/s2mps11.h>
19*4882a593Smuzhiyun #include <linux/mfd/samsung/s2mps13.h>
20*4882a593Smuzhiyun #include <linux/mfd/samsung/s2mps14.h>
21*4882a593Smuzhiyun #include <linux/mfd/samsung/s2mps15.h>
22*4882a593Smuzhiyun #include <linux/mfd/samsung/s2mpu02.h>
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun /* The highest number of possible regulators for supported devices. */
25*4882a593Smuzhiyun #define S2MPS_REGULATOR_MAX		S2MPS13_REGULATOR_MAX
26*4882a593Smuzhiyun struct s2mps11_info {
27*4882a593Smuzhiyun 	int ramp_delay2;
28*4882a593Smuzhiyun 	int ramp_delay34;
29*4882a593Smuzhiyun 	int ramp_delay5;
30*4882a593Smuzhiyun 	int ramp_delay16;
31*4882a593Smuzhiyun 	int ramp_delay7810;
32*4882a593Smuzhiyun 	int ramp_delay9;
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun 	enum sec_device_type dev_type;
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun 	/*
37*4882a593Smuzhiyun 	 * One bit for each S2MPS11/S2MPS13/S2MPS14/S2MPU02 regulator whether
38*4882a593Smuzhiyun 	 * the suspend mode was enabled.
39*4882a593Smuzhiyun 	 */
40*4882a593Smuzhiyun 	DECLARE_BITMAP(suspend_state, S2MPS_REGULATOR_MAX);
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun 	/*
43*4882a593Smuzhiyun 	 * Array (size: number of regulators) with GPIO-s for external
44*4882a593Smuzhiyun 	 * sleep control.
45*4882a593Smuzhiyun 	 */
46*4882a593Smuzhiyun 	struct gpio_desc **ext_control_gpiod;
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun 
get_ramp_delay(int ramp_delay)49*4882a593Smuzhiyun static int get_ramp_delay(int ramp_delay)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun 	unsigned char cnt = 0;
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 	ramp_delay /= 6250;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	while (true) {
56*4882a593Smuzhiyun 		ramp_delay = ramp_delay >> 1;
57*4882a593Smuzhiyun 		if (ramp_delay == 0)
58*4882a593Smuzhiyun 			break;
59*4882a593Smuzhiyun 		cnt++;
60*4882a593Smuzhiyun 	}
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	if (cnt > 3)
63*4882a593Smuzhiyun 		cnt = 3;
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	return cnt;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun 
s2mps11_regulator_set_voltage_time_sel(struct regulator_dev * rdev,unsigned int old_selector,unsigned int new_selector)68*4882a593Smuzhiyun static int s2mps11_regulator_set_voltage_time_sel(struct regulator_dev *rdev,
69*4882a593Smuzhiyun 				   unsigned int old_selector,
70*4882a593Smuzhiyun 				   unsigned int new_selector)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun 	struct s2mps11_info *s2mps11 = rdev_get_drvdata(rdev);
73*4882a593Smuzhiyun 	int rdev_id = rdev_get_id(rdev);
74*4882a593Smuzhiyun 	unsigned int ramp_delay = 0;
75*4882a593Smuzhiyun 	int old_volt, new_volt;
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	switch (rdev_id) {
78*4882a593Smuzhiyun 	case S2MPS11_BUCK2:
79*4882a593Smuzhiyun 		ramp_delay = s2mps11->ramp_delay2;
80*4882a593Smuzhiyun 		break;
81*4882a593Smuzhiyun 	case S2MPS11_BUCK3:
82*4882a593Smuzhiyun 	case S2MPS11_BUCK4:
83*4882a593Smuzhiyun 		ramp_delay = s2mps11->ramp_delay34;
84*4882a593Smuzhiyun 		break;
85*4882a593Smuzhiyun 	case S2MPS11_BUCK5:
86*4882a593Smuzhiyun 		ramp_delay = s2mps11->ramp_delay5;
87*4882a593Smuzhiyun 		break;
88*4882a593Smuzhiyun 	case S2MPS11_BUCK6:
89*4882a593Smuzhiyun 	case S2MPS11_BUCK1:
90*4882a593Smuzhiyun 		ramp_delay = s2mps11->ramp_delay16;
91*4882a593Smuzhiyun 		break;
92*4882a593Smuzhiyun 	case S2MPS11_BUCK7:
93*4882a593Smuzhiyun 	case S2MPS11_BUCK8:
94*4882a593Smuzhiyun 	case S2MPS11_BUCK10:
95*4882a593Smuzhiyun 		ramp_delay = s2mps11->ramp_delay7810;
96*4882a593Smuzhiyun 		break;
97*4882a593Smuzhiyun 	case S2MPS11_BUCK9:
98*4882a593Smuzhiyun 		ramp_delay = s2mps11->ramp_delay9;
99*4882a593Smuzhiyun 	}
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	if (ramp_delay == 0)
102*4882a593Smuzhiyun 		ramp_delay = rdev->desc->ramp_delay;
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	old_volt = rdev->desc->min_uV + (rdev->desc->uV_step * old_selector);
105*4882a593Smuzhiyun 	new_volt = rdev->desc->min_uV + (rdev->desc->uV_step * new_selector);
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	return DIV_ROUND_UP(abs(new_volt - old_volt), ramp_delay);
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun 
s2mps11_set_ramp_delay(struct regulator_dev * rdev,int ramp_delay)110*4882a593Smuzhiyun static int s2mps11_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun 	struct s2mps11_info *s2mps11 = rdev_get_drvdata(rdev);
113*4882a593Smuzhiyun 	unsigned int ramp_val, ramp_shift, ramp_reg = S2MPS11_REG_RAMP_BUCK;
114*4882a593Smuzhiyun 	unsigned int ramp_enable = 1, enable_shift = 0;
115*4882a593Smuzhiyun 	int rdev_id = rdev_get_id(rdev);
116*4882a593Smuzhiyun 	int ret;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	switch (rdev_id) {
119*4882a593Smuzhiyun 	case S2MPS11_BUCK1:
120*4882a593Smuzhiyun 		if (ramp_delay > s2mps11->ramp_delay16)
121*4882a593Smuzhiyun 			s2mps11->ramp_delay16 = ramp_delay;
122*4882a593Smuzhiyun 		else
123*4882a593Smuzhiyun 			ramp_delay = s2mps11->ramp_delay16;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 		ramp_shift = S2MPS11_BUCK16_RAMP_SHIFT;
126*4882a593Smuzhiyun 		break;
127*4882a593Smuzhiyun 	case S2MPS11_BUCK2:
128*4882a593Smuzhiyun 		enable_shift = S2MPS11_BUCK2_RAMP_EN_SHIFT;
129*4882a593Smuzhiyun 		if (!ramp_delay) {
130*4882a593Smuzhiyun 			ramp_enable = 0;
131*4882a593Smuzhiyun 			break;
132*4882a593Smuzhiyun 		}
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 		s2mps11->ramp_delay2 = ramp_delay;
135*4882a593Smuzhiyun 		ramp_shift = S2MPS11_BUCK2_RAMP_SHIFT;
136*4882a593Smuzhiyun 		ramp_reg = S2MPS11_REG_RAMP;
137*4882a593Smuzhiyun 		break;
138*4882a593Smuzhiyun 	case S2MPS11_BUCK3:
139*4882a593Smuzhiyun 		enable_shift = S2MPS11_BUCK3_RAMP_EN_SHIFT;
140*4882a593Smuzhiyun 		if (!ramp_delay) {
141*4882a593Smuzhiyun 			ramp_enable = 0;
142*4882a593Smuzhiyun 			break;
143*4882a593Smuzhiyun 		}
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 		if (ramp_delay > s2mps11->ramp_delay34)
146*4882a593Smuzhiyun 			s2mps11->ramp_delay34 = ramp_delay;
147*4882a593Smuzhiyun 		else
148*4882a593Smuzhiyun 			ramp_delay = s2mps11->ramp_delay34;
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 		ramp_shift = S2MPS11_BUCK34_RAMP_SHIFT;
151*4882a593Smuzhiyun 		ramp_reg = S2MPS11_REG_RAMP;
152*4882a593Smuzhiyun 		break;
153*4882a593Smuzhiyun 	case S2MPS11_BUCK4:
154*4882a593Smuzhiyun 		enable_shift = S2MPS11_BUCK4_RAMP_EN_SHIFT;
155*4882a593Smuzhiyun 		if (!ramp_delay) {
156*4882a593Smuzhiyun 			ramp_enable = 0;
157*4882a593Smuzhiyun 			break;
158*4882a593Smuzhiyun 		}
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 		if (ramp_delay > s2mps11->ramp_delay34)
161*4882a593Smuzhiyun 			s2mps11->ramp_delay34 = ramp_delay;
162*4882a593Smuzhiyun 		else
163*4882a593Smuzhiyun 			ramp_delay = s2mps11->ramp_delay34;
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 		ramp_shift = S2MPS11_BUCK34_RAMP_SHIFT;
166*4882a593Smuzhiyun 		ramp_reg = S2MPS11_REG_RAMP;
167*4882a593Smuzhiyun 		break;
168*4882a593Smuzhiyun 	case S2MPS11_BUCK5:
169*4882a593Smuzhiyun 		s2mps11->ramp_delay5 = ramp_delay;
170*4882a593Smuzhiyun 		ramp_shift = S2MPS11_BUCK5_RAMP_SHIFT;
171*4882a593Smuzhiyun 		break;
172*4882a593Smuzhiyun 	case S2MPS11_BUCK6:
173*4882a593Smuzhiyun 		enable_shift = S2MPS11_BUCK6_RAMP_EN_SHIFT;
174*4882a593Smuzhiyun 		if (!ramp_delay) {
175*4882a593Smuzhiyun 			ramp_enable = 0;
176*4882a593Smuzhiyun 			break;
177*4882a593Smuzhiyun 		}
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 		if (ramp_delay > s2mps11->ramp_delay16)
180*4882a593Smuzhiyun 			s2mps11->ramp_delay16 = ramp_delay;
181*4882a593Smuzhiyun 		else
182*4882a593Smuzhiyun 			ramp_delay = s2mps11->ramp_delay16;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 		ramp_shift = S2MPS11_BUCK16_RAMP_SHIFT;
185*4882a593Smuzhiyun 		break;
186*4882a593Smuzhiyun 	case S2MPS11_BUCK7:
187*4882a593Smuzhiyun 	case S2MPS11_BUCK8:
188*4882a593Smuzhiyun 	case S2MPS11_BUCK10:
189*4882a593Smuzhiyun 		if (ramp_delay > s2mps11->ramp_delay7810)
190*4882a593Smuzhiyun 			s2mps11->ramp_delay7810 = ramp_delay;
191*4882a593Smuzhiyun 		else
192*4882a593Smuzhiyun 			ramp_delay = s2mps11->ramp_delay7810;
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 		ramp_shift = S2MPS11_BUCK7810_RAMP_SHIFT;
195*4882a593Smuzhiyun 		break;
196*4882a593Smuzhiyun 	case S2MPS11_BUCK9:
197*4882a593Smuzhiyun 		s2mps11->ramp_delay9 = ramp_delay;
198*4882a593Smuzhiyun 		ramp_shift = S2MPS11_BUCK9_RAMP_SHIFT;
199*4882a593Smuzhiyun 		break;
200*4882a593Smuzhiyun 	default:
201*4882a593Smuzhiyun 		return 0;
202*4882a593Smuzhiyun 	}
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	if (!ramp_enable)
205*4882a593Smuzhiyun 		goto ramp_disable;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	/* Ramp delay can be enabled/disabled only for buck[2346] */
208*4882a593Smuzhiyun 	if ((rdev_id >= S2MPS11_BUCK2 && rdev_id <= S2MPS11_BUCK4) ||
209*4882a593Smuzhiyun 	    rdev_id == S2MPS11_BUCK6)  {
210*4882a593Smuzhiyun 		ret = regmap_update_bits(rdev->regmap, S2MPS11_REG_RAMP,
211*4882a593Smuzhiyun 					 1 << enable_shift, 1 << enable_shift);
212*4882a593Smuzhiyun 		if (ret) {
213*4882a593Smuzhiyun 			dev_err(&rdev->dev, "failed to enable ramp rate\n");
214*4882a593Smuzhiyun 			return ret;
215*4882a593Smuzhiyun 		}
216*4882a593Smuzhiyun 	}
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	ramp_val = get_ramp_delay(ramp_delay);
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	return regmap_update_bits(rdev->regmap, ramp_reg, 0x3 << ramp_shift,
221*4882a593Smuzhiyun 				  ramp_val << ramp_shift);
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun ramp_disable:
224*4882a593Smuzhiyun 	return regmap_update_bits(rdev->regmap, S2MPS11_REG_RAMP,
225*4882a593Smuzhiyun 				  1 << enable_shift, 0);
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun 
s2mps11_regulator_enable(struct regulator_dev * rdev)228*4882a593Smuzhiyun static int s2mps11_regulator_enable(struct regulator_dev *rdev)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun 	struct s2mps11_info *s2mps11 = rdev_get_drvdata(rdev);
231*4882a593Smuzhiyun 	int rdev_id = rdev_get_id(rdev);
232*4882a593Smuzhiyun 	unsigned int val;
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	switch (s2mps11->dev_type) {
235*4882a593Smuzhiyun 	case S2MPS11X:
236*4882a593Smuzhiyun 		if (test_bit(rdev_id, s2mps11->suspend_state))
237*4882a593Smuzhiyun 			val = S2MPS14_ENABLE_SUSPEND;
238*4882a593Smuzhiyun 		else
239*4882a593Smuzhiyun 			val = rdev->desc->enable_mask;
240*4882a593Smuzhiyun 		break;
241*4882a593Smuzhiyun 	case S2MPS13X:
242*4882a593Smuzhiyun 	case S2MPS14X:
243*4882a593Smuzhiyun 		if (test_bit(rdev_id, s2mps11->suspend_state))
244*4882a593Smuzhiyun 			val = S2MPS14_ENABLE_SUSPEND;
245*4882a593Smuzhiyun 		else if (s2mps11->ext_control_gpiod[rdev_id])
246*4882a593Smuzhiyun 			val = S2MPS14_ENABLE_EXT_CONTROL;
247*4882a593Smuzhiyun 		else
248*4882a593Smuzhiyun 			val = rdev->desc->enable_mask;
249*4882a593Smuzhiyun 		break;
250*4882a593Smuzhiyun 	case S2MPU02:
251*4882a593Smuzhiyun 		if (test_bit(rdev_id, s2mps11->suspend_state))
252*4882a593Smuzhiyun 			val = S2MPU02_ENABLE_SUSPEND;
253*4882a593Smuzhiyun 		else
254*4882a593Smuzhiyun 			val = rdev->desc->enable_mask;
255*4882a593Smuzhiyun 		break;
256*4882a593Smuzhiyun 	default:
257*4882a593Smuzhiyun 		return -EINVAL;
258*4882a593Smuzhiyun 	}
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun 	return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
261*4882a593Smuzhiyun 			rdev->desc->enable_mask, val);
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun 
s2mps11_regulator_set_suspend_disable(struct regulator_dev * rdev)264*4882a593Smuzhiyun static int s2mps11_regulator_set_suspend_disable(struct regulator_dev *rdev)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun 	int ret;
267*4882a593Smuzhiyun 	unsigned int val, state;
268*4882a593Smuzhiyun 	struct s2mps11_info *s2mps11 = rdev_get_drvdata(rdev);
269*4882a593Smuzhiyun 	int rdev_id = rdev_get_id(rdev);
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	/* Below LDO should be always on or does not support suspend mode. */
272*4882a593Smuzhiyun 	switch (s2mps11->dev_type) {
273*4882a593Smuzhiyun 	case S2MPS11X:
274*4882a593Smuzhiyun 		switch (rdev_id) {
275*4882a593Smuzhiyun 		case S2MPS11_LDO2:
276*4882a593Smuzhiyun 		case S2MPS11_LDO36:
277*4882a593Smuzhiyun 		case S2MPS11_LDO37:
278*4882a593Smuzhiyun 		case S2MPS11_LDO38:
279*4882a593Smuzhiyun 			return 0;
280*4882a593Smuzhiyun 		default:
281*4882a593Smuzhiyun 			state = S2MPS14_ENABLE_SUSPEND;
282*4882a593Smuzhiyun 			break;
283*4882a593Smuzhiyun 		}
284*4882a593Smuzhiyun 		break;
285*4882a593Smuzhiyun 	case S2MPS13X:
286*4882a593Smuzhiyun 	case S2MPS14X:
287*4882a593Smuzhiyun 		switch (rdev_id) {
288*4882a593Smuzhiyun 		case S2MPS14_LDO3:
289*4882a593Smuzhiyun 			return 0;
290*4882a593Smuzhiyun 		default:
291*4882a593Smuzhiyun 			state = S2MPS14_ENABLE_SUSPEND;
292*4882a593Smuzhiyun 			break;
293*4882a593Smuzhiyun 		}
294*4882a593Smuzhiyun 		break;
295*4882a593Smuzhiyun 	case S2MPU02:
296*4882a593Smuzhiyun 		switch (rdev_id) {
297*4882a593Smuzhiyun 		case S2MPU02_LDO13:
298*4882a593Smuzhiyun 		case S2MPU02_LDO14:
299*4882a593Smuzhiyun 		case S2MPU02_LDO15:
300*4882a593Smuzhiyun 		case S2MPU02_LDO17:
301*4882a593Smuzhiyun 		case S2MPU02_BUCK7:
302*4882a593Smuzhiyun 			state = S2MPU02_DISABLE_SUSPEND;
303*4882a593Smuzhiyun 			break;
304*4882a593Smuzhiyun 		default:
305*4882a593Smuzhiyun 			state = S2MPU02_ENABLE_SUSPEND;
306*4882a593Smuzhiyun 			break;
307*4882a593Smuzhiyun 		}
308*4882a593Smuzhiyun 		break;
309*4882a593Smuzhiyun 	default:
310*4882a593Smuzhiyun 		return -EINVAL;
311*4882a593Smuzhiyun 	}
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	ret = regmap_read(rdev->regmap, rdev->desc->enable_reg, &val);
314*4882a593Smuzhiyun 	if (ret < 0)
315*4882a593Smuzhiyun 		return ret;
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	set_bit(rdev_id, s2mps11->suspend_state);
318*4882a593Smuzhiyun 	/*
319*4882a593Smuzhiyun 	 * Don't enable suspend mode if regulator is already disabled because
320*4882a593Smuzhiyun 	 * this would effectively for a short time turn on the regulator after
321*4882a593Smuzhiyun 	 * resuming.
322*4882a593Smuzhiyun 	 * However we still want to toggle the suspend_state bit for regulator
323*4882a593Smuzhiyun 	 * in case if it got enabled before suspending the system.
324*4882a593Smuzhiyun 	 */
325*4882a593Smuzhiyun 	if (!(val & rdev->desc->enable_mask))
326*4882a593Smuzhiyun 		return 0;
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
329*4882a593Smuzhiyun 				  rdev->desc->enable_mask, state);
330*4882a593Smuzhiyun }
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun static const struct regulator_ops s2mps11_ldo_ops = {
333*4882a593Smuzhiyun 	.list_voltage		= regulator_list_voltage_linear,
334*4882a593Smuzhiyun 	.map_voltage		= regulator_map_voltage_linear,
335*4882a593Smuzhiyun 	.is_enabled		= regulator_is_enabled_regmap,
336*4882a593Smuzhiyun 	.enable			= s2mps11_regulator_enable,
337*4882a593Smuzhiyun 	.disable		= regulator_disable_regmap,
338*4882a593Smuzhiyun 	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
339*4882a593Smuzhiyun 	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
340*4882a593Smuzhiyun 	.set_voltage_time_sel	= regulator_set_voltage_time_sel,
341*4882a593Smuzhiyun 	.set_suspend_disable	= s2mps11_regulator_set_suspend_disable,
342*4882a593Smuzhiyun };
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun static const struct regulator_ops s2mps11_buck_ops = {
345*4882a593Smuzhiyun 	.list_voltage		= regulator_list_voltage_linear,
346*4882a593Smuzhiyun 	.map_voltage		= regulator_map_voltage_linear,
347*4882a593Smuzhiyun 	.is_enabled		= regulator_is_enabled_regmap,
348*4882a593Smuzhiyun 	.enable			= s2mps11_regulator_enable,
349*4882a593Smuzhiyun 	.disable		= regulator_disable_regmap,
350*4882a593Smuzhiyun 	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
351*4882a593Smuzhiyun 	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
352*4882a593Smuzhiyun 	.set_voltage_time_sel	= s2mps11_regulator_set_voltage_time_sel,
353*4882a593Smuzhiyun 	.set_ramp_delay		= s2mps11_set_ramp_delay,
354*4882a593Smuzhiyun 	.set_suspend_disable	= s2mps11_regulator_set_suspend_disable,
355*4882a593Smuzhiyun };
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun #define regulator_desc_s2mps11_ldo(num, step) {		\
358*4882a593Smuzhiyun 	.name		= "LDO"#num,			\
359*4882a593Smuzhiyun 	.id		= S2MPS11_LDO##num,		\
360*4882a593Smuzhiyun 	.ops		= &s2mps11_ldo_ops,		\
361*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,		\
362*4882a593Smuzhiyun 	.owner		= THIS_MODULE,			\
363*4882a593Smuzhiyun 	.ramp_delay	= RAMP_DELAY_12_MVUS,		\
364*4882a593Smuzhiyun 	.min_uV		= MIN_800_MV,			\
365*4882a593Smuzhiyun 	.uV_step	= step,				\
366*4882a593Smuzhiyun 	.n_voltages	= S2MPS11_LDO_N_VOLTAGES,	\
367*4882a593Smuzhiyun 	.vsel_reg	= S2MPS11_REG_L1CTRL + num - 1,	\
368*4882a593Smuzhiyun 	.vsel_mask	= S2MPS11_LDO_VSEL_MASK,	\
369*4882a593Smuzhiyun 	.enable_reg	= S2MPS11_REG_L1CTRL + num - 1,	\
370*4882a593Smuzhiyun 	.enable_mask	= S2MPS11_ENABLE_MASK		\
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun #define regulator_desc_s2mps11_buck1_4(num) {			\
374*4882a593Smuzhiyun 	.name		= "BUCK"#num,				\
375*4882a593Smuzhiyun 	.id		= S2MPS11_BUCK##num,			\
376*4882a593Smuzhiyun 	.ops		= &s2mps11_buck_ops,			\
377*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,			\
378*4882a593Smuzhiyun 	.owner		= THIS_MODULE,				\
379*4882a593Smuzhiyun 	.min_uV		= MIN_650_MV,				\
380*4882a593Smuzhiyun 	.uV_step	= STEP_6_25_MV,				\
381*4882a593Smuzhiyun 	.linear_min_sel	= 8,					\
382*4882a593Smuzhiyun 	.n_voltages	= S2MPS11_BUCK12346_N_VOLTAGES,		\
383*4882a593Smuzhiyun 	.ramp_delay	= S2MPS11_RAMP_DELAY,			\
384*4882a593Smuzhiyun 	.vsel_reg	= S2MPS11_REG_B1CTRL2 + (num - 1) * 2,	\
385*4882a593Smuzhiyun 	.vsel_mask	= S2MPS11_BUCK_VSEL_MASK,		\
386*4882a593Smuzhiyun 	.enable_reg	= S2MPS11_REG_B1CTRL1 + (num - 1) * 2,	\
387*4882a593Smuzhiyun 	.enable_mask	= S2MPS11_ENABLE_MASK			\
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun #define regulator_desc_s2mps11_buck5 {				\
391*4882a593Smuzhiyun 	.name		= "BUCK5",				\
392*4882a593Smuzhiyun 	.id		= S2MPS11_BUCK5,			\
393*4882a593Smuzhiyun 	.ops		= &s2mps11_buck_ops,			\
394*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,			\
395*4882a593Smuzhiyun 	.owner		= THIS_MODULE,				\
396*4882a593Smuzhiyun 	.min_uV		= MIN_650_MV,				\
397*4882a593Smuzhiyun 	.uV_step	= STEP_6_25_MV,				\
398*4882a593Smuzhiyun 	.linear_min_sel	= 8,					\
399*4882a593Smuzhiyun 	.n_voltages	= S2MPS11_BUCK5_N_VOLTAGES,		\
400*4882a593Smuzhiyun 	.ramp_delay	= S2MPS11_RAMP_DELAY,			\
401*4882a593Smuzhiyun 	.vsel_reg	= S2MPS11_REG_B5CTRL2,			\
402*4882a593Smuzhiyun 	.vsel_mask	= S2MPS11_BUCK_VSEL_MASK,		\
403*4882a593Smuzhiyun 	.enable_reg	= S2MPS11_REG_B5CTRL1,			\
404*4882a593Smuzhiyun 	.enable_mask	= S2MPS11_ENABLE_MASK			\
405*4882a593Smuzhiyun }
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun #define regulator_desc_s2mps11_buck67810(num, min, step, min_sel, voltages) {	\
408*4882a593Smuzhiyun 	.name		= "BUCK"#num,				\
409*4882a593Smuzhiyun 	.id		= S2MPS11_BUCK##num,			\
410*4882a593Smuzhiyun 	.ops		= &s2mps11_buck_ops,			\
411*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,			\
412*4882a593Smuzhiyun 	.owner		= THIS_MODULE,				\
413*4882a593Smuzhiyun 	.min_uV		= min,					\
414*4882a593Smuzhiyun 	.uV_step	= step,					\
415*4882a593Smuzhiyun 	.linear_min_sel	= min_sel,				\
416*4882a593Smuzhiyun 	.n_voltages	= voltages,				\
417*4882a593Smuzhiyun 	.ramp_delay	= S2MPS11_RAMP_DELAY,			\
418*4882a593Smuzhiyun 	.vsel_reg	= S2MPS11_REG_B6CTRL2 + (num - 6) * 2,	\
419*4882a593Smuzhiyun 	.vsel_mask	= S2MPS11_BUCK_VSEL_MASK,		\
420*4882a593Smuzhiyun 	.enable_reg	= S2MPS11_REG_B6CTRL1 + (num - 6) * 2,	\
421*4882a593Smuzhiyun 	.enable_mask	= S2MPS11_ENABLE_MASK			\
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun #define regulator_desc_s2mps11_buck9 {				\
425*4882a593Smuzhiyun 	.name		= "BUCK9",				\
426*4882a593Smuzhiyun 	.id		= S2MPS11_BUCK9,			\
427*4882a593Smuzhiyun 	.ops		= &s2mps11_buck_ops,			\
428*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,			\
429*4882a593Smuzhiyun 	.owner		= THIS_MODULE,				\
430*4882a593Smuzhiyun 	.min_uV		= MIN_3000_MV,				\
431*4882a593Smuzhiyun 	.uV_step	= STEP_25_MV,				\
432*4882a593Smuzhiyun 	.n_voltages	= S2MPS11_BUCK9_N_VOLTAGES,		\
433*4882a593Smuzhiyun 	.ramp_delay	= S2MPS11_RAMP_DELAY,			\
434*4882a593Smuzhiyun 	.vsel_reg	= S2MPS11_REG_B9CTRL2,			\
435*4882a593Smuzhiyun 	.vsel_mask	= S2MPS11_BUCK9_VSEL_MASK,		\
436*4882a593Smuzhiyun 	.enable_reg	= S2MPS11_REG_B9CTRL1,			\
437*4882a593Smuzhiyun 	.enable_mask	= S2MPS11_ENABLE_MASK			\
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun static const struct regulator_desc s2mps11_regulators[] = {
441*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(1, STEP_25_MV),
442*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(2, STEP_50_MV),
443*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(3, STEP_50_MV),
444*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(4, STEP_50_MV),
445*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(5, STEP_50_MV),
446*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(6, STEP_25_MV),
447*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(7, STEP_50_MV),
448*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(8, STEP_50_MV),
449*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(9, STEP_50_MV),
450*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(10, STEP_50_MV),
451*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(11, STEP_25_MV),
452*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(12, STEP_50_MV),
453*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(13, STEP_50_MV),
454*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(14, STEP_50_MV),
455*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(15, STEP_50_MV),
456*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(16, STEP_50_MV),
457*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(17, STEP_50_MV),
458*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(18, STEP_50_MV),
459*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(19, STEP_50_MV),
460*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(20, STEP_50_MV),
461*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(21, STEP_50_MV),
462*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(22, STEP_25_MV),
463*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(23, STEP_25_MV),
464*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(24, STEP_50_MV),
465*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(25, STEP_50_MV),
466*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(26, STEP_50_MV),
467*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(27, STEP_25_MV),
468*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(28, STEP_50_MV),
469*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(29, STEP_50_MV),
470*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(30, STEP_50_MV),
471*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(31, STEP_50_MV),
472*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(32, STEP_50_MV),
473*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(33, STEP_50_MV),
474*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(34, STEP_50_MV),
475*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(35, STEP_25_MV),
476*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(36, STEP_50_MV),
477*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(37, STEP_50_MV),
478*4882a593Smuzhiyun 	regulator_desc_s2mps11_ldo(38, STEP_50_MV),
479*4882a593Smuzhiyun 	regulator_desc_s2mps11_buck1_4(1),
480*4882a593Smuzhiyun 	regulator_desc_s2mps11_buck1_4(2),
481*4882a593Smuzhiyun 	regulator_desc_s2mps11_buck1_4(3),
482*4882a593Smuzhiyun 	regulator_desc_s2mps11_buck1_4(4),
483*4882a593Smuzhiyun 	regulator_desc_s2mps11_buck5,
484*4882a593Smuzhiyun 	regulator_desc_s2mps11_buck67810(6, MIN_650_MV, STEP_6_25_MV, 8,
485*4882a593Smuzhiyun 					 S2MPS11_BUCK12346_N_VOLTAGES),
486*4882a593Smuzhiyun 	regulator_desc_s2mps11_buck67810(7, MIN_750_MV, STEP_12_5_MV, 0,
487*4882a593Smuzhiyun 					 S2MPS11_BUCK7810_N_VOLTAGES),
488*4882a593Smuzhiyun 	regulator_desc_s2mps11_buck67810(8, MIN_750_MV, STEP_12_5_MV, 0,
489*4882a593Smuzhiyun 					 S2MPS11_BUCK7810_N_VOLTAGES),
490*4882a593Smuzhiyun 	regulator_desc_s2mps11_buck9,
491*4882a593Smuzhiyun 	regulator_desc_s2mps11_buck67810(10, MIN_750_MV, STEP_12_5_MV, 0,
492*4882a593Smuzhiyun 					 S2MPS11_BUCK7810_N_VOLTAGES),
493*4882a593Smuzhiyun };
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun static const struct regulator_ops s2mps14_reg_ops;
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun #define regulator_desc_s2mps13_ldo(num, min, step, min_sel) {	\
498*4882a593Smuzhiyun 	.name		= "LDO"#num,				\
499*4882a593Smuzhiyun 	.id		= S2MPS13_LDO##num,			\
500*4882a593Smuzhiyun 	.ops		= &s2mps14_reg_ops,			\
501*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,			\
502*4882a593Smuzhiyun 	.owner		= THIS_MODULE,				\
503*4882a593Smuzhiyun 	.min_uV		= min,					\
504*4882a593Smuzhiyun 	.uV_step	= step,					\
505*4882a593Smuzhiyun 	.linear_min_sel	= min_sel,				\
506*4882a593Smuzhiyun 	.n_voltages	= S2MPS14_LDO_N_VOLTAGES,		\
507*4882a593Smuzhiyun 	.vsel_reg	= S2MPS13_REG_L1CTRL + num - 1,		\
508*4882a593Smuzhiyun 	.vsel_mask	= S2MPS14_LDO_VSEL_MASK,		\
509*4882a593Smuzhiyun 	.enable_reg	= S2MPS13_REG_L1CTRL + num - 1,		\
510*4882a593Smuzhiyun 	.enable_mask	= S2MPS14_ENABLE_MASK			\
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun 
513*4882a593Smuzhiyun #define regulator_desc_s2mps13_buck(num, min, step, min_sel) {	\
514*4882a593Smuzhiyun 	.name		= "BUCK"#num,				\
515*4882a593Smuzhiyun 	.id		= S2MPS13_BUCK##num,			\
516*4882a593Smuzhiyun 	.ops		= &s2mps14_reg_ops,			\
517*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,			\
518*4882a593Smuzhiyun 	.owner		= THIS_MODULE,				\
519*4882a593Smuzhiyun 	.min_uV		= min,					\
520*4882a593Smuzhiyun 	.uV_step	= step,					\
521*4882a593Smuzhiyun 	.linear_min_sel	= min_sel,				\
522*4882a593Smuzhiyun 	.n_voltages	= S2MPS14_BUCK_N_VOLTAGES,		\
523*4882a593Smuzhiyun 	.ramp_delay	= S2MPS13_BUCK_RAMP_DELAY,		\
524*4882a593Smuzhiyun 	.vsel_reg	= S2MPS13_REG_B1OUT + (num - 1) * 2,	\
525*4882a593Smuzhiyun 	.vsel_mask	= S2MPS14_BUCK_VSEL_MASK,		\
526*4882a593Smuzhiyun 	.enable_reg	= S2MPS13_REG_B1CTRL + (num - 1) * 2,	\
527*4882a593Smuzhiyun 	.enable_mask	= S2MPS14_ENABLE_MASK			\
528*4882a593Smuzhiyun }
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun #define regulator_desc_s2mps13_buck7(num, min, step, min_sel) {	\
531*4882a593Smuzhiyun 	.name		= "BUCK"#num,				\
532*4882a593Smuzhiyun 	.id		= S2MPS13_BUCK##num,			\
533*4882a593Smuzhiyun 	.ops		= &s2mps14_reg_ops,			\
534*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,			\
535*4882a593Smuzhiyun 	.owner		= THIS_MODULE,				\
536*4882a593Smuzhiyun 	.min_uV		= min,					\
537*4882a593Smuzhiyun 	.uV_step	= step,					\
538*4882a593Smuzhiyun 	.linear_min_sel	= min_sel,				\
539*4882a593Smuzhiyun 	.n_voltages	= S2MPS14_BUCK_N_VOLTAGES,		\
540*4882a593Smuzhiyun 	.ramp_delay	= S2MPS13_BUCK_RAMP_DELAY,		\
541*4882a593Smuzhiyun 	.vsel_reg	= S2MPS13_REG_B1OUT + (num) * 2 - 1,	\
542*4882a593Smuzhiyun 	.vsel_mask	= S2MPS14_BUCK_VSEL_MASK,		\
543*4882a593Smuzhiyun 	.enable_reg	= S2MPS13_REG_B1CTRL + (num - 1) * 2,	\
544*4882a593Smuzhiyun 	.enable_mask	= S2MPS14_ENABLE_MASK			\
545*4882a593Smuzhiyun }
546*4882a593Smuzhiyun 
547*4882a593Smuzhiyun #define regulator_desc_s2mps13_buck8_10(num, min, step, min_sel) {	\
548*4882a593Smuzhiyun 	.name		= "BUCK"#num,				\
549*4882a593Smuzhiyun 	.id		= S2MPS13_BUCK##num,			\
550*4882a593Smuzhiyun 	.ops		= &s2mps14_reg_ops,			\
551*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,			\
552*4882a593Smuzhiyun 	.owner		= THIS_MODULE,				\
553*4882a593Smuzhiyun 	.min_uV		= min,					\
554*4882a593Smuzhiyun 	.uV_step	= step,					\
555*4882a593Smuzhiyun 	.linear_min_sel	= min_sel,				\
556*4882a593Smuzhiyun 	.n_voltages	= S2MPS14_BUCK_N_VOLTAGES,		\
557*4882a593Smuzhiyun 	.ramp_delay	= S2MPS13_BUCK_RAMP_DELAY,		\
558*4882a593Smuzhiyun 	.vsel_reg	= S2MPS13_REG_B1OUT + (num) * 2 - 1,	\
559*4882a593Smuzhiyun 	.vsel_mask	= S2MPS14_BUCK_VSEL_MASK,		\
560*4882a593Smuzhiyun 	.enable_reg	= S2MPS13_REG_B1CTRL + (num) * 2 - 1,	\
561*4882a593Smuzhiyun 	.enable_mask	= S2MPS14_ENABLE_MASK			\
562*4882a593Smuzhiyun }
563*4882a593Smuzhiyun 
564*4882a593Smuzhiyun static const struct regulator_desc s2mps13_regulators[] = {
565*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(1,  MIN_800_MV,  STEP_12_5_MV, 0x00),
566*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(2,  MIN_1400_MV, STEP_50_MV,   0x0C),
567*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(3,  MIN_1000_MV, STEP_25_MV,   0x08),
568*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(4,  MIN_800_MV,  STEP_12_5_MV, 0x00),
569*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(5,  MIN_800_MV,  STEP_12_5_MV, 0x00),
570*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(6,  MIN_800_MV,  STEP_12_5_MV, 0x00),
571*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(7,  MIN_1000_MV, STEP_25_MV,   0x08),
572*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(8,  MIN_1000_MV, STEP_25_MV,   0x08),
573*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(9,  MIN_1000_MV, STEP_25_MV,   0x08),
574*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(10, MIN_1400_MV, STEP_50_MV,   0x0C),
575*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(11, MIN_800_MV,  STEP_25_MV,   0x10),
576*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(12, MIN_800_MV,  STEP_25_MV,   0x10),
577*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(13, MIN_800_MV,  STEP_25_MV,   0x10),
578*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(14, MIN_800_MV,  STEP_12_5_MV, 0x00),
579*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(15, MIN_800_MV,  STEP_12_5_MV, 0x00),
580*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(16, MIN_1400_MV, STEP_50_MV,   0x0C),
581*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(17, MIN_1400_MV, STEP_50_MV,   0x0C),
582*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(18, MIN_1000_MV, STEP_25_MV,   0x08),
583*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(19, MIN_1000_MV, STEP_25_MV,   0x08),
584*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(20, MIN_1400_MV, STEP_50_MV,   0x0C),
585*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(21, MIN_1000_MV, STEP_25_MV,   0x08),
586*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(22, MIN_1000_MV, STEP_25_MV,   0x08),
587*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(23, MIN_800_MV,  STEP_12_5_MV, 0x00),
588*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(24, MIN_800_MV,  STEP_12_5_MV, 0x00),
589*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(25, MIN_1400_MV, STEP_50_MV,   0x0C),
590*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(26, MIN_1400_MV, STEP_50_MV,   0x0C),
591*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(27, MIN_1400_MV, STEP_50_MV,   0x0C),
592*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(28, MIN_1000_MV, STEP_25_MV,   0x08),
593*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(29, MIN_1400_MV, STEP_50_MV,   0x0C),
594*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(30, MIN_1400_MV, STEP_50_MV,   0x0C),
595*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(31, MIN_1000_MV, STEP_25_MV,   0x08),
596*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(32, MIN_1000_MV, STEP_25_MV,   0x08),
597*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(33, MIN_1400_MV, STEP_50_MV,   0x0C),
598*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(34, MIN_1000_MV, STEP_25_MV,   0x08),
599*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(35, MIN_1400_MV, STEP_50_MV,   0x0C),
600*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(36, MIN_800_MV,  STEP_12_5_MV, 0x00),
601*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(37, MIN_1000_MV, STEP_25_MV,   0x08),
602*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(38, MIN_1400_MV, STEP_50_MV,   0x0C),
603*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(39, MIN_1000_MV, STEP_25_MV,   0x08),
604*4882a593Smuzhiyun 	regulator_desc_s2mps13_ldo(40, MIN_1400_MV, STEP_50_MV,   0x0C),
605*4882a593Smuzhiyun 	regulator_desc_s2mps13_buck(1,  MIN_500_MV,  STEP_6_25_MV, 0x10),
606*4882a593Smuzhiyun 	regulator_desc_s2mps13_buck(2,  MIN_500_MV,  STEP_6_25_MV, 0x10),
607*4882a593Smuzhiyun 	regulator_desc_s2mps13_buck(3,  MIN_500_MV,  STEP_6_25_MV, 0x10),
608*4882a593Smuzhiyun 	regulator_desc_s2mps13_buck(4,  MIN_500_MV,  STEP_6_25_MV, 0x10),
609*4882a593Smuzhiyun 	regulator_desc_s2mps13_buck(5,  MIN_500_MV,  STEP_6_25_MV, 0x10),
610*4882a593Smuzhiyun 	regulator_desc_s2mps13_buck(6,  MIN_500_MV,  STEP_6_25_MV, 0x10),
611*4882a593Smuzhiyun 	regulator_desc_s2mps13_buck7(7,  MIN_500_MV,  STEP_6_25_MV, 0x10),
612*4882a593Smuzhiyun 	regulator_desc_s2mps13_buck8_10(8,  MIN_1000_MV, STEP_12_5_MV, 0x20),
613*4882a593Smuzhiyun 	regulator_desc_s2mps13_buck8_10(9,  MIN_1000_MV, STEP_12_5_MV, 0x20),
614*4882a593Smuzhiyun 	regulator_desc_s2mps13_buck8_10(10, MIN_500_MV,  STEP_6_25_MV, 0x10),
615*4882a593Smuzhiyun };
616*4882a593Smuzhiyun 
617*4882a593Smuzhiyun static const struct regulator_ops s2mps14_reg_ops = {
618*4882a593Smuzhiyun 	.list_voltage		= regulator_list_voltage_linear,
619*4882a593Smuzhiyun 	.map_voltage		= regulator_map_voltage_linear,
620*4882a593Smuzhiyun 	.is_enabled		= regulator_is_enabled_regmap,
621*4882a593Smuzhiyun 	.enable			= s2mps11_regulator_enable,
622*4882a593Smuzhiyun 	.disable		= regulator_disable_regmap,
623*4882a593Smuzhiyun 	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
624*4882a593Smuzhiyun 	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
625*4882a593Smuzhiyun 	.set_voltage_time_sel	= regulator_set_voltage_time_sel,
626*4882a593Smuzhiyun 	.set_suspend_disable	= s2mps11_regulator_set_suspend_disable,
627*4882a593Smuzhiyun };
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun #define regulator_desc_s2mps14_ldo(num, min, step) {	\
630*4882a593Smuzhiyun 	.name		= "LDO"#num,			\
631*4882a593Smuzhiyun 	.id		= S2MPS14_LDO##num,		\
632*4882a593Smuzhiyun 	.ops		= &s2mps14_reg_ops,		\
633*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,		\
634*4882a593Smuzhiyun 	.owner		= THIS_MODULE,			\
635*4882a593Smuzhiyun 	.min_uV		= min,				\
636*4882a593Smuzhiyun 	.uV_step	= step,				\
637*4882a593Smuzhiyun 	.n_voltages	= S2MPS14_LDO_N_VOLTAGES,	\
638*4882a593Smuzhiyun 	.vsel_reg	= S2MPS14_REG_L1CTRL + num - 1,	\
639*4882a593Smuzhiyun 	.vsel_mask	= S2MPS14_LDO_VSEL_MASK,	\
640*4882a593Smuzhiyun 	.enable_reg	= S2MPS14_REG_L1CTRL + num - 1,	\
641*4882a593Smuzhiyun 	.enable_mask	= S2MPS14_ENABLE_MASK		\
642*4882a593Smuzhiyun }
643*4882a593Smuzhiyun 
644*4882a593Smuzhiyun #define regulator_desc_s2mps14_buck(num, min, step, min_sel) {	\
645*4882a593Smuzhiyun 	.name		= "BUCK"#num,				\
646*4882a593Smuzhiyun 	.id		= S2MPS14_BUCK##num,			\
647*4882a593Smuzhiyun 	.ops		= &s2mps14_reg_ops,			\
648*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,			\
649*4882a593Smuzhiyun 	.owner		= THIS_MODULE,				\
650*4882a593Smuzhiyun 	.min_uV		= min,					\
651*4882a593Smuzhiyun 	.uV_step	= step,					\
652*4882a593Smuzhiyun 	.n_voltages	= S2MPS14_BUCK_N_VOLTAGES,		\
653*4882a593Smuzhiyun 	.linear_min_sel = min_sel,				\
654*4882a593Smuzhiyun 	.ramp_delay	= S2MPS14_BUCK_RAMP_DELAY,		\
655*4882a593Smuzhiyun 	.vsel_reg	= S2MPS14_REG_B1CTRL2 + (num - 1) * 2,	\
656*4882a593Smuzhiyun 	.vsel_mask	= S2MPS14_BUCK_VSEL_MASK,		\
657*4882a593Smuzhiyun 	.enable_reg	= S2MPS14_REG_B1CTRL1 + (num - 1) * 2,	\
658*4882a593Smuzhiyun 	.enable_mask	= S2MPS14_ENABLE_MASK			\
659*4882a593Smuzhiyun }
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun static const struct regulator_desc s2mps14_regulators[] = {
662*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(1, MIN_800_MV, STEP_12_5_MV),
663*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(2, MIN_800_MV, STEP_12_5_MV),
664*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(3, MIN_800_MV, STEP_25_MV),
665*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(4, MIN_800_MV, STEP_25_MV),
666*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(5, MIN_800_MV, STEP_12_5_MV),
667*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(6, MIN_800_MV, STEP_12_5_MV),
668*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(7, MIN_800_MV, STEP_25_MV),
669*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(8, MIN_1800_MV, STEP_25_MV),
670*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(9, MIN_800_MV, STEP_12_5_MV),
671*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(10, MIN_800_MV, STEP_12_5_MV),
672*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(11, MIN_800_MV, STEP_25_MV),
673*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(12, MIN_1800_MV, STEP_25_MV),
674*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(13, MIN_1800_MV, STEP_25_MV),
675*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(14, MIN_1800_MV, STEP_25_MV),
676*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(15, MIN_1800_MV, STEP_25_MV),
677*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(16, MIN_1800_MV, STEP_25_MV),
678*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(17, MIN_1800_MV, STEP_25_MV),
679*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(18, MIN_1800_MV, STEP_25_MV),
680*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(19, MIN_800_MV, STEP_25_MV),
681*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(20, MIN_800_MV, STEP_25_MV),
682*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(21, MIN_800_MV, STEP_25_MV),
683*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(22, MIN_800_MV, STEP_12_5_MV),
684*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(23, MIN_800_MV, STEP_25_MV),
685*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(24, MIN_1800_MV, STEP_25_MV),
686*4882a593Smuzhiyun 	regulator_desc_s2mps14_ldo(25, MIN_1800_MV, STEP_25_MV),
687*4882a593Smuzhiyun 	regulator_desc_s2mps14_buck(1, MIN_600_MV, STEP_6_25_MV,
688*4882a593Smuzhiyun 				    S2MPS14_BUCK1235_START_SEL),
689*4882a593Smuzhiyun 	regulator_desc_s2mps14_buck(2, MIN_600_MV, STEP_6_25_MV,
690*4882a593Smuzhiyun 				    S2MPS14_BUCK1235_START_SEL),
691*4882a593Smuzhiyun 	regulator_desc_s2mps14_buck(3, MIN_600_MV, STEP_6_25_MV,
692*4882a593Smuzhiyun 				    S2MPS14_BUCK1235_START_SEL),
693*4882a593Smuzhiyun 	regulator_desc_s2mps14_buck(4, MIN_1400_MV, STEP_12_5_MV,
694*4882a593Smuzhiyun 				    S2MPS14_BUCK4_START_SEL),
695*4882a593Smuzhiyun 	regulator_desc_s2mps14_buck(5, MIN_600_MV, STEP_6_25_MV,
696*4882a593Smuzhiyun 				    S2MPS14_BUCK1235_START_SEL),
697*4882a593Smuzhiyun };
698*4882a593Smuzhiyun 
699*4882a593Smuzhiyun static const struct regulator_ops s2mps15_reg_ldo_ops = {
700*4882a593Smuzhiyun 	.list_voltage		= regulator_list_voltage_linear_range,
701*4882a593Smuzhiyun 	.map_voltage		= regulator_map_voltage_linear_range,
702*4882a593Smuzhiyun 	.is_enabled		= regulator_is_enabled_regmap,
703*4882a593Smuzhiyun 	.enable			= regulator_enable_regmap,
704*4882a593Smuzhiyun 	.disable		= regulator_disable_regmap,
705*4882a593Smuzhiyun 	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
706*4882a593Smuzhiyun 	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
707*4882a593Smuzhiyun };
708*4882a593Smuzhiyun 
709*4882a593Smuzhiyun static const struct regulator_ops s2mps15_reg_buck_ops = {
710*4882a593Smuzhiyun 	.list_voltage		= regulator_list_voltage_linear_range,
711*4882a593Smuzhiyun 	.map_voltage		= regulator_map_voltage_linear_range,
712*4882a593Smuzhiyun 	.is_enabled		= regulator_is_enabled_regmap,
713*4882a593Smuzhiyun 	.enable			= regulator_enable_regmap,
714*4882a593Smuzhiyun 	.disable		= regulator_disable_regmap,
715*4882a593Smuzhiyun 	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
716*4882a593Smuzhiyun 	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
717*4882a593Smuzhiyun 	.set_voltage_time_sel	= regulator_set_voltage_time_sel,
718*4882a593Smuzhiyun };
719*4882a593Smuzhiyun 
720*4882a593Smuzhiyun #define regulator_desc_s2mps15_ldo(num, range) {	\
721*4882a593Smuzhiyun 	.name		= "LDO"#num,			\
722*4882a593Smuzhiyun 	.id		= S2MPS15_LDO##num,		\
723*4882a593Smuzhiyun 	.ops		= &s2mps15_reg_ldo_ops,		\
724*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,		\
725*4882a593Smuzhiyun 	.owner		= THIS_MODULE,			\
726*4882a593Smuzhiyun 	.linear_ranges	= range,			\
727*4882a593Smuzhiyun 	.n_linear_ranges = ARRAY_SIZE(range),		\
728*4882a593Smuzhiyun 	.n_voltages	= S2MPS15_LDO_N_VOLTAGES,	\
729*4882a593Smuzhiyun 	.vsel_reg	= S2MPS15_REG_L1CTRL + num - 1,	\
730*4882a593Smuzhiyun 	.vsel_mask	= S2MPS15_LDO_VSEL_MASK,	\
731*4882a593Smuzhiyun 	.enable_reg	= S2MPS15_REG_L1CTRL + num - 1,	\
732*4882a593Smuzhiyun 	.enable_mask	= S2MPS15_ENABLE_MASK		\
733*4882a593Smuzhiyun }
734*4882a593Smuzhiyun 
735*4882a593Smuzhiyun #define regulator_desc_s2mps15_buck(num, range) {			\
736*4882a593Smuzhiyun 	.name		= "BUCK"#num,					\
737*4882a593Smuzhiyun 	.id		= S2MPS15_BUCK##num,				\
738*4882a593Smuzhiyun 	.ops		= &s2mps15_reg_buck_ops,			\
739*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,				\
740*4882a593Smuzhiyun 	.owner		= THIS_MODULE,					\
741*4882a593Smuzhiyun 	.linear_ranges	= range,					\
742*4882a593Smuzhiyun 	.n_linear_ranges = ARRAY_SIZE(range),				\
743*4882a593Smuzhiyun 	.ramp_delay	= 12500,					\
744*4882a593Smuzhiyun 	.n_voltages	= S2MPS15_BUCK_N_VOLTAGES,			\
745*4882a593Smuzhiyun 	.vsel_reg	= S2MPS15_REG_B1CTRL2 + ((num - 1) * 2),	\
746*4882a593Smuzhiyun 	.vsel_mask	= S2MPS15_BUCK_VSEL_MASK,			\
747*4882a593Smuzhiyun 	.enable_reg	= S2MPS15_REG_B1CTRL1 + ((num - 1) * 2),	\
748*4882a593Smuzhiyun 	.enable_mask	= S2MPS15_ENABLE_MASK				\
749*4882a593Smuzhiyun }
750*4882a593Smuzhiyun 
751*4882a593Smuzhiyun /* voltage range for s2mps15 LDO 3, 5, 15, 16, 18, 20, 23 and 27 */
752*4882a593Smuzhiyun static const struct linear_range s2mps15_ldo_voltage_ranges1[] = {
753*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE(1000000, 0xc, 0x38, 25000),
754*4882a593Smuzhiyun };
755*4882a593Smuzhiyun 
756*4882a593Smuzhiyun /* voltage range for s2mps15 LDO 2, 6, 14, 17, 19, 21, 24 and 25 */
757*4882a593Smuzhiyun static const struct linear_range s2mps15_ldo_voltage_ranges2[] = {
758*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE(1800000, 0x0, 0x3f, 25000),
759*4882a593Smuzhiyun };
760*4882a593Smuzhiyun 
761*4882a593Smuzhiyun /* voltage range for s2mps15 LDO 4, 11, 12, 13, 22 and 26 */
762*4882a593Smuzhiyun static const struct linear_range s2mps15_ldo_voltage_ranges3[] = {
763*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE(700000, 0x0, 0x34, 12500),
764*4882a593Smuzhiyun };
765*4882a593Smuzhiyun 
766*4882a593Smuzhiyun /* voltage range for s2mps15 LDO 7, 8, 9 and 10 */
767*4882a593Smuzhiyun static const struct linear_range s2mps15_ldo_voltage_ranges4[] = {
768*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE(700000, 0x10, 0x20, 25000),
769*4882a593Smuzhiyun };
770*4882a593Smuzhiyun 
771*4882a593Smuzhiyun /* voltage range for s2mps15 LDO 1 */
772*4882a593Smuzhiyun static const struct linear_range s2mps15_ldo_voltage_ranges5[] = {
773*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE(500000, 0x0, 0x20, 12500),
774*4882a593Smuzhiyun };
775*4882a593Smuzhiyun 
776*4882a593Smuzhiyun /* voltage range for s2mps15 BUCK 1, 2, 3, 4, 5, 6 and 7 */
777*4882a593Smuzhiyun static const struct linear_range s2mps15_buck_voltage_ranges1[] = {
778*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE(500000, 0x20, 0xc0, 6250),
779*4882a593Smuzhiyun };
780*4882a593Smuzhiyun 
781*4882a593Smuzhiyun /* voltage range for s2mps15 BUCK 8, 9 and 10 */
782*4882a593Smuzhiyun static const struct linear_range s2mps15_buck_voltage_ranges2[] = {
783*4882a593Smuzhiyun 	REGULATOR_LINEAR_RANGE(1000000, 0x20, 0x78, 12500),
784*4882a593Smuzhiyun };
785*4882a593Smuzhiyun 
786*4882a593Smuzhiyun static const struct regulator_desc s2mps15_regulators[] = {
787*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(1, s2mps15_ldo_voltage_ranges5),
788*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(2, s2mps15_ldo_voltage_ranges2),
789*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(3, s2mps15_ldo_voltage_ranges1),
790*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(4, s2mps15_ldo_voltage_ranges3),
791*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(5, s2mps15_ldo_voltage_ranges1),
792*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(6, s2mps15_ldo_voltage_ranges2),
793*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(7, s2mps15_ldo_voltage_ranges4),
794*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(8, s2mps15_ldo_voltage_ranges4),
795*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(9, s2mps15_ldo_voltage_ranges4),
796*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(10, s2mps15_ldo_voltage_ranges4),
797*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(11, s2mps15_ldo_voltage_ranges3),
798*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(12, s2mps15_ldo_voltage_ranges3),
799*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(13, s2mps15_ldo_voltage_ranges3),
800*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(14, s2mps15_ldo_voltage_ranges2),
801*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(15, s2mps15_ldo_voltage_ranges1),
802*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(16, s2mps15_ldo_voltage_ranges1),
803*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(17, s2mps15_ldo_voltage_ranges2),
804*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(18, s2mps15_ldo_voltage_ranges1),
805*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(19, s2mps15_ldo_voltage_ranges2),
806*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(20, s2mps15_ldo_voltage_ranges1),
807*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(21, s2mps15_ldo_voltage_ranges2),
808*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(22, s2mps15_ldo_voltage_ranges3),
809*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(23, s2mps15_ldo_voltage_ranges1),
810*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(24, s2mps15_ldo_voltage_ranges2),
811*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(25, s2mps15_ldo_voltage_ranges2),
812*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(26, s2mps15_ldo_voltage_ranges3),
813*4882a593Smuzhiyun 	regulator_desc_s2mps15_ldo(27, s2mps15_ldo_voltage_ranges1),
814*4882a593Smuzhiyun 	regulator_desc_s2mps15_buck(1, s2mps15_buck_voltage_ranges1),
815*4882a593Smuzhiyun 	regulator_desc_s2mps15_buck(2, s2mps15_buck_voltage_ranges1),
816*4882a593Smuzhiyun 	regulator_desc_s2mps15_buck(3, s2mps15_buck_voltage_ranges1),
817*4882a593Smuzhiyun 	regulator_desc_s2mps15_buck(4, s2mps15_buck_voltage_ranges1),
818*4882a593Smuzhiyun 	regulator_desc_s2mps15_buck(5, s2mps15_buck_voltage_ranges1),
819*4882a593Smuzhiyun 	regulator_desc_s2mps15_buck(6, s2mps15_buck_voltage_ranges1),
820*4882a593Smuzhiyun 	regulator_desc_s2mps15_buck(7, s2mps15_buck_voltage_ranges1),
821*4882a593Smuzhiyun 	regulator_desc_s2mps15_buck(8, s2mps15_buck_voltage_ranges2),
822*4882a593Smuzhiyun 	regulator_desc_s2mps15_buck(9, s2mps15_buck_voltage_ranges2),
823*4882a593Smuzhiyun 	regulator_desc_s2mps15_buck(10, s2mps15_buck_voltage_ranges2),
824*4882a593Smuzhiyun };
825*4882a593Smuzhiyun 
s2mps14_pmic_enable_ext_control(struct s2mps11_info * s2mps11,struct regulator_dev * rdev)826*4882a593Smuzhiyun static int s2mps14_pmic_enable_ext_control(struct s2mps11_info *s2mps11,
827*4882a593Smuzhiyun 		struct regulator_dev *rdev)
828*4882a593Smuzhiyun {
829*4882a593Smuzhiyun 	return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
830*4882a593Smuzhiyun 			rdev->desc->enable_mask, S2MPS14_ENABLE_EXT_CONTROL);
831*4882a593Smuzhiyun }
832*4882a593Smuzhiyun 
s2mps14_pmic_dt_parse_ext_control_gpio(struct platform_device * pdev,struct of_regulator_match * rdata,struct s2mps11_info * s2mps11)833*4882a593Smuzhiyun static void s2mps14_pmic_dt_parse_ext_control_gpio(struct platform_device *pdev,
834*4882a593Smuzhiyun 		struct of_regulator_match *rdata, struct s2mps11_info *s2mps11)
835*4882a593Smuzhiyun {
836*4882a593Smuzhiyun 	struct gpio_desc **gpio = s2mps11->ext_control_gpiod;
837*4882a593Smuzhiyun 	unsigned int i;
838*4882a593Smuzhiyun 	unsigned int valid_regulators[3] = { S2MPS14_LDO10, S2MPS14_LDO11,
839*4882a593Smuzhiyun 		S2MPS14_LDO12 };
840*4882a593Smuzhiyun 
841*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(valid_regulators); i++) {
842*4882a593Smuzhiyun 		unsigned int reg = valid_regulators[i];
843*4882a593Smuzhiyun 
844*4882a593Smuzhiyun 		if (!rdata[reg].init_data || !rdata[reg].of_node)
845*4882a593Smuzhiyun 			continue;
846*4882a593Smuzhiyun 
847*4882a593Smuzhiyun 		gpio[reg] = devm_fwnode_gpiod_get(&pdev->dev,
848*4882a593Smuzhiyun 				of_fwnode_handle(rdata[reg].of_node),
849*4882a593Smuzhiyun 				"samsung,ext-control",
850*4882a593Smuzhiyun 				GPIOD_OUT_HIGH | GPIOD_FLAGS_BIT_NONEXCLUSIVE,
851*4882a593Smuzhiyun 				"s2mps11-regulator");
852*4882a593Smuzhiyun 		if (PTR_ERR(gpio[reg]) == -ENOENT)
853*4882a593Smuzhiyun 			gpio[reg] = NULL;
854*4882a593Smuzhiyun 		else if (IS_ERR(gpio[reg])) {
855*4882a593Smuzhiyun 			dev_err(&pdev->dev, "Failed to get control GPIO for %d/%s\n",
856*4882a593Smuzhiyun 				reg, rdata[reg].name);
857*4882a593Smuzhiyun 			gpio[reg] = NULL;
858*4882a593Smuzhiyun 			continue;
859*4882a593Smuzhiyun 		}
860*4882a593Smuzhiyun 		if (gpio[reg])
861*4882a593Smuzhiyun 			dev_dbg(&pdev->dev, "Using GPIO for ext-control over %d/%s\n",
862*4882a593Smuzhiyun 				reg, rdata[reg].name);
863*4882a593Smuzhiyun 	}
864*4882a593Smuzhiyun }
865*4882a593Smuzhiyun 
s2mps11_pmic_dt_parse(struct platform_device * pdev,struct of_regulator_match * rdata,struct s2mps11_info * s2mps11,unsigned int rdev_num)866*4882a593Smuzhiyun static int s2mps11_pmic_dt_parse(struct platform_device *pdev,
867*4882a593Smuzhiyun 		struct of_regulator_match *rdata, struct s2mps11_info *s2mps11,
868*4882a593Smuzhiyun 		unsigned int rdev_num)
869*4882a593Smuzhiyun {
870*4882a593Smuzhiyun 	struct device_node *reg_np;
871*4882a593Smuzhiyun 
872*4882a593Smuzhiyun 	reg_np = of_get_child_by_name(pdev->dev.parent->of_node, "regulators");
873*4882a593Smuzhiyun 	if (!reg_np) {
874*4882a593Smuzhiyun 		dev_err(&pdev->dev, "could not find regulators sub-node\n");
875*4882a593Smuzhiyun 		return -EINVAL;
876*4882a593Smuzhiyun 	}
877*4882a593Smuzhiyun 
878*4882a593Smuzhiyun 	of_regulator_match(&pdev->dev, reg_np, rdata, rdev_num);
879*4882a593Smuzhiyun 	if (s2mps11->dev_type == S2MPS14X)
880*4882a593Smuzhiyun 		s2mps14_pmic_dt_parse_ext_control_gpio(pdev, rdata, s2mps11);
881*4882a593Smuzhiyun 
882*4882a593Smuzhiyun 	of_node_put(reg_np);
883*4882a593Smuzhiyun 
884*4882a593Smuzhiyun 	return 0;
885*4882a593Smuzhiyun }
886*4882a593Smuzhiyun 
s2mpu02_set_ramp_delay(struct regulator_dev * rdev,int ramp_delay)887*4882a593Smuzhiyun static int s2mpu02_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
888*4882a593Smuzhiyun {
889*4882a593Smuzhiyun 	unsigned int ramp_val, ramp_shift, ramp_reg;
890*4882a593Smuzhiyun 	int rdev_id = rdev_get_id(rdev);
891*4882a593Smuzhiyun 
892*4882a593Smuzhiyun 	switch (rdev_id) {
893*4882a593Smuzhiyun 	case S2MPU02_BUCK1:
894*4882a593Smuzhiyun 		ramp_shift = S2MPU02_BUCK1_RAMP_SHIFT;
895*4882a593Smuzhiyun 		break;
896*4882a593Smuzhiyun 	case S2MPU02_BUCK2:
897*4882a593Smuzhiyun 		ramp_shift = S2MPU02_BUCK2_RAMP_SHIFT;
898*4882a593Smuzhiyun 		break;
899*4882a593Smuzhiyun 	case S2MPU02_BUCK3:
900*4882a593Smuzhiyun 		ramp_shift = S2MPU02_BUCK3_RAMP_SHIFT;
901*4882a593Smuzhiyun 		break;
902*4882a593Smuzhiyun 	case S2MPU02_BUCK4:
903*4882a593Smuzhiyun 		ramp_shift = S2MPU02_BUCK4_RAMP_SHIFT;
904*4882a593Smuzhiyun 		break;
905*4882a593Smuzhiyun 	default:
906*4882a593Smuzhiyun 		return 0;
907*4882a593Smuzhiyun 	}
908*4882a593Smuzhiyun 	ramp_reg = S2MPU02_REG_RAMP1;
909*4882a593Smuzhiyun 	ramp_val = get_ramp_delay(ramp_delay);
910*4882a593Smuzhiyun 
911*4882a593Smuzhiyun 	return regmap_update_bits(rdev->regmap, ramp_reg,
912*4882a593Smuzhiyun 				  S2MPU02_BUCK1234_RAMP_MASK << ramp_shift,
913*4882a593Smuzhiyun 				  ramp_val << ramp_shift);
914*4882a593Smuzhiyun }
915*4882a593Smuzhiyun 
916*4882a593Smuzhiyun static const struct regulator_ops s2mpu02_ldo_ops = {
917*4882a593Smuzhiyun 	.list_voltage		= regulator_list_voltage_linear,
918*4882a593Smuzhiyun 	.map_voltage		= regulator_map_voltage_linear,
919*4882a593Smuzhiyun 	.is_enabled		= regulator_is_enabled_regmap,
920*4882a593Smuzhiyun 	.enable			= s2mps11_regulator_enable,
921*4882a593Smuzhiyun 	.disable		= regulator_disable_regmap,
922*4882a593Smuzhiyun 	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
923*4882a593Smuzhiyun 	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
924*4882a593Smuzhiyun 	.set_voltage_time_sel	= regulator_set_voltage_time_sel,
925*4882a593Smuzhiyun 	.set_suspend_disable	= s2mps11_regulator_set_suspend_disable,
926*4882a593Smuzhiyun };
927*4882a593Smuzhiyun 
928*4882a593Smuzhiyun static const struct regulator_ops s2mpu02_buck_ops = {
929*4882a593Smuzhiyun 	.list_voltage		= regulator_list_voltage_linear,
930*4882a593Smuzhiyun 	.map_voltage		= regulator_map_voltage_linear,
931*4882a593Smuzhiyun 	.is_enabled		= regulator_is_enabled_regmap,
932*4882a593Smuzhiyun 	.enable			= s2mps11_regulator_enable,
933*4882a593Smuzhiyun 	.disable		= regulator_disable_regmap,
934*4882a593Smuzhiyun 	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
935*4882a593Smuzhiyun 	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
936*4882a593Smuzhiyun 	.set_voltage_time_sel	= regulator_set_voltage_time_sel,
937*4882a593Smuzhiyun 	.set_suspend_disable	= s2mps11_regulator_set_suspend_disable,
938*4882a593Smuzhiyun 	.set_ramp_delay		= s2mpu02_set_ramp_delay,
939*4882a593Smuzhiyun };
940*4882a593Smuzhiyun 
941*4882a593Smuzhiyun #define regulator_desc_s2mpu02_ldo1(num) {		\
942*4882a593Smuzhiyun 	.name		= "LDO"#num,			\
943*4882a593Smuzhiyun 	.id		= S2MPU02_LDO##num,		\
944*4882a593Smuzhiyun 	.ops		= &s2mpu02_ldo_ops,		\
945*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,		\
946*4882a593Smuzhiyun 	.owner		= THIS_MODULE,			\
947*4882a593Smuzhiyun 	.min_uV		= S2MPU02_LDO_MIN_900MV,	\
948*4882a593Smuzhiyun 	.uV_step	= S2MPU02_LDO_STEP_12_5MV,	\
949*4882a593Smuzhiyun 	.linear_min_sel	= S2MPU02_LDO_GROUP1_START_SEL,	\
950*4882a593Smuzhiyun 	.n_voltages	= S2MPU02_LDO_N_VOLTAGES,	\
951*4882a593Smuzhiyun 	.vsel_reg	= S2MPU02_REG_L1CTRL,		\
952*4882a593Smuzhiyun 	.vsel_mask	= S2MPU02_LDO_VSEL_MASK,	\
953*4882a593Smuzhiyun 	.enable_reg	= S2MPU02_REG_L1CTRL,		\
954*4882a593Smuzhiyun 	.enable_mask	= S2MPU02_ENABLE_MASK		\
955*4882a593Smuzhiyun }
956*4882a593Smuzhiyun #define regulator_desc_s2mpu02_ldo2(num) {		\
957*4882a593Smuzhiyun 	.name		= "LDO"#num,			\
958*4882a593Smuzhiyun 	.id		= S2MPU02_LDO##num,		\
959*4882a593Smuzhiyun 	.ops		= &s2mpu02_ldo_ops,		\
960*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,		\
961*4882a593Smuzhiyun 	.owner		= THIS_MODULE,			\
962*4882a593Smuzhiyun 	.min_uV		= S2MPU02_LDO_MIN_1050MV,	\
963*4882a593Smuzhiyun 	.uV_step	= S2MPU02_LDO_STEP_25MV,	\
964*4882a593Smuzhiyun 	.linear_min_sel	= S2MPU02_LDO_GROUP2_START_SEL,	\
965*4882a593Smuzhiyun 	.n_voltages	= S2MPU02_LDO_N_VOLTAGES,	\
966*4882a593Smuzhiyun 	.vsel_reg	= S2MPU02_REG_L2CTRL1,		\
967*4882a593Smuzhiyun 	.vsel_mask	= S2MPU02_LDO_VSEL_MASK,	\
968*4882a593Smuzhiyun 	.enable_reg	= S2MPU02_REG_L2CTRL1,		\
969*4882a593Smuzhiyun 	.enable_mask	= S2MPU02_ENABLE_MASK		\
970*4882a593Smuzhiyun }
971*4882a593Smuzhiyun #define regulator_desc_s2mpu02_ldo3(num) {		\
972*4882a593Smuzhiyun 	.name		= "LDO"#num,			\
973*4882a593Smuzhiyun 	.id		= S2MPU02_LDO##num,		\
974*4882a593Smuzhiyun 	.ops		= &s2mpu02_ldo_ops,		\
975*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,		\
976*4882a593Smuzhiyun 	.owner		= THIS_MODULE,			\
977*4882a593Smuzhiyun 	.min_uV		= S2MPU02_LDO_MIN_900MV,	\
978*4882a593Smuzhiyun 	.uV_step	= S2MPU02_LDO_STEP_12_5MV,	\
979*4882a593Smuzhiyun 	.linear_min_sel	= S2MPU02_LDO_GROUP1_START_SEL,	\
980*4882a593Smuzhiyun 	.n_voltages	= S2MPU02_LDO_N_VOLTAGES,	\
981*4882a593Smuzhiyun 	.vsel_reg	= S2MPU02_REG_L3CTRL + num - 3,	\
982*4882a593Smuzhiyun 	.vsel_mask	= S2MPU02_LDO_VSEL_MASK,	\
983*4882a593Smuzhiyun 	.enable_reg	= S2MPU02_REG_L3CTRL + num - 3,	\
984*4882a593Smuzhiyun 	.enable_mask	= S2MPU02_ENABLE_MASK		\
985*4882a593Smuzhiyun }
986*4882a593Smuzhiyun #define regulator_desc_s2mpu02_ldo4(num) {		\
987*4882a593Smuzhiyun 	.name		= "LDO"#num,			\
988*4882a593Smuzhiyun 	.id		= S2MPU02_LDO##num,		\
989*4882a593Smuzhiyun 	.ops		= &s2mpu02_ldo_ops,		\
990*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,		\
991*4882a593Smuzhiyun 	.owner		= THIS_MODULE,			\
992*4882a593Smuzhiyun 	.min_uV		= S2MPU02_LDO_MIN_1050MV,	\
993*4882a593Smuzhiyun 	.uV_step	= S2MPU02_LDO_STEP_25MV,	\
994*4882a593Smuzhiyun 	.linear_min_sel	= S2MPU02_LDO_GROUP2_START_SEL,	\
995*4882a593Smuzhiyun 	.n_voltages	= S2MPU02_LDO_N_VOLTAGES,	\
996*4882a593Smuzhiyun 	.vsel_reg	= S2MPU02_REG_L3CTRL + num - 3,	\
997*4882a593Smuzhiyun 	.vsel_mask	= S2MPU02_LDO_VSEL_MASK,	\
998*4882a593Smuzhiyun 	.enable_reg	= S2MPU02_REG_L3CTRL + num - 3,	\
999*4882a593Smuzhiyun 	.enable_mask	= S2MPU02_ENABLE_MASK		\
1000*4882a593Smuzhiyun }
1001*4882a593Smuzhiyun #define regulator_desc_s2mpu02_ldo5(num) {		\
1002*4882a593Smuzhiyun 	.name		= "LDO"#num,			\
1003*4882a593Smuzhiyun 	.id		= S2MPU02_LDO##num,		\
1004*4882a593Smuzhiyun 	.ops		= &s2mpu02_ldo_ops,		\
1005*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,		\
1006*4882a593Smuzhiyun 	.owner		= THIS_MODULE,			\
1007*4882a593Smuzhiyun 	.min_uV		= S2MPU02_LDO_MIN_1600MV,	\
1008*4882a593Smuzhiyun 	.uV_step	= S2MPU02_LDO_STEP_50MV,	\
1009*4882a593Smuzhiyun 	.linear_min_sel	= S2MPU02_LDO_GROUP3_START_SEL,	\
1010*4882a593Smuzhiyun 	.n_voltages	= S2MPU02_LDO_N_VOLTAGES,	\
1011*4882a593Smuzhiyun 	.vsel_reg	= S2MPU02_REG_L3CTRL + num - 3,	\
1012*4882a593Smuzhiyun 	.vsel_mask	= S2MPU02_LDO_VSEL_MASK,	\
1013*4882a593Smuzhiyun 	.enable_reg	= S2MPU02_REG_L3CTRL + num - 3,	\
1014*4882a593Smuzhiyun 	.enable_mask	= S2MPU02_ENABLE_MASK		\
1015*4882a593Smuzhiyun }
1016*4882a593Smuzhiyun 
1017*4882a593Smuzhiyun #define regulator_desc_s2mpu02_buck1234(num) {			\
1018*4882a593Smuzhiyun 	.name		= "BUCK"#num,				\
1019*4882a593Smuzhiyun 	.id		= S2MPU02_BUCK##num,			\
1020*4882a593Smuzhiyun 	.ops		= &s2mpu02_buck_ops,			\
1021*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,			\
1022*4882a593Smuzhiyun 	.owner		= THIS_MODULE,				\
1023*4882a593Smuzhiyun 	.min_uV		= S2MPU02_BUCK1234_MIN_600MV,		\
1024*4882a593Smuzhiyun 	.uV_step	= S2MPU02_BUCK1234_STEP_6_25MV,		\
1025*4882a593Smuzhiyun 	.n_voltages	= S2MPU02_BUCK_N_VOLTAGES,		\
1026*4882a593Smuzhiyun 	.linear_min_sel = S2MPU02_BUCK1234_START_SEL,		\
1027*4882a593Smuzhiyun 	.ramp_delay	= S2MPU02_BUCK_RAMP_DELAY,		\
1028*4882a593Smuzhiyun 	.vsel_reg	= S2MPU02_REG_B1CTRL2 + (num - 1) * 2,	\
1029*4882a593Smuzhiyun 	.vsel_mask	= S2MPU02_BUCK_VSEL_MASK,		\
1030*4882a593Smuzhiyun 	.enable_reg	= S2MPU02_REG_B1CTRL1 + (num - 1) * 2,	\
1031*4882a593Smuzhiyun 	.enable_mask	= S2MPU02_ENABLE_MASK			\
1032*4882a593Smuzhiyun }
1033*4882a593Smuzhiyun #define regulator_desc_s2mpu02_buck5(num) {			\
1034*4882a593Smuzhiyun 	.name		= "BUCK"#num,				\
1035*4882a593Smuzhiyun 	.id		= S2MPU02_BUCK##num,			\
1036*4882a593Smuzhiyun 	.ops		= &s2mpu02_ldo_ops,			\
1037*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,			\
1038*4882a593Smuzhiyun 	.owner		= THIS_MODULE,				\
1039*4882a593Smuzhiyun 	.min_uV		= S2MPU02_BUCK5_MIN_1081_25MV,		\
1040*4882a593Smuzhiyun 	.uV_step	= S2MPU02_BUCK5_STEP_6_25MV,		\
1041*4882a593Smuzhiyun 	.n_voltages	= S2MPU02_BUCK_N_VOLTAGES,		\
1042*4882a593Smuzhiyun 	.linear_min_sel = S2MPU02_BUCK5_START_SEL,		\
1043*4882a593Smuzhiyun 	.ramp_delay	= S2MPU02_BUCK_RAMP_DELAY,		\
1044*4882a593Smuzhiyun 	.vsel_reg	= S2MPU02_REG_B5CTRL2,			\
1045*4882a593Smuzhiyun 	.vsel_mask	= S2MPU02_BUCK_VSEL_MASK,		\
1046*4882a593Smuzhiyun 	.enable_reg	= S2MPU02_REG_B5CTRL1,			\
1047*4882a593Smuzhiyun 	.enable_mask	= S2MPU02_ENABLE_MASK			\
1048*4882a593Smuzhiyun }
1049*4882a593Smuzhiyun #define regulator_desc_s2mpu02_buck6(num) {			\
1050*4882a593Smuzhiyun 	.name		= "BUCK"#num,				\
1051*4882a593Smuzhiyun 	.id		= S2MPU02_BUCK##num,			\
1052*4882a593Smuzhiyun 	.ops		= &s2mpu02_ldo_ops,			\
1053*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,			\
1054*4882a593Smuzhiyun 	.owner		= THIS_MODULE,				\
1055*4882a593Smuzhiyun 	.min_uV		= S2MPU02_BUCK6_MIN_1700MV,		\
1056*4882a593Smuzhiyun 	.uV_step	= S2MPU02_BUCK6_STEP_2_50MV,		\
1057*4882a593Smuzhiyun 	.n_voltages	= S2MPU02_BUCK_N_VOLTAGES,		\
1058*4882a593Smuzhiyun 	.linear_min_sel = S2MPU02_BUCK6_START_SEL,		\
1059*4882a593Smuzhiyun 	.ramp_delay	= S2MPU02_BUCK_RAMP_DELAY,		\
1060*4882a593Smuzhiyun 	.vsel_reg	= S2MPU02_REG_B6CTRL2,			\
1061*4882a593Smuzhiyun 	.vsel_mask	= S2MPU02_BUCK_VSEL_MASK,		\
1062*4882a593Smuzhiyun 	.enable_reg	= S2MPU02_REG_B6CTRL1,			\
1063*4882a593Smuzhiyun 	.enable_mask	= S2MPU02_ENABLE_MASK			\
1064*4882a593Smuzhiyun }
1065*4882a593Smuzhiyun #define regulator_desc_s2mpu02_buck7(num) {			\
1066*4882a593Smuzhiyun 	.name		= "BUCK"#num,				\
1067*4882a593Smuzhiyun 	.id		= S2MPU02_BUCK##num,			\
1068*4882a593Smuzhiyun 	.ops		= &s2mpu02_ldo_ops,			\
1069*4882a593Smuzhiyun 	.type		= REGULATOR_VOLTAGE,			\
1070*4882a593Smuzhiyun 	.owner		= THIS_MODULE,				\
1071*4882a593Smuzhiyun 	.min_uV		= S2MPU02_BUCK7_MIN_900MV,		\
1072*4882a593Smuzhiyun 	.uV_step	= S2MPU02_BUCK7_STEP_6_25MV,		\
1073*4882a593Smuzhiyun 	.n_voltages	= S2MPU02_BUCK_N_VOLTAGES,		\
1074*4882a593Smuzhiyun 	.linear_min_sel = S2MPU02_BUCK7_START_SEL,		\
1075*4882a593Smuzhiyun 	.ramp_delay	= S2MPU02_BUCK_RAMP_DELAY,		\
1076*4882a593Smuzhiyun 	.vsel_reg	= S2MPU02_REG_B7CTRL2,			\
1077*4882a593Smuzhiyun 	.vsel_mask	= S2MPU02_BUCK_VSEL_MASK,		\
1078*4882a593Smuzhiyun 	.enable_reg	= S2MPU02_REG_B7CTRL1,			\
1079*4882a593Smuzhiyun 	.enable_mask	= S2MPU02_ENABLE_MASK			\
1080*4882a593Smuzhiyun }
1081*4882a593Smuzhiyun 
1082*4882a593Smuzhiyun static const struct regulator_desc s2mpu02_regulators[] = {
1083*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo1(1),
1084*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo2(2),
1085*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo4(3),
1086*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo5(4),
1087*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo4(5),
1088*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo3(6),
1089*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo3(7),
1090*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo4(8),
1091*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo5(9),
1092*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo3(10),
1093*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo4(11),
1094*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo5(12),
1095*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo5(13),
1096*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo5(14),
1097*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo5(15),
1098*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo5(16),
1099*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo4(17),
1100*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo5(18),
1101*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo3(19),
1102*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo4(20),
1103*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo5(21),
1104*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo5(22),
1105*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo5(23),
1106*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo4(24),
1107*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo5(25),
1108*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo4(26),
1109*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo5(27),
1110*4882a593Smuzhiyun 	regulator_desc_s2mpu02_ldo5(28),
1111*4882a593Smuzhiyun 	regulator_desc_s2mpu02_buck1234(1),
1112*4882a593Smuzhiyun 	regulator_desc_s2mpu02_buck1234(2),
1113*4882a593Smuzhiyun 	regulator_desc_s2mpu02_buck1234(3),
1114*4882a593Smuzhiyun 	regulator_desc_s2mpu02_buck1234(4),
1115*4882a593Smuzhiyun 	regulator_desc_s2mpu02_buck5(5),
1116*4882a593Smuzhiyun 	regulator_desc_s2mpu02_buck6(6),
1117*4882a593Smuzhiyun 	regulator_desc_s2mpu02_buck7(7),
1118*4882a593Smuzhiyun };
1119*4882a593Smuzhiyun 
s2mps11_pmic_probe(struct platform_device * pdev)1120*4882a593Smuzhiyun static int s2mps11_pmic_probe(struct platform_device *pdev)
1121*4882a593Smuzhiyun {
1122*4882a593Smuzhiyun 	struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
1123*4882a593Smuzhiyun 	struct sec_platform_data *pdata = NULL;
1124*4882a593Smuzhiyun 	struct of_regulator_match *rdata = NULL;
1125*4882a593Smuzhiyun 	struct regulator_config config = { };
1126*4882a593Smuzhiyun 	struct s2mps11_info *s2mps11;
1127*4882a593Smuzhiyun 	unsigned int rdev_num = 0;
1128*4882a593Smuzhiyun 	int i, ret = 0;
1129*4882a593Smuzhiyun 	const struct regulator_desc *regulators;
1130*4882a593Smuzhiyun 
1131*4882a593Smuzhiyun 	s2mps11 = devm_kzalloc(&pdev->dev, sizeof(struct s2mps11_info),
1132*4882a593Smuzhiyun 				GFP_KERNEL);
1133*4882a593Smuzhiyun 	if (!s2mps11)
1134*4882a593Smuzhiyun 		return -ENOMEM;
1135*4882a593Smuzhiyun 
1136*4882a593Smuzhiyun 	s2mps11->dev_type = platform_get_device_id(pdev)->driver_data;
1137*4882a593Smuzhiyun 	switch (s2mps11->dev_type) {
1138*4882a593Smuzhiyun 	case S2MPS11X:
1139*4882a593Smuzhiyun 		rdev_num = ARRAY_SIZE(s2mps11_regulators);
1140*4882a593Smuzhiyun 		regulators = s2mps11_regulators;
1141*4882a593Smuzhiyun 		BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mps11_regulators));
1142*4882a593Smuzhiyun 		break;
1143*4882a593Smuzhiyun 	case S2MPS13X:
1144*4882a593Smuzhiyun 		rdev_num = ARRAY_SIZE(s2mps13_regulators);
1145*4882a593Smuzhiyun 		regulators = s2mps13_regulators;
1146*4882a593Smuzhiyun 		BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mps13_regulators));
1147*4882a593Smuzhiyun 		break;
1148*4882a593Smuzhiyun 	case S2MPS14X:
1149*4882a593Smuzhiyun 		rdev_num = ARRAY_SIZE(s2mps14_regulators);
1150*4882a593Smuzhiyun 		regulators = s2mps14_regulators;
1151*4882a593Smuzhiyun 		BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mps14_regulators));
1152*4882a593Smuzhiyun 		break;
1153*4882a593Smuzhiyun 	case S2MPS15X:
1154*4882a593Smuzhiyun 		rdev_num = ARRAY_SIZE(s2mps15_regulators);
1155*4882a593Smuzhiyun 		regulators = s2mps15_regulators;
1156*4882a593Smuzhiyun 		BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mps15_regulators));
1157*4882a593Smuzhiyun 		break;
1158*4882a593Smuzhiyun 	case S2MPU02:
1159*4882a593Smuzhiyun 		rdev_num = ARRAY_SIZE(s2mpu02_regulators);
1160*4882a593Smuzhiyun 		regulators = s2mpu02_regulators;
1161*4882a593Smuzhiyun 		BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mpu02_regulators));
1162*4882a593Smuzhiyun 		break;
1163*4882a593Smuzhiyun 	default:
1164*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Invalid device type: %u\n",
1165*4882a593Smuzhiyun 				    s2mps11->dev_type);
1166*4882a593Smuzhiyun 		return -EINVAL;
1167*4882a593Smuzhiyun 	}
1168*4882a593Smuzhiyun 
1169*4882a593Smuzhiyun 	s2mps11->ext_control_gpiod = devm_kcalloc(&pdev->dev, rdev_num,
1170*4882a593Smuzhiyun 			       sizeof(*s2mps11->ext_control_gpiod), GFP_KERNEL);
1171*4882a593Smuzhiyun 	if (!s2mps11->ext_control_gpiod)
1172*4882a593Smuzhiyun 		return -ENOMEM;
1173*4882a593Smuzhiyun 
1174*4882a593Smuzhiyun 	if (!iodev->dev->of_node) {
1175*4882a593Smuzhiyun 		if (iodev->pdata) {
1176*4882a593Smuzhiyun 			pdata = iodev->pdata;
1177*4882a593Smuzhiyun 			goto common_reg;
1178*4882a593Smuzhiyun 		} else {
1179*4882a593Smuzhiyun 			dev_err(pdev->dev.parent,
1180*4882a593Smuzhiyun 				"Platform data or DT node not supplied\n");
1181*4882a593Smuzhiyun 			return -ENODEV;
1182*4882a593Smuzhiyun 		}
1183*4882a593Smuzhiyun 	}
1184*4882a593Smuzhiyun 
1185*4882a593Smuzhiyun 	rdata = kcalloc(rdev_num, sizeof(*rdata), GFP_KERNEL);
1186*4882a593Smuzhiyun 	if (!rdata)
1187*4882a593Smuzhiyun 		return -ENOMEM;
1188*4882a593Smuzhiyun 
1189*4882a593Smuzhiyun 	for (i = 0; i < rdev_num; i++)
1190*4882a593Smuzhiyun 		rdata[i].name = regulators[i].name;
1191*4882a593Smuzhiyun 
1192*4882a593Smuzhiyun 	ret = s2mps11_pmic_dt_parse(pdev, rdata, s2mps11, rdev_num);
1193*4882a593Smuzhiyun 	if (ret)
1194*4882a593Smuzhiyun 		goto out;
1195*4882a593Smuzhiyun 
1196*4882a593Smuzhiyun common_reg:
1197*4882a593Smuzhiyun 	platform_set_drvdata(pdev, s2mps11);
1198*4882a593Smuzhiyun 
1199*4882a593Smuzhiyun 	config.dev = &pdev->dev;
1200*4882a593Smuzhiyun 	config.regmap = iodev->regmap_pmic;
1201*4882a593Smuzhiyun 	config.driver_data = s2mps11;
1202*4882a593Smuzhiyun 	for (i = 0; i < rdev_num; i++) {
1203*4882a593Smuzhiyun 		struct regulator_dev *regulator;
1204*4882a593Smuzhiyun 
1205*4882a593Smuzhiyun 		if (pdata) {
1206*4882a593Smuzhiyun 			config.init_data = pdata->regulators[i].initdata;
1207*4882a593Smuzhiyun 			config.of_node = pdata->regulators[i].reg_node;
1208*4882a593Smuzhiyun 		} else {
1209*4882a593Smuzhiyun 			config.init_data = rdata[i].init_data;
1210*4882a593Smuzhiyun 			config.of_node = rdata[i].of_node;
1211*4882a593Smuzhiyun 		}
1212*4882a593Smuzhiyun 		config.ena_gpiod = s2mps11->ext_control_gpiod[i];
1213*4882a593Smuzhiyun 		/*
1214*4882a593Smuzhiyun 		 * Hand the GPIO descriptor management over to the regulator
1215*4882a593Smuzhiyun 		 * core, remove it from devres management.
1216*4882a593Smuzhiyun 		 */
1217*4882a593Smuzhiyun 		if (config.ena_gpiod)
1218*4882a593Smuzhiyun 			devm_gpiod_unhinge(&pdev->dev, config.ena_gpiod);
1219*4882a593Smuzhiyun 		regulator = devm_regulator_register(&pdev->dev,
1220*4882a593Smuzhiyun 						&regulators[i], &config);
1221*4882a593Smuzhiyun 		if (IS_ERR(regulator)) {
1222*4882a593Smuzhiyun 			ret = PTR_ERR(regulator);
1223*4882a593Smuzhiyun 			dev_err(&pdev->dev, "regulator init failed for %d\n",
1224*4882a593Smuzhiyun 				i);
1225*4882a593Smuzhiyun 			goto out;
1226*4882a593Smuzhiyun 		}
1227*4882a593Smuzhiyun 
1228*4882a593Smuzhiyun 		if (config.ena_gpiod) {
1229*4882a593Smuzhiyun 			ret = s2mps14_pmic_enable_ext_control(s2mps11,
1230*4882a593Smuzhiyun 					regulator);
1231*4882a593Smuzhiyun 			if (ret < 0) {
1232*4882a593Smuzhiyun 				dev_err(&pdev->dev,
1233*4882a593Smuzhiyun 						"failed to enable GPIO control over %s: %d\n",
1234*4882a593Smuzhiyun 						regulator->desc->name, ret);
1235*4882a593Smuzhiyun 				goto out;
1236*4882a593Smuzhiyun 			}
1237*4882a593Smuzhiyun 		}
1238*4882a593Smuzhiyun 	}
1239*4882a593Smuzhiyun 
1240*4882a593Smuzhiyun out:
1241*4882a593Smuzhiyun 	kfree(rdata);
1242*4882a593Smuzhiyun 
1243*4882a593Smuzhiyun 	return ret;
1244*4882a593Smuzhiyun }
1245*4882a593Smuzhiyun 
1246*4882a593Smuzhiyun static const struct platform_device_id s2mps11_pmic_id[] = {
1247*4882a593Smuzhiyun 	{ "s2mps11-regulator", S2MPS11X},
1248*4882a593Smuzhiyun 	{ "s2mps13-regulator", S2MPS13X},
1249*4882a593Smuzhiyun 	{ "s2mps14-regulator", S2MPS14X},
1250*4882a593Smuzhiyun 	{ "s2mps15-regulator", S2MPS15X},
1251*4882a593Smuzhiyun 	{ "s2mpu02-regulator", S2MPU02},
1252*4882a593Smuzhiyun 	{ },
1253*4882a593Smuzhiyun };
1254*4882a593Smuzhiyun MODULE_DEVICE_TABLE(platform, s2mps11_pmic_id);
1255*4882a593Smuzhiyun 
1256*4882a593Smuzhiyun static struct platform_driver s2mps11_pmic_driver = {
1257*4882a593Smuzhiyun 	.driver = {
1258*4882a593Smuzhiyun 		.name = "s2mps11-pmic",
1259*4882a593Smuzhiyun 	},
1260*4882a593Smuzhiyun 	.probe = s2mps11_pmic_probe,
1261*4882a593Smuzhiyun 	.id_table = s2mps11_pmic_id,
1262*4882a593Smuzhiyun };
1263*4882a593Smuzhiyun 
1264*4882a593Smuzhiyun module_platform_driver(s2mps11_pmic_driver);
1265*4882a593Smuzhiyun 
1266*4882a593Smuzhiyun /* Module information */
1267*4882a593Smuzhiyun MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
1268*4882a593Smuzhiyun MODULE_DESCRIPTION("Samsung S2MPS11/S2MPS14/S2MPS15/S2MPU02 Regulator Driver");
1269*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1270