1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (c) 2013 Samsung Electronics Co., Ltd
4*4882a593Smuzhiyun // http://www.samsung.com
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/bug.h>
7*4882a593Smuzhiyun #include <linux/err.h>
8*4882a593Smuzhiyun #include <linux/gpio.h>
9*4882a593Smuzhiyun #include <linux/slab.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/of.h>
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/regulator/driver.h>
15*4882a593Smuzhiyun #include <linux/regulator/machine.h>
16*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
17*4882a593Smuzhiyun #include <linux/mfd/samsung/core.h>
18*4882a593Smuzhiyun #include <linux/mfd/samsung/s2mpa01.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun struct s2mpa01_info {
21*4882a593Smuzhiyun int ramp_delay24;
22*4882a593Smuzhiyun int ramp_delay3;
23*4882a593Smuzhiyun int ramp_delay5;
24*4882a593Smuzhiyun int ramp_delay16;
25*4882a593Smuzhiyun int ramp_delay7;
26*4882a593Smuzhiyun int ramp_delay8910;
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
get_ramp_delay(int ramp_delay)29*4882a593Smuzhiyun static int get_ramp_delay(int ramp_delay)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun unsigned char cnt = 0;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun ramp_delay /= 6250;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun while (true) {
36*4882a593Smuzhiyun ramp_delay = ramp_delay >> 1;
37*4882a593Smuzhiyun if (ramp_delay == 0)
38*4882a593Smuzhiyun break;
39*4882a593Smuzhiyun cnt++;
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun if (cnt > 3)
43*4882a593Smuzhiyun cnt = 3;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun return cnt;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
s2mpa01_regulator_set_voltage_time_sel(struct regulator_dev * rdev,unsigned int old_selector,unsigned int new_selector)48*4882a593Smuzhiyun static int s2mpa01_regulator_set_voltage_time_sel(struct regulator_dev *rdev,
49*4882a593Smuzhiyun unsigned int old_selector,
50*4882a593Smuzhiyun unsigned int new_selector)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun struct s2mpa01_info *s2mpa01 = rdev_get_drvdata(rdev);
53*4882a593Smuzhiyun unsigned int ramp_delay = 0;
54*4882a593Smuzhiyun int old_volt, new_volt;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun switch (rdev_get_id(rdev)) {
57*4882a593Smuzhiyun case S2MPA01_BUCK2:
58*4882a593Smuzhiyun case S2MPA01_BUCK4:
59*4882a593Smuzhiyun ramp_delay = s2mpa01->ramp_delay24;
60*4882a593Smuzhiyun break;
61*4882a593Smuzhiyun case S2MPA01_BUCK3:
62*4882a593Smuzhiyun ramp_delay = s2mpa01->ramp_delay3;
63*4882a593Smuzhiyun break;
64*4882a593Smuzhiyun case S2MPA01_BUCK5:
65*4882a593Smuzhiyun ramp_delay = s2mpa01->ramp_delay5;
66*4882a593Smuzhiyun break;
67*4882a593Smuzhiyun case S2MPA01_BUCK1:
68*4882a593Smuzhiyun case S2MPA01_BUCK6:
69*4882a593Smuzhiyun ramp_delay = s2mpa01->ramp_delay16;
70*4882a593Smuzhiyun break;
71*4882a593Smuzhiyun case S2MPA01_BUCK7:
72*4882a593Smuzhiyun ramp_delay = s2mpa01->ramp_delay7;
73*4882a593Smuzhiyun break;
74*4882a593Smuzhiyun case S2MPA01_BUCK8:
75*4882a593Smuzhiyun case S2MPA01_BUCK9:
76*4882a593Smuzhiyun case S2MPA01_BUCK10:
77*4882a593Smuzhiyun ramp_delay = s2mpa01->ramp_delay8910;
78*4882a593Smuzhiyun break;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun if (ramp_delay == 0)
82*4882a593Smuzhiyun ramp_delay = rdev->desc->ramp_delay;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun old_volt = rdev->desc->min_uV + (rdev->desc->uV_step * old_selector);
85*4882a593Smuzhiyun new_volt = rdev->desc->min_uV + (rdev->desc->uV_step * new_selector);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun return DIV_ROUND_UP(abs(new_volt - old_volt), ramp_delay);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
s2mpa01_set_ramp_delay(struct regulator_dev * rdev,int ramp_delay)90*4882a593Smuzhiyun static int s2mpa01_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun struct s2mpa01_info *s2mpa01 = rdev_get_drvdata(rdev);
93*4882a593Smuzhiyun unsigned int ramp_val, ramp_shift, ramp_reg = S2MPA01_REG_RAMP2;
94*4882a593Smuzhiyun unsigned int ramp_enable = 1, enable_shift = 0;
95*4882a593Smuzhiyun int ret;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun switch (rdev_get_id(rdev)) {
98*4882a593Smuzhiyun case S2MPA01_BUCK1:
99*4882a593Smuzhiyun enable_shift = S2MPA01_BUCK1_RAMP_EN_SHIFT;
100*4882a593Smuzhiyun if (!ramp_delay) {
101*4882a593Smuzhiyun ramp_enable = 0;
102*4882a593Smuzhiyun break;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun if (ramp_delay > s2mpa01->ramp_delay16)
106*4882a593Smuzhiyun s2mpa01->ramp_delay16 = ramp_delay;
107*4882a593Smuzhiyun else
108*4882a593Smuzhiyun ramp_delay = s2mpa01->ramp_delay16;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun ramp_shift = S2MPA01_BUCK16_RAMP_SHIFT;
111*4882a593Smuzhiyun break;
112*4882a593Smuzhiyun case S2MPA01_BUCK2:
113*4882a593Smuzhiyun enable_shift = S2MPA01_BUCK2_RAMP_EN_SHIFT;
114*4882a593Smuzhiyun if (!ramp_delay) {
115*4882a593Smuzhiyun ramp_enable = 0;
116*4882a593Smuzhiyun break;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun if (ramp_delay > s2mpa01->ramp_delay24)
120*4882a593Smuzhiyun s2mpa01->ramp_delay24 = ramp_delay;
121*4882a593Smuzhiyun else
122*4882a593Smuzhiyun ramp_delay = s2mpa01->ramp_delay24;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun ramp_shift = S2MPA01_BUCK24_RAMP_SHIFT;
125*4882a593Smuzhiyun ramp_reg = S2MPA01_REG_RAMP1;
126*4882a593Smuzhiyun break;
127*4882a593Smuzhiyun case S2MPA01_BUCK3:
128*4882a593Smuzhiyun enable_shift = S2MPA01_BUCK3_RAMP_EN_SHIFT;
129*4882a593Smuzhiyun if (!ramp_delay) {
130*4882a593Smuzhiyun ramp_enable = 0;
131*4882a593Smuzhiyun break;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun s2mpa01->ramp_delay3 = ramp_delay;
135*4882a593Smuzhiyun ramp_shift = S2MPA01_BUCK3_RAMP_SHIFT;
136*4882a593Smuzhiyun ramp_reg = S2MPA01_REG_RAMP1;
137*4882a593Smuzhiyun break;
138*4882a593Smuzhiyun case S2MPA01_BUCK4:
139*4882a593Smuzhiyun enable_shift = S2MPA01_BUCK4_RAMP_EN_SHIFT;
140*4882a593Smuzhiyun if (!ramp_delay) {
141*4882a593Smuzhiyun ramp_enable = 0;
142*4882a593Smuzhiyun break;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun if (ramp_delay > s2mpa01->ramp_delay24)
146*4882a593Smuzhiyun s2mpa01->ramp_delay24 = ramp_delay;
147*4882a593Smuzhiyun else
148*4882a593Smuzhiyun ramp_delay = s2mpa01->ramp_delay24;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun ramp_shift = S2MPA01_BUCK24_RAMP_SHIFT;
151*4882a593Smuzhiyun ramp_reg = S2MPA01_REG_RAMP1;
152*4882a593Smuzhiyun break;
153*4882a593Smuzhiyun case S2MPA01_BUCK5:
154*4882a593Smuzhiyun s2mpa01->ramp_delay5 = ramp_delay;
155*4882a593Smuzhiyun ramp_shift = S2MPA01_BUCK5_RAMP_SHIFT;
156*4882a593Smuzhiyun break;
157*4882a593Smuzhiyun case S2MPA01_BUCK6:
158*4882a593Smuzhiyun if (ramp_delay > s2mpa01->ramp_delay16)
159*4882a593Smuzhiyun s2mpa01->ramp_delay16 = ramp_delay;
160*4882a593Smuzhiyun else
161*4882a593Smuzhiyun ramp_delay = s2mpa01->ramp_delay16;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun ramp_shift = S2MPA01_BUCK16_RAMP_SHIFT;
164*4882a593Smuzhiyun break;
165*4882a593Smuzhiyun case S2MPA01_BUCK7:
166*4882a593Smuzhiyun s2mpa01->ramp_delay7 = ramp_delay;
167*4882a593Smuzhiyun ramp_shift = S2MPA01_BUCK7_RAMP_SHIFT;
168*4882a593Smuzhiyun break;
169*4882a593Smuzhiyun case S2MPA01_BUCK8:
170*4882a593Smuzhiyun case S2MPA01_BUCK9:
171*4882a593Smuzhiyun case S2MPA01_BUCK10:
172*4882a593Smuzhiyun if (ramp_delay > s2mpa01->ramp_delay8910)
173*4882a593Smuzhiyun s2mpa01->ramp_delay8910 = ramp_delay;
174*4882a593Smuzhiyun else
175*4882a593Smuzhiyun ramp_delay = s2mpa01->ramp_delay8910;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun ramp_shift = S2MPA01_BUCK8910_RAMP_SHIFT;
178*4882a593Smuzhiyun break;
179*4882a593Smuzhiyun default:
180*4882a593Smuzhiyun return 0;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun if (!ramp_enable)
184*4882a593Smuzhiyun goto ramp_disable;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun /* Ramp delay can be enabled/disabled only for buck[1234] */
187*4882a593Smuzhiyun if (rdev_get_id(rdev) >= S2MPA01_BUCK1 &&
188*4882a593Smuzhiyun rdev_get_id(rdev) <= S2MPA01_BUCK4) {
189*4882a593Smuzhiyun ret = regmap_update_bits(rdev->regmap, S2MPA01_REG_RAMP1,
190*4882a593Smuzhiyun 1 << enable_shift, 1 << enable_shift);
191*4882a593Smuzhiyun if (ret) {
192*4882a593Smuzhiyun dev_err(&rdev->dev, "failed to enable ramp rate\n");
193*4882a593Smuzhiyun return ret;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun ramp_val = get_ramp_delay(ramp_delay);
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, ramp_reg, 0x3 << ramp_shift,
200*4882a593Smuzhiyun ramp_val << ramp_shift);
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun ramp_disable:
203*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, S2MPA01_REG_RAMP1,
204*4882a593Smuzhiyun 1 << enable_shift, 0);
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun static const struct regulator_ops s2mpa01_ldo_ops = {
208*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
209*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear,
210*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
211*4882a593Smuzhiyun .enable = regulator_enable_regmap,
212*4882a593Smuzhiyun .disable = regulator_disable_regmap,
213*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
214*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
215*4882a593Smuzhiyun .set_voltage_time_sel = regulator_set_voltage_time_sel,
216*4882a593Smuzhiyun };
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun static const struct regulator_ops s2mpa01_buck_ops = {
219*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
220*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear,
221*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
222*4882a593Smuzhiyun .enable = regulator_enable_regmap,
223*4882a593Smuzhiyun .disable = regulator_disable_regmap,
224*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
225*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
226*4882a593Smuzhiyun .set_voltage_time_sel = s2mpa01_regulator_set_voltage_time_sel,
227*4882a593Smuzhiyun .set_ramp_delay = s2mpa01_set_ramp_delay,
228*4882a593Smuzhiyun };
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun #define regulator_desc_ldo(num, step) { \
231*4882a593Smuzhiyun .name = "LDO"#num, \
232*4882a593Smuzhiyun .of_match = of_match_ptr("LDO"#num), \
233*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"), \
234*4882a593Smuzhiyun .id = S2MPA01_LDO##num, \
235*4882a593Smuzhiyun .ops = &s2mpa01_ldo_ops, \
236*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
237*4882a593Smuzhiyun .owner = THIS_MODULE, \
238*4882a593Smuzhiyun .min_uV = MIN_800_MV, \
239*4882a593Smuzhiyun .uV_step = step, \
240*4882a593Smuzhiyun .n_voltages = S2MPA01_LDO_N_VOLTAGES, \
241*4882a593Smuzhiyun .vsel_reg = S2MPA01_REG_L1CTRL + num - 1, \
242*4882a593Smuzhiyun .vsel_mask = S2MPA01_LDO_VSEL_MASK, \
243*4882a593Smuzhiyun .enable_reg = S2MPA01_REG_L1CTRL + num - 1, \
244*4882a593Smuzhiyun .enable_mask = S2MPA01_ENABLE_MASK \
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun #define regulator_desc_buck1_4(num) { \
248*4882a593Smuzhiyun .name = "BUCK"#num, \
249*4882a593Smuzhiyun .of_match = of_match_ptr("BUCK"#num), \
250*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"), \
251*4882a593Smuzhiyun .id = S2MPA01_BUCK##num, \
252*4882a593Smuzhiyun .ops = &s2mpa01_buck_ops, \
253*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
254*4882a593Smuzhiyun .owner = THIS_MODULE, \
255*4882a593Smuzhiyun .min_uV = MIN_600_MV, \
256*4882a593Smuzhiyun .uV_step = STEP_6_25_MV, \
257*4882a593Smuzhiyun .n_voltages = S2MPA01_BUCK_N_VOLTAGES, \
258*4882a593Smuzhiyun .ramp_delay = S2MPA01_RAMP_DELAY, \
259*4882a593Smuzhiyun .vsel_reg = S2MPA01_REG_B1CTRL2 + (num - 1) * 2, \
260*4882a593Smuzhiyun .vsel_mask = S2MPA01_BUCK_VSEL_MASK, \
261*4882a593Smuzhiyun .enable_reg = S2MPA01_REG_B1CTRL1 + (num - 1) * 2, \
262*4882a593Smuzhiyun .enable_mask = S2MPA01_ENABLE_MASK \
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun #define regulator_desc_buck5 { \
266*4882a593Smuzhiyun .name = "BUCK5", \
267*4882a593Smuzhiyun .of_match = of_match_ptr("BUCK5"), \
268*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"), \
269*4882a593Smuzhiyun .id = S2MPA01_BUCK5, \
270*4882a593Smuzhiyun .ops = &s2mpa01_buck_ops, \
271*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
272*4882a593Smuzhiyun .owner = THIS_MODULE, \
273*4882a593Smuzhiyun .min_uV = MIN_800_MV, \
274*4882a593Smuzhiyun .uV_step = STEP_6_25_MV, \
275*4882a593Smuzhiyun .n_voltages = S2MPA01_BUCK_N_VOLTAGES, \
276*4882a593Smuzhiyun .ramp_delay = S2MPA01_RAMP_DELAY, \
277*4882a593Smuzhiyun .vsel_reg = S2MPA01_REG_B5CTRL2, \
278*4882a593Smuzhiyun .vsel_mask = S2MPA01_BUCK_VSEL_MASK, \
279*4882a593Smuzhiyun .enable_reg = S2MPA01_REG_B5CTRL1, \
280*4882a593Smuzhiyun .enable_mask = S2MPA01_ENABLE_MASK \
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun #define regulator_desc_buck6_10(num, min, step) { \
284*4882a593Smuzhiyun .name = "BUCK"#num, \
285*4882a593Smuzhiyun .of_match = of_match_ptr("BUCK"#num), \
286*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"), \
287*4882a593Smuzhiyun .id = S2MPA01_BUCK##num, \
288*4882a593Smuzhiyun .ops = &s2mpa01_buck_ops, \
289*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
290*4882a593Smuzhiyun .owner = THIS_MODULE, \
291*4882a593Smuzhiyun .min_uV = min, \
292*4882a593Smuzhiyun .uV_step = step, \
293*4882a593Smuzhiyun .n_voltages = S2MPA01_BUCK_N_VOLTAGES, \
294*4882a593Smuzhiyun .ramp_delay = S2MPA01_RAMP_DELAY, \
295*4882a593Smuzhiyun .vsel_reg = S2MPA01_REG_B6CTRL2 + (num - 6) * 2, \
296*4882a593Smuzhiyun .vsel_mask = S2MPA01_BUCK_VSEL_MASK, \
297*4882a593Smuzhiyun .enable_reg = S2MPA01_REG_B6CTRL1 + (num - 6) * 2, \
298*4882a593Smuzhiyun .enable_mask = S2MPA01_ENABLE_MASK \
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun static const struct regulator_desc regulators[] = {
302*4882a593Smuzhiyun regulator_desc_ldo(1, STEP_25_MV),
303*4882a593Smuzhiyun regulator_desc_ldo(2, STEP_50_MV),
304*4882a593Smuzhiyun regulator_desc_ldo(3, STEP_50_MV),
305*4882a593Smuzhiyun regulator_desc_ldo(4, STEP_50_MV),
306*4882a593Smuzhiyun regulator_desc_ldo(5, STEP_25_MV),
307*4882a593Smuzhiyun regulator_desc_ldo(6, STEP_25_MV),
308*4882a593Smuzhiyun regulator_desc_ldo(7, STEP_50_MV),
309*4882a593Smuzhiyun regulator_desc_ldo(8, STEP_50_MV),
310*4882a593Smuzhiyun regulator_desc_ldo(9, STEP_50_MV),
311*4882a593Smuzhiyun regulator_desc_ldo(10, STEP_50_MV),
312*4882a593Smuzhiyun regulator_desc_ldo(11, STEP_50_MV),
313*4882a593Smuzhiyun regulator_desc_ldo(12, STEP_50_MV),
314*4882a593Smuzhiyun regulator_desc_ldo(13, STEP_50_MV),
315*4882a593Smuzhiyun regulator_desc_ldo(14, STEP_50_MV),
316*4882a593Smuzhiyun regulator_desc_ldo(15, STEP_50_MV),
317*4882a593Smuzhiyun regulator_desc_ldo(16, STEP_50_MV),
318*4882a593Smuzhiyun regulator_desc_ldo(17, STEP_50_MV),
319*4882a593Smuzhiyun regulator_desc_ldo(18, STEP_50_MV),
320*4882a593Smuzhiyun regulator_desc_ldo(19, STEP_50_MV),
321*4882a593Smuzhiyun regulator_desc_ldo(20, STEP_50_MV),
322*4882a593Smuzhiyun regulator_desc_ldo(21, STEP_50_MV),
323*4882a593Smuzhiyun regulator_desc_ldo(22, STEP_50_MV),
324*4882a593Smuzhiyun regulator_desc_ldo(23, STEP_50_MV),
325*4882a593Smuzhiyun regulator_desc_ldo(24, STEP_50_MV),
326*4882a593Smuzhiyun regulator_desc_ldo(25, STEP_50_MV),
327*4882a593Smuzhiyun regulator_desc_ldo(26, STEP_25_MV),
328*4882a593Smuzhiyun regulator_desc_buck1_4(1),
329*4882a593Smuzhiyun regulator_desc_buck1_4(2),
330*4882a593Smuzhiyun regulator_desc_buck1_4(3),
331*4882a593Smuzhiyun regulator_desc_buck1_4(4),
332*4882a593Smuzhiyun regulator_desc_buck5,
333*4882a593Smuzhiyun regulator_desc_buck6_10(6, MIN_600_MV, STEP_6_25_MV),
334*4882a593Smuzhiyun regulator_desc_buck6_10(7, MIN_600_MV, STEP_6_25_MV),
335*4882a593Smuzhiyun regulator_desc_buck6_10(8, MIN_800_MV, STEP_12_5_MV),
336*4882a593Smuzhiyun regulator_desc_buck6_10(9, MIN_1500_MV, STEP_12_5_MV),
337*4882a593Smuzhiyun regulator_desc_buck6_10(10, MIN_1000_MV, STEP_12_5_MV),
338*4882a593Smuzhiyun };
339*4882a593Smuzhiyun
s2mpa01_pmic_probe(struct platform_device * pdev)340*4882a593Smuzhiyun static int s2mpa01_pmic_probe(struct platform_device *pdev)
341*4882a593Smuzhiyun {
342*4882a593Smuzhiyun struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
343*4882a593Smuzhiyun struct sec_platform_data *pdata = dev_get_platdata(iodev->dev);
344*4882a593Smuzhiyun struct regulator_config config = { };
345*4882a593Smuzhiyun struct s2mpa01_info *s2mpa01;
346*4882a593Smuzhiyun int i;
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun s2mpa01 = devm_kzalloc(&pdev->dev, sizeof(*s2mpa01), GFP_KERNEL);
349*4882a593Smuzhiyun if (!s2mpa01)
350*4882a593Smuzhiyun return -ENOMEM;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun config.dev = iodev->dev;
353*4882a593Smuzhiyun config.regmap = iodev->regmap_pmic;
354*4882a593Smuzhiyun config.driver_data = s2mpa01;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun for (i = 0; i < S2MPA01_REGULATOR_MAX; i++) {
357*4882a593Smuzhiyun struct regulator_dev *rdev;
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun if (pdata)
360*4882a593Smuzhiyun config.init_data = pdata->regulators[i].initdata;
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun rdev = devm_regulator_register(&pdev->dev,
363*4882a593Smuzhiyun ®ulators[i], &config);
364*4882a593Smuzhiyun if (IS_ERR(rdev)) {
365*4882a593Smuzhiyun dev_err(&pdev->dev, "regulator init failed for %d\n",
366*4882a593Smuzhiyun i);
367*4882a593Smuzhiyun return PTR_ERR(rdev);
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun return 0;
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun static const struct platform_device_id s2mpa01_pmic_id[] = {
375*4882a593Smuzhiyun { "s2mpa01-pmic", 0},
376*4882a593Smuzhiyun { },
377*4882a593Smuzhiyun };
378*4882a593Smuzhiyun MODULE_DEVICE_TABLE(platform, s2mpa01_pmic_id);
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun static struct platform_driver s2mpa01_pmic_driver = {
381*4882a593Smuzhiyun .driver = {
382*4882a593Smuzhiyun .name = "s2mpa01-pmic",
383*4882a593Smuzhiyun },
384*4882a593Smuzhiyun .probe = s2mpa01_pmic_probe,
385*4882a593Smuzhiyun .id_table = s2mpa01_pmic_id,
386*4882a593Smuzhiyun };
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun module_platform_driver(s2mpa01_pmic_driver);
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun /* Module information */
391*4882a593Smuzhiyun MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
392*4882a593Smuzhiyun MODULE_AUTHOR("Sachin Kamat <sachin.kamat@samsung.com>");
393*4882a593Smuzhiyun MODULE_DESCRIPTION("Samsung S2MPA01 Regulator Driver");
394*4882a593Smuzhiyun MODULE_LICENSE("GPL");
395