1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Regulator driver for Rockchip RK805/RK808/RK818
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Chris Zhong <zyw@rock-chips.com>
8*4882a593Smuzhiyun * Author: Zhang Qing <zhangqing@rock-chips.com>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Copyright (C) 2016 PHYTEC Messtechnik GmbH
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * Author: Wadim Egorov <w.egorov@phytec.de>
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/gpio.h>
17*4882a593Smuzhiyun #include <linux/i2c.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/of_device.h>
20*4882a593Smuzhiyun #include <linux/of_gpio.h>
21*4882a593Smuzhiyun #include <linux/mfd/rk808.h>
22*4882a593Smuzhiyun #include <linux/regulator/driver.h>
23*4882a593Smuzhiyun #include <linux/regulator/of_regulator.h>
24*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* Field Definitions */
27*4882a593Smuzhiyun #define RK808_BUCK_VSEL_MASK 0x3f
28*4882a593Smuzhiyun #define RK808_BUCK4_VSEL_MASK 0xf
29*4882a593Smuzhiyun #define RK808_LDO_VSEL_MASK 0x1f
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define RK809_BUCK5_VSEL_MASK 0x7
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define RK817_LDO_VSEL_MASK 0x7f
34*4882a593Smuzhiyun #define RK817_BOOST_VSEL_MASK 0x7
35*4882a593Smuzhiyun #define RK817_BUCK_VSEL_MASK 0x7f
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define RK816_DCDC_SLP_EN_REG_OFFSET 2
38*4882a593Smuzhiyun #define RK816_SWITCH_SLP_EN_REG_OFFSET 1
39*4882a593Smuzhiyun #define RK816_LDO1_4_SLP_EN_REG_OFFSET 1
40*4882a593Smuzhiyun #define RK816_LDO5_6_SLP_EN_REG_OFFSET 2
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define RK818_BUCK_VSEL_MASK 0x3f
43*4882a593Smuzhiyun #define RK818_BUCK4_VSEL_MASK 0x1f
44*4882a593Smuzhiyun #define RK818_LDO_VSEL_MASK 0x1f
45*4882a593Smuzhiyun #define RK818_LDO3_ON_VSEL_MASK 0xf
46*4882a593Smuzhiyun #define RK818_BOOST_ON_VSEL_MASK 0xe0
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* Ramp rate definitions for buck1 / buck2 only */
49*4882a593Smuzhiyun #define RK808_RAMP_RATE_OFFSET 3
50*4882a593Smuzhiyun #define RK808_RAMP_RATE_MASK (3 << RK808_RAMP_RATE_OFFSET)
51*4882a593Smuzhiyun #define RK808_RAMP_RATE_2MV_PER_US (0 << RK808_RAMP_RATE_OFFSET)
52*4882a593Smuzhiyun #define RK808_RAMP_RATE_4MV_PER_US (1 << RK808_RAMP_RATE_OFFSET)
53*4882a593Smuzhiyun #define RK808_RAMP_RATE_6MV_PER_US (2 << RK808_RAMP_RATE_OFFSET)
54*4882a593Smuzhiyun #define RK808_RAMP_RATE_10MV_PER_US (3 << RK808_RAMP_RATE_OFFSET)
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #define RK808_DVS2_POL BIT(2)
57*4882a593Smuzhiyun #define RK808_DVS1_POL BIT(1)
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* Offset from XXX_ON_VSEL to XXX_SLP_VSEL */
60*4882a593Smuzhiyun #define RK808_SLP_REG_OFFSET 1
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* Offset from XXX_ON_VSEL to XXX_DVS_VSEL */
63*4882a593Smuzhiyun #define RK808_DVS_REG_OFFSET 2
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* Offset from XXX_EN_REG to SLEEP_SET_OFF_XXX */
66*4882a593Smuzhiyun #define RK808_SLP_SET_OFF_REG_OFFSET 2
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* max steps for increase voltage of Buck1/2, equal 25mv*/
69*4882a593Smuzhiyun #define MAX_STEPS_ONE_TIME 2
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #define ENABLE_MASK(id) (BIT(id) | BIT(4 + (id)))
72*4882a593Smuzhiyun #define DISABLE_VAL(id) (BIT(4 + (id)))
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #define RK817_BOOST_DESC(_id, _match, _supply, _min, _max, _step, _vreg,\
75*4882a593Smuzhiyun _vmask, _ereg, _emask, _enval, _disval, _etime, m_drop) \
76*4882a593Smuzhiyun { \
77*4882a593Smuzhiyun .name = (_match), \
78*4882a593Smuzhiyun .supply_name = (_supply), \
79*4882a593Smuzhiyun .of_match = of_match_ptr(_match), \
80*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"), \
81*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
82*4882a593Smuzhiyun .id = (_id), \
83*4882a593Smuzhiyun .n_voltages = (((_max) - (_min)) / (_step) + 1), \
84*4882a593Smuzhiyun .owner = THIS_MODULE, \
85*4882a593Smuzhiyun .min_uV = (_min) * 1000, \
86*4882a593Smuzhiyun .uV_step = (_step) * 1000, \
87*4882a593Smuzhiyun .vsel_reg = (_vreg), \
88*4882a593Smuzhiyun .vsel_mask = (_vmask), \
89*4882a593Smuzhiyun .enable_reg = (_ereg), \
90*4882a593Smuzhiyun .enable_mask = (_emask), \
91*4882a593Smuzhiyun .enable_val = (_enval), \
92*4882a593Smuzhiyun .disable_val = (_disval), \
93*4882a593Smuzhiyun .enable_time = (_etime), \
94*4882a593Smuzhiyun .min_dropout_uV = (m_drop) * 1000, \
95*4882a593Smuzhiyun .ops = &rk817_boost_ops, \
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun #define RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \
99*4882a593Smuzhiyun _vmask, _ereg, _emask, _enval, _disval, _etime, _ops) \
100*4882a593Smuzhiyun { \
101*4882a593Smuzhiyun .name = (_match), \
102*4882a593Smuzhiyun .supply_name = (_supply), \
103*4882a593Smuzhiyun .of_match = of_match_ptr(_match), \
104*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"), \
105*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
106*4882a593Smuzhiyun .id = (_id), \
107*4882a593Smuzhiyun .n_voltages = (((_max) - (_min)) / (_step) + 1), \
108*4882a593Smuzhiyun .owner = THIS_MODULE, \
109*4882a593Smuzhiyun .min_uV = (_min) * 1000, \
110*4882a593Smuzhiyun .uV_step = (_step) * 1000, \
111*4882a593Smuzhiyun .vsel_reg = (_vreg), \
112*4882a593Smuzhiyun .vsel_mask = (_vmask), \
113*4882a593Smuzhiyun .enable_reg = (_ereg), \
114*4882a593Smuzhiyun .enable_mask = (_emask), \
115*4882a593Smuzhiyun .enable_val = (_enval), \
116*4882a593Smuzhiyun .disable_val = (_disval), \
117*4882a593Smuzhiyun .enable_time = (_etime), \
118*4882a593Smuzhiyun .ops = _ops, \
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun #define RK816_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \
122*4882a593Smuzhiyun _vmask, _ereg, _emask, _disval, _etime) \
123*4882a593Smuzhiyun RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \
124*4882a593Smuzhiyun _vmask, _ereg, _emask, _emask, _disval, _etime, &rk808_reg_ops)
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun #define RK805_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \
127*4882a593Smuzhiyun _vmask, _ereg, _emask, _disval, _etime) \
128*4882a593Smuzhiyun RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \
129*4882a593Smuzhiyun _vmask, _ereg, _emask, _emask, _disval, _etime, &rk808_reg_ops)
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun #define RK8XX_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \
132*4882a593Smuzhiyun _vmask, _ereg, _emask, _etime) \
133*4882a593Smuzhiyun RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \
134*4882a593Smuzhiyun _vmask, _ereg, _emask, 0, 0, _etime, &rk808_reg_ops)
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun #define RK817_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \
137*4882a593Smuzhiyun _vmask, _ereg, _emask, _enval, _disval, _etime) \
138*4882a593Smuzhiyun RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \
139*4882a593Smuzhiyun _vmask, _ereg, _emask, _enval, _disval, _etime, &rk817_reg_ops)
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun #define RKXX_DESC_SWITCH_COM(_id, _match, _supply, _ereg, _emask, \
142*4882a593Smuzhiyun _enval, _disval, _ops) \
143*4882a593Smuzhiyun { \
144*4882a593Smuzhiyun .name = (_match), \
145*4882a593Smuzhiyun .supply_name = (_supply), \
146*4882a593Smuzhiyun .of_match = of_match_ptr(_match), \
147*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"), \
148*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE, \
149*4882a593Smuzhiyun .id = (_id), \
150*4882a593Smuzhiyun .enable_reg = (_ereg), \
151*4882a593Smuzhiyun .enable_mask = (_emask), \
152*4882a593Smuzhiyun .enable_val = (_enval), \
153*4882a593Smuzhiyun .disable_val = (_disval), \
154*4882a593Smuzhiyun .owner = THIS_MODULE, \
155*4882a593Smuzhiyun .ops = _ops \
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun #define RK817_DESC_SWITCH(_id, _match, _supply, _ereg, _emask, _enval, \
159*4882a593Smuzhiyun _disval) \
160*4882a593Smuzhiyun RKXX_DESC_SWITCH_COM(_id, _match, _supply, _ereg, _emask, \
161*4882a593Smuzhiyun _enval, _disval, &rk817_switch_ops)
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun #define RK8XX_DESC_SWITCH(_id, _match, _supply, _ereg, _emask) \
164*4882a593Smuzhiyun RKXX_DESC_SWITCH_COM(_id, _match, _supply, _ereg, _emask, \
165*4882a593Smuzhiyun 0, 0, &rk808_switch_ops)
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun struct rk808_regulator_data {
168*4882a593Smuzhiyun struct gpio_desc *dvs_gpio[2];
169*4882a593Smuzhiyun };
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun static const int rk808_buck_config_regs[] = {
172*4882a593Smuzhiyun RK808_BUCK1_CONFIG_REG,
173*4882a593Smuzhiyun RK808_BUCK2_CONFIG_REG,
174*4882a593Smuzhiyun RK808_BUCK3_CONFIG_REG,
175*4882a593Smuzhiyun RK808_BUCK4_CONFIG_REG,
176*4882a593Smuzhiyun };
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun static const struct linear_range rk805_buck_1_2_voltage_ranges[] = {
179*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(712500, 0, 59, 12500), /* 0.7125v - 1.45v */
180*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1800000, 60, 62, 200000),/* 1.8v - 2.2v */
181*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2300000, 63, 63, 0), /* 2.3v - 2.3v */
182*4882a593Smuzhiyun };
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun static const struct linear_range rk805_buck4_voltage_ranges[] = {
185*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(800000, 0, 26, 100000), /* 0.8v - 3.4v */
186*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3500000, 27, 31, 0), /* 3.5v */
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun static const struct linear_range rk808_ldo3_voltage_ranges[] = {
190*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(800000, 0, 13, 100000),
191*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2500000, 15, 15, 0),
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun static const struct linear_range rk816_buck_voltage_ranges[] = {
195*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(712500, 0, 59, 12500), /* 0.7125v - 1.45v */
196*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1800000, 60, 62, 200000),/* 1.8v - 2.2v */
197*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2300000, 63, 63, 0), /* 2.3v - 2.3v */
198*4882a593Smuzhiyun };
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun static const struct linear_range rk816_buck4_voltage_ranges[] = {
201*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(800000, 0, 26, 100000), /* 0.8v - 3.4 */
202*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3500000, 27, 31, 0), /* 3.5v */
203*4882a593Smuzhiyun };
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun #define RK809_BUCK5_SEL_CNT (8)
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun static const struct linear_range rk809_buck5_voltage_ranges[] = {
208*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1500000, 0, 0, 0),
209*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(1800000, 1, 3, 200000),
210*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(2800000, 4, 5, 200000),
211*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(3300000, 6, 7, 300000),
212*4882a593Smuzhiyun };
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun #define RK817_BUCK1_MIN0 500000
215*4882a593Smuzhiyun #define RK817_BUCK1_MAX0 1500000
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun #define RK817_BUCK1_MIN1 1600000
218*4882a593Smuzhiyun #define RK817_BUCK1_MAX1 2400000
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun #define RK817_BUCK3_MAX1 3400000
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun #define RK817_BUCK1_STP0 12500
223*4882a593Smuzhiyun #define RK817_BUCK1_STP1 100000
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun #define RK817_BUCK1_SEL0 ((RK817_BUCK1_MAX0 - RK817_BUCK1_MIN0) /\
226*4882a593Smuzhiyun RK817_BUCK1_STP0)
227*4882a593Smuzhiyun #define RK817_BUCK1_SEL1 ((RK817_BUCK1_MAX1 - RK817_BUCK1_MIN1) /\
228*4882a593Smuzhiyun RK817_BUCK1_STP1)
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun #define RK817_BUCK3_SEL1 ((RK817_BUCK3_MAX1 - RK817_BUCK1_MIN1) /\
231*4882a593Smuzhiyun RK817_BUCK1_STP1)
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun #define RK817_BUCK1_SEL_CNT (RK817_BUCK1_SEL0 + RK817_BUCK1_SEL1 + 1)
234*4882a593Smuzhiyun #define RK817_BUCK3_SEL_CNT (RK817_BUCK1_SEL0 + RK817_BUCK3_SEL1 + 1)
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun static const struct linear_range rk817_buck1_voltage_ranges[] = {
237*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(RK817_BUCK1_MIN0, 0,
238*4882a593Smuzhiyun RK817_BUCK1_SEL0, RK817_BUCK1_STP0),
239*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(RK817_BUCK1_MIN1, RK817_BUCK1_SEL0 + 1,
240*4882a593Smuzhiyun RK817_BUCK1_SEL_CNT, RK817_BUCK1_STP1),
241*4882a593Smuzhiyun };
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun static const struct linear_range rk817_buck3_voltage_ranges[] = {
244*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(RK817_BUCK1_MIN0, 0,
245*4882a593Smuzhiyun RK817_BUCK1_SEL0, RK817_BUCK1_STP0),
246*4882a593Smuzhiyun REGULATOR_LINEAR_RANGE(RK817_BUCK1_MIN1, RK817_BUCK1_SEL0 + 1,
247*4882a593Smuzhiyun RK817_BUCK3_SEL_CNT, RK817_BUCK1_STP1),
248*4882a593Smuzhiyun };
249*4882a593Smuzhiyun
rk808_buck1_2_get_voltage_sel_regmap(struct regulator_dev * rdev)250*4882a593Smuzhiyun static int rk808_buck1_2_get_voltage_sel_regmap(struct regulator_dev *rdev)
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun struct rk808_regulator_data *pdata = rdev_get_drvdata(rdev);
253*4882a593Smuzhiyun int id = rdev_get_id(rdev);
254*4882a593Smuzhiyun struct gpio_desc *gpio = pdata->dvs_gpio[id];
255*4882a593Smuzhiyun unsigned int val;
256*4882a593Smuzhiyun int ret;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun if (!gpio || gpiod_get_value(gpio) == 0)
259*4882a593Smuzhiyun return regulator_get_voltage_sel_regmap(rdev);
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun ret = regmap_read(rdev->regmap,
262*4882a593Smuzhiyun rdev->desc->vsel_reg + RK808_DVS_REG_OFFSET,
263*4882a593Smuzhiyun &val);
264*4882a593Smuzhiyun if (ret != 0)
265*4882a593Smuzhiyun return ret;
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun val &= rdev->desc->vsel_mask;
268*4882a593Smuzhiyun val >>= ffs(rdev->desc->vsel_mask) - 1;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun return val;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
rk808_buck1_2_i2c_set_voltage_sel(struct regulator_dev * rdev,unsigned sel)273*4882a593Smuzhiyun static int rk808_buck1_2_i2c_set_voltage_sel(struct regulator_dev *rdev,
274*4882a593Smuzhiyun unsigned sel)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun int ret, delta_sel;
277*4882a593Smuzhiyun unsigned int old_sel, tmp, val, mask = rdev->desc->vsel_mask;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun ret = regmap_read(rdev->regmap, rdev->desc->vsel_reg, &val);
280*4882a593Smuzhiyun if (ret != 0)
281*4882a593Smuzhiyun return ret;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun tmp = val & ~mask;
284*4882a593Smuzhiyun old_sel = val & mask;
285*4882a593Smuzhiyun old_sel >>= ffs(mask) - 1;
286*4882a593Smuzhiyun delta_sel = sel - old_sel;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun /*
289*4882a593Smuzhiyun * If directly modify the register to change the voltage, we will face
290*4882a593Smuzhiyun * the risk of overshoot. Put it into a multi-step, can effectively
291*4882a593Smuzhiyun * avoid this problem, a step is 100mv here.
292*4882a593Smuzhiyun */
293*4882a593Smuzhiyun while (delta_sel > MAX_STEPS_ONE_TIME) {
294*4882a593Smuzhiyun old_sel += MAX_STEPS_ONE_TIME;
295*4882a593Smuzhiyun val = old_sel << (ffs(mask) - 1);
296*4882a593Smuzhiyun val |= tmp;
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun /*
299*4882a593Smuzhiyun * i2c is 400kHz (2.5us per bit) and we must transmit _at least_
300*4882a593Smuzhiyun * 3 bytes (24 bits) plus start and stop so 26 bits. So we've
301*4882a593Smuzhiyun * got more than 65 us between each voltage change and thus
302*4882a593Smuzhiyun * won't ramp faster than ~1500 uV / us.
303*4882a593Smuzhiyun */
304*4882a593Smuzhiyun ret = regmap_write(rdev->regmap, rdev->desc->vsel_reg, val);
305*4882a593Smuzhiyun delta_sel = sel - old_sel;
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun sel <<= ffs(mask) - 1;
309*4882a593Smuzhiyun val = tmp | sel;
310*4882a593Smuzhiyun ret = regmap_write(rdev->regmap, rdev->desc->vsel_reg, val);
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun /*
313*4882a593Smuzhiyun * When we change the voltage register directly, the ramp rate is about
314*4882a593Smuzhiyun * 100000uv/us, wait 1us to make sure the target voltage to be stable,
315*4882a593Smuzhiyun * so we needn't wait extra time after that.
316*4882a593Smuzhiyun */
317*4882a593Smuzhiyun udelay(1);
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun return ret;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun #ifdef CONFIG_CLK_RK312X
323*4882a593Smuzhiyun extern void rkclk_cpuclk_div_setting(int div);
324*4882a593Smuzhiyun #else
rkclk_cpuclk_div_setting(int div)325*4882a593Smuzhiyun static inline void rkclk_cpuclk_div_setting(int div) {}
326*4882a593Smuzhiyun #endif
327*4882a593Smuzhiyun
rk816_regulator_set_voltage_sel_regmap(struct regulator_dev * rdev,unsigned int sel)328*4882a593Smuzhiyun static int rk816_regulator_set_voltage_sel_regmap(struct regulator_dev *rdev,
329*4882a593Smuzhiyun unsigned int sel)
330*4882a593Smuzhiyun {
331*4882a593Smuzhiyun int ret, real_sel, delay = 100;
332*4882a593Smuzhiyun int rk816_type;
333*4882a593Smuzhiyun int id = rdev_get_id(rdev);
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun regmap_read(rdev->regmap, RK816_CHIP_VER_REG, &rk816_type);
336*4882a593Smuzhiyun rk816_type &= RK816_CHIP_VERSION_MASK;
337*4882a593Smuzhiyun sel <<= ffs(rdev->desc->vsel_mask) - 1;
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun if ((rk816_type != RK816_TYPE_ES2) && (id == 0)) {
340*4882a593Smuzhiyun if (sel > 23)
341*4882a593Smuzhiyun rkclk_cpuclk_div_setting(4);
342*4882a593Smuzhiyun else
343*4882a593Smuzhiyun rkclk_cpuclk_div_setting(2);
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun do {
347*4882a593Smuzhiyun ret = regmap_update_bits(rdev->regmap,
348*4882a593Smuzhiyun rdev->desc->vsel_reg,
349*4882a593Smuzhiyun rdev->desc->vsel_mask, sel);
350*4882a593Smuzhiyun if (ret)
351*4882a593Smuzhiyun return ret;
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun if (rk816_type == RK816_TYPE_ES2) {
354*4882a593Smuzhiyun ret = regmap_update_bits(rdev->regmap,
355*4882a593Smuzhiyun RK816_DCDC_EN_REG2,
356*4882a593Smuzhiyun RK816_BUCK_DVS_CONFIRM,
357*4882a593Smuzhiyun RK816_BUCK_DVS_CONFIRM);
358*4882a593Smuzhiyun if (ret)
359*4882a593Smuzhiyun return ret;
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun regmap_read(rdev->regmap,
363*4882a593Smuzhiyun rdev->desc->vsel_reg, &real_sel);
364*4882a593Smuzhiyun real_sel &= rdev->desc->vsel_mask;
365*4882a593Smuzhiyun delay--;
366*4882a593Smuzhiyun } while ((sel != real_sel) && (delay > 0));
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun if ((rk816_type != RK816_TYPE_ES2) && (id == 0))
369*4882a593Smuzhiyun rkclk_cpuclk_div_setting(1);
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun return ret;
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun
rk808_buck1_2_set_voltage_sel(struct regulator_dev * rdev,unsigned sel)374*4882a593Smuzhiyun static int rk808_buck1_2_set_voltage_sel(struct regulator_dev *rdev,
375*4882a593Smuzhiyun unsigned sel)
376*4882a593Smuzhiyun {
377*4882a593Smuzhiyun struct rk808_regulator_data *pdata = rdev_get_drvdata(rdev);
378*4882a593Smuzhiyun int id = rdev_get_id(rdev);
379*4882a593Smuzhiyun struct gpio_desc *gpio = pdata->dvs_gpio[id];
380*4882a593Smuzhiyun unsigned int reg = rdev->desc->vsel_reg;
381*4882a593Smuzhiyun unsigned old_sel;
382*4882a593Smuzhiyun int ret, gpio_level;
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun if (!gpio)
385*4882a593Smuzhiyun return rk808_buck1_2_i2c_set_voltage_sel(rdev, sel);
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun gpio_level = gpiod_get_value(gpio);
388*4882a593Smuzhiyun if (gpio_level == 0) {
389*4882a593Smuzhiyun reg += RK808_DVS_REG_OFFSET;
390*4882a593Smuzhiyun ret = regmap_read(rdev->regmap, rdev->desc->vsel_reg, &old_sel);
391*4882a593Smuzhiyun } else {
392*4882a593Smuzhiyun ret = regmap_read(rdev->regmap,
393*4882a593Smuzhiyun reg + RK808_DVS_REG_OFFSET,
394*4882a593Smuzhiyun &old_sel);
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun if (ret != 0)
398*4882a593Smuzhiyun return ret;
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun sel <<= ffs(rdev->desc->vsel_mask) - 1;
401*4882a593Smuzhiyun sel |= old_sel & ~rdev->desc->vsel_mask;
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun ret = regmap_write(rdev->regmap, reg, sel);
404*4882a593Smuzhiyun if (ret)
405*4882a593Smuzhiyun return ret;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun gpiod_set_value(gpio, !gpio_level);
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun return ret;
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
rk808_buck1_2_set_voltage_time_sel(struct regulator_dev * rdev,unsigned int old_selector,unsigned int new_selector)412*4882a593Smuzhiyun static int rk808_buck1_2_set_voltage_time_sel(struct regulator_dev *rdev,
413*4882a593Smuzhiyun unsigned int old_selector,
414*4882a593Smuzhiyun unsigned int new_selector)
415*4882a593Smuzhiyun {
416*4882a593Smuzhiyun struct rk808_regulator_data *pdata = rdev_get_drvdata(rdev);
417*4882a593Smuzhiyun int id = rdev_get_id(rdev);
418*4882a593Smuzhiyun struct gpio_desc *gpio = pdata->dvs_gpio[id];
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun /* if there is no dvs1/2 pin, we don't need wait extra time here. */
421*4882a593Smuzhiyun if (!gpio)
422*4882a593Smuzhiyun return 0;
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun return regulator_set_voltage_time_sel(rdev, old_selector, new_selector);
425*4882a593Smuzhiyun }
426*4882a593Smuzhiyun
rk805_set_ramp_delay(struct regulator_dev * rdev,int ramp_delay)427*4882a593Smuzhiyun static int rk805_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
428*4882a593Smuzhiyun {
429*4882a593Smuzhiyun unsigned int ramp_value = RK808_RAMP_RATE_10MV_PER_US;
430*4882a593Smuzhiyun unsigned int reg = rk808_buck_config_regs[rdev_get_id(rdev)];
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun switch (ramp_delay) {
433*4882a593Smuzhiyun case 0 ... 3000:
434*4882a593Smuzhiyun ramp_value = RK805_RAMP_RATE_3MV_PER_US;
435*4882a593Smuzhiyun break;
436*4882a593Smuzhiyun case 3001 ... 6000:
437*4882a593Smuzhiyun ramp_value = RK805_RAMP_RATE_6MV_PER_US;
438*4882a593Smuzhiyun break;
439*4882a593Smuzhiyun case 6001 ... 12500:
440*4882a593Smuzhiyun ramp_value = RK805_RAMP_RATE_12_5MV_PER_US;
441*4882a593Smuzhiyun break;
442*4882a593Smuzhiyun case 12501 ... 25000:
443*4882a593Smuzhiyun ramp_value = RK805_RAMP_RATE_25MV_PER_US;
444*4882a593Smuzhiyun break;
445*4882a593Smuzhiyun default:
446*4882a593Smuzhiyun pr_warn("%s ramp_delay: %d not supported\n",
447*4882a593Smuzhiyun rdev->desc->name, ramp_delay);
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, reg,
451*4882a593Smuzhiyun RK805_RAMP_RATE_MASK, ramp_value);
452*4882a593Smuzhiyun }
453*4882a593Smuzhiyun
rk808_set_ramp_delay(struct regulator_dev * rdev,int ramp_delay)454*4882a593Smuzhiyun static int rk808_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
455*4882a593Smuzhiyun {
456*4882a593Smuzhiyun unsigned int ramp_value = RK808_RAMP_RATE_10MV_PER_US;
457*4882a593Smuzhiyun unsigned int reg = rk808_buck_config_regs[rdev_get_id(rdev)];
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun switch (ramp_delay) {
460*4882a593Smuzhiyun case 1 ... 2000:
461*4882a593Smuzhiyun ramp_value = RK808_RAMP_RATE_2MV_PER_US;
462*4882a593Smuzhiyun break;
463*4882a593Smuzhiyun case 2001 ... 4000:
464*4882a593Smuzhiyun ramp_value = RK808_RAMP_RATE_4MV_PER_US;
465*4882a593Smuzhiyun break;
466*4882a593Smuzhiyun case 4001 ... 6000:
467*4882a593Smuzhiyun ramp_value = RK808_RAMP_RATE_6MV_PER_US;
468*4882a593Smuzhiyun break;
469*4882a593Smuzhiyun case 6001 ... 10000:
470*4882a593Smuzhiyun break;
471*4882a593Smuzhiyun default:
472*4882a593Smuzhiyun pr_warn("%s ramp_delay: %d not supported, setting 10000\n",
473*4882a593Smuzhiyun rdev->desc->name, ramp_delay);
474*4882a593Smuzhiyun }
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, reg,
477*4882a593Smuzhiyun RK808_RAMP_RATE_MASK, ramp_value);
478*4882a593Smuzhiyun }
479*4882a593Smuzhiyun
rk8xx_set_ramp_delay(struct regulator_dev * rdev,int ramp_delay)480*4882a593Smuzhiyun static int rk8xx_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
481*4882a593Smuzhiyun {
482*4882a593Smuzhiyun struct rk808 *rk808 = dev_get_drvdata(rdev->dev.parent);
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun if (rk808->variant == RK805_ID)
485*4882a593Smuzhiyun return rk805_set_ramp_delay(rdev, ramp_delay);
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun return rk808_set_ramp_delay(rdev, ramp_delay);
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun /*
491*4882a593Smuzhiyun * RK817 RK809
492*4882a593Smuzhiyun */
rk817_set_ramp_delay(struct regulator_dev * rdev,int ramp_delay)493*4882a593Smuzhiyun static int rk817_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
494*4882a593Smuzhiyun {
495*4882a593Smuzhiyun unsigned int ramp_value = RK817_RAMP_RATE_25MV_PER_US;
496*4882a593Smuzhiyun unsigned int reg = RK817_BUCK_CONFIG_REG(rdev_get_id(rdev));
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun switch (ramp_delay) {
499*4882a593Smuzhiyun case 0 ... 3000:
500*4882a593Smuzhiyun ramp_value = RK817_RAMP_RATE_3MV_PER_US;
501*4882a593Smuzhiyun break;
502*4882a593Smuzhiyun case 3001 ... 6300:
503*4882a593Smuzhiyun ramp_value = RK817_RAMP_RATE_6_3MV_PER_US;
504*4882a593Smuzhiyun break;
505*4882a593Smuzhiyun case 6301 ... 12500:
506*4882a593Smuzhiyun ramp_value = RK817_RAMP_RATE_12_5MV_PER_US;
507*4882a593Smuzhiyun break;
508*4882a593Smuzhiyun case 12501 ... 25000:
509*4882a593Smuzhiyun break;
510*4882a593Smuzhiyun default:
511*4882a593Smuzhiyun dev_warn(&rdev->dev,
512*4882a593Smuzhiyun "%s ramp_delay: %d not supported, setting 25000\n",
513*4882a593Smuzhiyun rdev->desc->name, ramp_delay);
514*4882a593Smuzhiyun }
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, reg,
517*4882a593Smuzhiyun RK817_RAMP_RATE_MASK, ramp_value);
518*4882a593Smuzhiyun }
519*4882a593Smuzhiyun
rk808_set_suspend_voltage(struct regulator_dev * rdev,int uv)520*4882a593Smuzhiyun static int rk808_set_suspend_voltage(struct regulator_dev *rdev, int uv)
521*4882a593Smuzhiyun {
522*4882a593Smuzhiyun unsigned int reg;
523*4882a593Smuzhiyun int sel = regulator_map_voltage_linear(rdev, uv, uv);
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun if (sel < 0)
526*4882a593Smuzhiyun return -EINVAL;
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun reg = rdev->desc->vsel_reg + RK808_SLP_REG_OFFSET;
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, reg,
531*4882a593Smuzhiyun rdev->desc->vsel_mask,
532*4882a593Smuzhiyun sel);
533*4882a593Smuzhiyun }
534*4882a593Smuzhiyun
rk808_set_suspend_voltage_range(struct regulator_dev * rdev,int uv)535*4882a593Smuzhiyun static int rk808_set_suspend_voltage_range(struct regulator_dev *rdev, int uv)
536*4882a593Smuzhiyun {
537*4882a593Smuzhiyun unsigned int reg;
538*4882a593Smuzhiyun int sel = regulator_map_voltage_linear_range(rdev, uv, uv);
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun if (sel < 0)
541*4882a593Smuzhiyun return -EINVAL;
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun reg = rdev->desc->vsel_reg + RK808_SLP_REG_OFFSET;
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, reg,
546*4882a593Smuzhiyun rdev->desc->vsel_mask,
547*4882a593Smuzhiyun sel);
548*4882a593Smuzhiyun }
549*4882a593Smuzhiyun
rk805_set_suspend_enable(struct regulator_dev * rdev)550*4882a593Smuzhiyun static int rk805_set_suspend_enable(struct regulator_dev *rdev)
551*4882a593Smuzhiyun {
552*4882a593Smuzhiyun unsigned int reg, offset;
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun if (rdev->desc->id >= RK805_ID_LDO1)
555*4882a593Smuzhiyun offset = RK805_SLP_LDO_EN_OFFSET;
556*4882a593Smuzhiyun else
557*4882a593Smuzhiyun offset = RK805_SLP_DCDC_EN_OFFSET;
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun reg = rdev->desc->enable_reg + offset;
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, reg,
562*4882a593Smuzhiyun rdev->desc->enable_mask,
563*4882a593Smuzhiyun rdev->desc->enable_mask);
564*4882a593Smuzhiyun }
565*4882a593Smuzhiyun
rk805_set_suspend_disable(struct regulator_dev * rdev)566*4882a593Smuzhiyun static int rk805_set_suspend_disable(struct regulator_dev *rdev)
567*4882a593Smuzhiyun {
568*4882a593Smuzhiyun unsigned int reg, offset;
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun if (rdev->desc->id >= RK805_ID_LDO1)
571*4882a593Smuzhiyun offset = RK805_SLP_LDO_EN_OFFSET;
572*4882a593Smuzhiyun else
573*4882a593Smuzhiyun offset = RK805_SLP_DCDC_EN_OFFSET;
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun reg = rdev->desc->enable_reg + offset;
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, reg,
578*4882a593Smuzhiyun rdev->desc->enable_mask,
579*4882a593Smuzhiyun 0);
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun
rk816_set_suspend_enable(struct regulator_dev * rdev)582*4882a593Smuzhiyun static int rk816_set_suspend_enable(struct regulator_dev *rdev)
583*4882a593Smuzhiyun {
584*4882a593Smuzhiyun unsigned int reg, val;
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun if (rdev->desc->id <= RK816_ID_DCDC4) {
587*4882a593Smuzhiyun reg = rdev->desc->enable_reg +
588*4882a593Smuzhiyun RK816_DCDC_SLP_EN_REG_OFFSET;
589*4882a593Smuzhiyun val = 1 << rdev->desc->id;
590*4882a593Smuzhiyun } else if ((rdev->desc->id > RK816_ID_DCDC4) &&
591*4882a593Smuzhiyun (rdev->desc->id <= RK816_ID_LDO4)) {
592*4882a593Smuzhiyun reg = rdev->desc->enable_reg -
593*4882a593Smuzhiyun RK816_LDO1_4_SLP_EN_REG_OFFSET;
594*4882a593Smuzhiyun val = 1 << (rdev->desc->id - RK816_ID_LDO1);
595*4882a593Smuzhiyun } else {
596*4882a593Smuzhiyun reg = rdev->desc->enable_reg -
597*4882a593Smuzhiyun RK816_LDO5_6_SLP_EN_REG_OFFSET;
598*4882a593Smuzhiyun val = 1 << (rdev->desc->id - RK816_ID_LDO1);
599*4882a593Smuzhiyun }
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, reg,
602*4882a593Smuzhiyun val,
603*4882a593Smuzhiyun val);
604*4882a593Smuzhiyun }
605*4882a593Smuzhiyun
rk816_set_suspend_disable(struct regulator_dev * rdev)606*4882a593Smuzhiyun static int rk816_set_suspend_disable(struct regulator_dev *rdev)
607*4882a593Smuzhiyun {
608*4882a593Smuzhiyun unsigned int reg, val;
609*4882a593Smuzhiyun
610*4882a593Smuzhiyun if (rdev->desc->id <= RK816_ID_DCDC4) {
611*4882a593Smuzhiyun reg = rdev->desc->enable_reg +
612*4882a593Smuzhiyun RK816_DCDC_SLP_EN_REG_OFFSET;
613*4882a593Smuzhiyun val = 1 << rdev->desc->id;
614*4882a593Smuzhiyun } else if ((rdev->desc->id > RK816_ID_DCDC4) &&
615*4882a593Smuzhiyun (rdev->desc->id <= RK816_ID_LDO4)) {
616*4882a593Smuzhiyun reg = rdev->desc->enable_reg -
617*4882a593Smuzhiyun RK816_LDO1_4_SLP_EN_REG_OFFSET;
618*4882a593Smuzhiyun val = 1 << (rdev->desc->id - RK816_ID_LDO1);
619*4882a593Smuzhiyun } else {
620*4882a593Smuzhiyun reg = rdev->desc->enable_reg -
621*4882a593Smuzhiyun RK816_LDO5_6_SLP_EN_REG_OFFSET;
622*4882a593Smuzhiyun val = 1 << (rdev->desc->id - RK816_ID_LDO1);
623*4882a593Smuzhiyun }
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, reg,
626*4882a593Smuzhiyun val,
627*4882a593Smuzhiyun 0);
628*4882a593Smuzhiyun }
629*4882a593Smuzhiyun
rk808_set_suspend_enable(struct regulator_dev * rdev)630*4882a593Smuzhiyun static int rk808_set_suspend_enable(struct regulator_dev *rdev)
631*4882a593Smuzhiyun {
632*4882a593Smuzhiyun unsigned int reg;
633*4882a593Smuzhiyun struct rk808 *rk808 = dev_get_drvdata(rdev->dev.parent);
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun if (rk808->variant == RK816_ID)
636*4882a593Smuzhiyun return rk816_set_suspend_enable(rdev);
637*4882a593Smuzhiyun else if (rk808->variant == RK805_ID)
638*4882a593Smuzhiyun return rk805_set_suspend_enable(rdev);
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun reg = rdev->desc->enable_reg + RK808_SLP_SET_OFF_REG_OFFSET;
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, reg,
643*4882a593Smuzhiyun rdev->desc->enable_mask,
644*4882a593Smuzhiyun 0);
645*4882a593Smuzhiyun }
646*4882a593Smuzhiyun
rk808_set_suspend_disable(struct regulator_dev * rdev)647*4882a593Smuzhiyun static int rk808_set_suspend_disable(struct regulator_dev *rdev)
648*4882a593Smuzhiyun {
649*4882a593Smuzhiyun unsigned int reg;
650*4882a593Smuzhiyun struct rk808 *rk808 = dev_get_drvdata(rdev->dev.parent);
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun if (rk808->variant == RK816_ID)
653*4882a593Smuzhiyun return rk816_set_suspend_disable(rdev);
654*4882a593Smuzhiyun else if (rk808->variant == RK805_ID)
655*4882a593Smuzhiyun return rk805_set_suspend_disable(rdev);
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun reg = rdev->desc->enable_reg + RK808_SLP_SET_OFF_REG_OFFSET;
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, reg,
660*4882a593Smuzhiyun rdev->desc->enable_mask,
661*4882a593Smuzhiyun rdev->desc->enable_mask);
662*4882a593Smuzhiyun }
663*4882a593Smuzhiyun
rk817_set_suspend_enable_ctrl(struct regulator_dev * rdev,unsigned int en)664*4882a593Smuzhiyun static int rk817_set_suspend_enable_ctrl(struct regulator_dev *rdev,
665*4882a593Smuzhiyun unsigned int en)
666*4882a593Smuzhiyun {
667*4882a593Smuzhiyun unsigned int reg;
668*4882a593Smuzhiyun int id = rdev_get_id(rdev);
669*4882a593Smuzhiyun unsigned int id_slp, msk, val;
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun if (id >= RK817_ID_DCDC1 && id <= RK817_ID_DCDC4)
672*4882a593Smuzhiyun id_slp = id;
673*4882a593Smuzhiyun else if (id >= RK817_ID_LDO1 && id <= RK817_ID_LDO8)
674*4882a593Smuzhiyun id_slp = 8 + (id - RK817_ID_LDO1);
675*4882a593Smuzhiyun else if (id >= RK817_ID_LDO9 && id <= RK809_ID_SW2)
676*4882a593Smuzhiyun id_slp = 4 + (id - RK817_ID_LDO9);
677*4882a593Smuzhiyun else
678*4882a593Smuzhiyun return -EINVAL;
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun reg = RK817_POWER_SLP_EN_REG(id_slp / 8);
681*4882a593Smuzhiyun
682*4882a593Smuzhiyun msk = BIT(id_slp % 8);
683*4882a593Smuzhiyun if (en)
684*4882a593Smuzhiyun val = msk;
685*4882a593Smuzhiyun else
686*4882a593Smuzhiyun val = 0;
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, reg, msk, val);
689*4882a593Smuzhiyun }
690*4882a593Smuzhiyun
rk817_set_suspend_enable(struct regulator_dev * rdev)691*4882a593Smuzhiyun static int rk817_set_suspend_enable(struct regulator_dev *rdev)
692*4882a593Smuzhiyun {
693*4882a593Smuzhiyun return rk817_set_suspend_enable_ctrl(rdev, 1);
694*4882a593Smuzhiyun }
695*4882a593Smuzhiyun
rk817_set_suspend_disable(struct regulator_dev * rdev)696*4882a593Smuzhiyun static int rk817_set_suspend_disable(struct regulator_dev *rdev)
697*4882a593Smuzhiyun {
698*4882a593Smuzhiyun return rk817_set_suspend_enable_ctrl(rdev, 0);
699*4882a593Smuzhiyun }
700*4882a593Smuzhiyun
rk8xx_set_suspend_mode(struct regulator_dev * rdev,unsigned int mode)701*4882a593Smuzhiyun static int rk8xx_set_suspend_mode(struct regulator_dev *rdev, unsigned int mode)
702*4882a593Smuzhiyun {
703*4882a593Smuzhiyun unsigned int reg;
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun reg = rdev->desc->vsel_reg + RK808_SLP_REG_OFFSET;
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun switch (mode) {
708*4882a593Smuzhiyun case REGULATOR_MODE_FAST:
709*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, reg,
710*4882a593Smuzhiyun PWM_MODE_MSK, FPWM_MODE);
711*4882a593Smuzhiyun case REGULATOR_MODE_NORMAL:
712*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, reg,
713*4882a593Smuzhiyun PWM_MODE_MSK, AUTO_PWM_MODE);
714*4882a593Smuzhiyun default:
715*4882a593Smuzhiyun dev_err(&rdev->dev, "do not support this mode\n");
716*4882a593Smuzhiyun return -EINVAL;
717*4882a593Smuzhiyun }
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun return 0;
720*4882a593Smuzhiyun }
721*4882a593Smuzhiyun
rk8xx_set_mode(struct regulator_dev * rdev,unsigned int mode)722*4882a593Smuzhiyun static int rk8xx_set_mode(struct regulator_dev *rdev, unsigned int mode)
723*4882a593Smuzhiyun {
724*4882a593Smuzhiyun switch (mode) {
725*4882a593Smuzhiyun case REGULATOR_MODE_FAST:
726*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, rdev->desc->vsel_reg,
727*4882a593Smuzhiyun PWM_MODE_MSK, FPWM_MODE);
728*4882a593Smuzhiyun case REGULATOR_MODE_NORMAL:
729*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap, rdev->desc->vsel_reg,
730*4882a593Smuzhiyun PWM_MODE_MSK, AUTO_PWM_MODE);
731*4882a593Smuzhiyun default:
732*4882a593Smuzhiyun dev_err(&rdev->dev, "do not support this mode\n");
733*4882a593Smuzhiyun return -EINVAL;
734*4882a593Smuzhiyun }
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun return 0;
737*4882a593Smuzhiyun }
738*4882a593Smuzhiyun
rk8xx_get_mode(struct regulator_dev * rdev)739*4882a593Smuzhiyun static unsigned int rk8xx_get_mode(struct regulator_dev *rdev)
740*4882a593Smuzhiyun {
741*4882a593Smuzhiyun unsigned int val;
742*4882a593Smuzhiyun int err;
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun err = regmap_read(rdev->regmap, rdev->desc->vsel_reg, &val);
745*4882a593Smuzhiyun if (err)
746*4882a593Smuzhiyun return err;
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun if (val & FPWM_MODE)
749*4882a593Smuzhiyun return REGULATOR_MODE_FAST;
750*4882a593Smuzhiyun else
751*4882a593Smuzhiyun return REGULATOR_MODE_NORMAL;
752*4882a593Smuzhiyun }
753*4882a593Smuzhiyun
rk8xx_enabled_wmsk_regmap(struct regulator_dev * rdev)754*4882a593Smuzhiyun static int rk8xx_enabled_wmsk_regmap(struct regulator_dev *rdev)
755*4882a593Smuzhiyun {
756*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap,
757*4882a593Smuzhiyun rdev->desc->enable_reg,
758*4882a593Smuzhiyun rdev->desc->enable_mask,
759*4882a593Smuzhiyun rdev->desc->enable_mask);
760*4882a593Smuzhiyun }
761*4882a593Smuzhiyun
rk8xx_disabled_wmsk_regmap(struct regulator_dev * rdev)762*4882a593Smuzhiyun static int rk8xx_disabled_wmsk_regmap(struct regulator_dev *rdev)
763*4882a593Smuzhiyun {
764*4882a593Smuzhiyun return regmap_update_bits(rdev->regmap,
765*4882a593Smuzhiyun rdev->desc->enable_reg,
766*4882a593Smuzhiyun rdev->desc->enable_mask,
767*4882a593Smuzhiyun rdev->desc->disable_val);
768*4882a593Smuzhiyun }
769*4882a593Smuzhiyun
rk8xx_is_enabled_wmsk_regmap(struct regulator_dev * rdev)770*4882a593Smuzhiyun static int rk8xx_is_enabled_wmsk_regmap(struct regulator_dev *rdev)
771*4882a593Smuzhiyun {
772*4882a593Smuzhiyun unsigned int val;
773*4882a593Smuzhiyun int ret;
774*4882a593Smuzhiyun
775*4882a593Smuzhiyun ret = regmap_read(rdev->regmap, rdev->desc->enable_reg, &val);
776*4882a593Smuzhiyun if (ret != 0)
777*4882a593Smuzhiyun return ret;
778*4882a593Smuzhiyun
779*4882a593Smuzhiyun val &= rdev->desc->enable_val;
780*4882a593Smuzhiyun return val != 0;
781*4882a593Smuzhiyun }
782*4882a593Smuzhiyun
rk8xx_regulator_of_map_mode(unsigned int mode)783*4882a593Smuzhiyun static unsigned int rk8xx_regulator_of_map_mode(unsigned int mode)
784*4882a593Smuzhiyun {
785*4882a593Smuzhiyun switch (mode) {
786*4882a593Smuzhiyun case 1:
787*4882a593Smuzhiyun return REGULATOR_MODE_FAST;
788*4882a593Smuzhiyun case 2:
789*4882a593Smuzhiyun return REGULATOR_MODE_NORMAL;
790*4882a593Smuzhiyun default:
791*4882a593Smuzhiyun return REGULATOR_MODE_INVALID;
792*4882a593Smuzhiyun }
793*4882a593Smuzhiyun }
794*4882a593Smuzhiyun
795*4882a593Smuzhiyun static const struct regulator_ops rk808_buck1_2_ops = {
796*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
797*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear,
798*4882a593Smuzhiyun .get_voltage_sel = rk808_buck1_2_get_voltage_sel_regmap,
799*4882a593Smuzhiyun .set_voltage_sel = rk808_buck1_2_set_voltage_sel,
800*4882a593Smuzhiyun .set_voltage_time_sel = rk808_buck1_2_set_voltage_time_sel,
801*4882a593Smuzhiyun .enable = regulator_enable_regmap,
802*4882a593Smuzhiyun .disable = regulator_disable_regmap,
803*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
804*4882a593Smuzhiyun .set_mode = rk8xx_set_mode,
805*4882a593Smuzhiyun .get_mode = rk8xx_get_mode,
806*4882a593Smuzhiyun .set_suspend_mode = rk8xx_set_suspend_mode,
807*4882a593Smuzhiyun .set_ramp_delay = rk8xx_set_ramp_delay,
808*4882a593Smuzhiyun .set_suspend_voltage = rk808_set_suspend_voltage,
809*4882a593Smuzhiyun .set_suspend_enable = rk808_set_suspend_enable,
810*4882a593Smuzhiyun .set_suspend_disable = rk808_set_suspend_disable,
811*4882a593Smuzhiyun };
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun static const struct regulator_ops rk816_buck1_2_ops_ranges = {
814*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
815*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
816*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
817*4882a593Smuzhiyun .set_voltage_sel = rk816_regulator_set_voltage_sel_regmap,
818*4882a593Smuzhiyun .set_voltage_time_sel = regulator_set_voltage_time_sel,
819*4882a593Smuzhiyun .enable = regulator_enable_regmap,
820*4882a593Smuzhiyun .disable = regulator_disable_regmap,
821*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
822*4882a593Smuzhiyun .set_mode = rk8xx_set_mode,
823*4882a593Smuzhiyun .get_mode = rk8xx_get_mode,
824*4882a593Smuzhiyun .set_suspend_mode = rk8xx_set_suspend_mode,
825*4882a593Smuzhiyun .set_ramp_delay = rk8xx_set_ramp_delay,
826*4882a593Smuzhiyun .set_suspend_voltage = rk808_set_suspend_voltage_range,
827*4882a593Smuzhiyun .set_suspend_enable = rk808_set_suspend_enable,
828*4882a593Smuzhiyun .set_suspend_disable = rk808_set_suspend_disable,
829*4882a593Smuzhiyun };
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun static const struct regulator_ops rk808_reg_ops = {
832*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
833*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear,
834*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
835*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
836*4882a593Smuzhiyun .enable = regulator_enable_regmap,
837*4882a593Smuzhiyun .disable = regulator_disable_regmap,
838*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
839*4882a593Smuzhiyun .set_suspend_voltage = rk808_set_suspend_voltage,
840*4882a593Smuzhiyun .set_suspend_enable = rk808_set_suspend_enable,
841*4882a593Smuzhiyun .set_suspend_disable = rk808_set_suspend_disable,
842*4882a593Smuzhiyun };
843*4882a593Smuzhiyun
844*4882a593Smuzhiyun static const struct regulator_ops rk808_reg_ops_ranges = {
845*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
846*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
847*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
848*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
849*4882a593Smuzhiyun .enable = regulator_enable_regmap,
850*4882a593Smuzhiyun .disable = regulator_disable_regmap,
851*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
852*4882a593Smuzhiyun .set_mode = rk8xx_set_mode,
853*4882a593Smuzhiyun .get_mode = rk8xx_get_mode,
854*4882a593Smuzhiyun .set_suspend_mode = rk8xx_set_suspend_mode,
855*4882a593Smuzhiyun .set_ramp_delay = rk8xx_set_ramp_delay,
856*4882a593Smuzhiyun .set_suspend_voltage = rk808_set_suspend_voltage_range,
857*4882a593Smuzhiyun .set_suspend_enable = rk808_set_suspend_enable,
858*4882a593Smuzhiyun .set_suspend_disable = rk808_set_suspend_disable,
859*4882a593Smuzhiyun };
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun static const struct regulator_ops rk808_switch_ops = {
862*4882a593Smuzhiyun .enable = regulator_enable_regmap,
863*4882a593Smuzhiyun .disable = regulator_disable_regmap,
864*4882a593Smuzhiyun .is_enabled = regulator_is_enabled_regmap,
865*4882a593Smuzhiyun .set_mode = rk8xx_set_mode,
866*4882a593Smuzhiyun .get_mode = rk8xx_get_mode,
867*4882a593Smuzhiyun .set_suspend_enable = rk808_set_suspend_enable,
868*4882a593Smuzhiyun .set_suspend_disable = rk808_set_suspend_disable,
869*4882a593Smuzhiyun };
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun static const struct regulator_ops rk809_buck5_ops_range = {
872*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
873*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
874*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
875*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
876*4882a593Smuzhiyun .set_voltage_time_sel = regulator_set_voltage_time_sel,
877*4882a593Smuzhiyun .enable = rk8xx_enabled_wmsk_regmap,
878*4882a593Smuzhiyun .disable = rk8xx_disabled_wmsk_regmap,
879*4882a593Smuzhiyun .is_enabled = rk8xx_is_enabled_wmsk_regmap,
880*4882a593Smuzhiyun .set_suspend_voltage = rk808_set_suspend_voltage_range,
881*4882a593Smuzhiyun .set_suspend_enable = rk817_set_suspend_enable,
882*4882a593Smuzhiyun .set_suspend_disable = rk817_set_suspend_disable,
883*4882a593Smuzhiyun };
884*4882a593Smuzhiyun
885*4882a593Smuzhiyun static const struct regulator_ops rk817_reg_ops = {
886*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
887*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear,
888*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
889*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
890*4882a593Smuzhiyun .enable = rk8xx_enabled_wmsk_regmap,
891*4882a593Smuzhiyun .disable = rk8xx_disabled_wmsk_regmap,
892*4882a593Smuzhiyun .is_enabled = rk8xx_is_enabled_wmsk_regmap,
893*4882a593Smuzhiyun .set_suspend_voltage = rk808_set_suspend_voltage,
894*4882a593Smuzhiyun .set_suspend_enable = rk817_set_suspend_enable,
895*4882a593Smuzhiyun .set_suspend_disable = rk817_set_suspend_disable,
896*4882a593Smuzhiyun };
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun static const struct regulator_ops rk817_boost_ops = {
899*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear,
900*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear,
901*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
902*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
903*4882a593Smuzhiyun .enable = rk8xx_enabled_wmsk_regmap,
904*4882a593Smuzhiyun .disable = rk8xx_disabled_wmsk_regmap,
905*4882a593Smuzhiyun .is_enabled = rk8xx_is_enabled_wmsk_regmap,
906*4882a593Smuzhiyun .set_suspend_enable = rk817_set_suspend_enable,
907*4882a593Smuzhiyun .set_suspend_disable = rk817_set_suspend_disable,
908*4882a593Smuzhiyun };
909*4882a593Smuzhiyun
910*4882a593Smuzhiyun static const struct regulator_ops rk817_buck_ops_range = {
911*4882a593Smuzhiyun .list_voltage = regulator_list_voltage_linear_range,
912*4882a593Smuzhiyun .map_voltage = regulator_map_voltage_linear_range,
913*4882a593Smuzhiyun .get_voltage_sel = regulator_get_voltage_sel_regmap,
914*4882a593Smuzhiyun .set_voltage_sel = regulator_set_voltage_sel_regmap,
915*4882a593Smuzhiyun .set_voltage_time_sel = regulator_set_voltage_time_sel,
916*4882a593Smuzhiyun .enable = rk8xx_enabled_wmsk_regmap,
917*4882a593Smuzhiyun .disable = rk8xx_disabled_wmsk_regmap,
918*4882a593Smuzhiyun .is_enabled = rk8xx_is_enabled_wmsk_regmap,
919*4882a593Smuzhiyun .set_mode = rk8xx_set_mode,
920*4882a593Smuzhiyun .get_mode = rk8xx_get_mode,
921*4882a593Smuzhiyun .set_suspend_mode = rk8xx_set_suspend_mode,
922*4882a593Smuzhiyun .set_ramp_delay = rk817_set_ramp_delay,
923*4882a593Smuzhiyun .set_suspend_voltage = rk808_set_suspend_voltage_range,
924*4882a593Smuzhiyun .set_suspend_enable = rk817_set_suspend_enable,
925*4882a593Smuzhiyun .set_suspend_disable = rk817_set_suspend_disable,
926*4882a593Smuzhiyun };
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun static const struct regulator_ops rk817_switch_ops = {
929*4882a593Smuzhiyun .enable = rk8xx_enabled_wmsk_regmap,
930*4882a593Smuzhiyun .disable = rk8xx_disabled_wmsk_regmap,
931*4882a593Smuzhiyun .is_enabled = rk8xx_is_enabled_wmsk_regmap,
932*4882a593Smuzhiyun .set_suspend_enable = rk817_set_suspend_enable,
933*4882a593Smuzhiyun .set_suspend_disable = rk817_set_suspend_disable,
934*4882a593Smuzhiyun };
935*4882a593Smuzhiyun
936*4882a593Smuzhiyun static const struct regulator_desc rk805_reg[] = {
937*4882a593Smuzhiyun {
938*4882a593Smuzhiyun .name = "DCDC_REG1",
939*4882a593Smuzhiyun .supply_name = "vcc1",
940*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG1"),
941*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
942*4882a593Smuzhiyun .id = RK805_ID_DCDC1,
943*4882a593Smuzhiyun .ops = &rk808_reg_ops_ranges,
944*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
945*4882a593Smuzhiyun .n_voltages = 64,
946*4882a593Smuzhiyun .linear_ranges = rk805_buck_1_2_voltage_ranges,
947*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(rk805_buck_1_2_voltage_ranges),
948*4882a593Smuzhiyun .vsel_reg = RK805_BUCK1_ON_VSEL_REG,
949*4882a593Smuzhiyun .vsel_mask = RK818_BUCK_VSEL_MASK,
950*4882a593Smuzhiyun .enable_reg = RK805_DCDC_EN_REG,
951*4882a593Smuzhiyun .enable_mask = ENABLE_MASK(RK805_ID_DCDC1),
952*4882a593Smuzhiyun .enable_val = ENABLE_MASK(RK805_ID_DCDC1),
953*4882a593Smuzhiyun .disable_val = DISABLE_VAL(RK805_ID_DCDC1),
954*4882a593Smuzhiyun .of_map_mode = rk8xx_regulator_of_map_mode,
955*4882a593Smuzhiyun .owner = THIS_MODULE,
956*4882a593Smuzhiyun }, {
957*4882a593Smuzhiyun .name = "DCDC_REG2",
958*4882a593Smuzhiyun .supply_name = "vcc2",
959*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG2"),
960*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
961*4882a593Smuzhiyun .id = RK805_ID_DCDC2,
962*4882a593Smuzhiyun .ops = &rk808_reg_ops_ranges,
963*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
964*4882a593Smuzhiyun .n_voltages = 64,
965*4882a593Smuzhiyun .linear_ranges = rk805_buck_1_2_voltage_ranges,
966*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(rk805_buck_1_2_voltage_ranges),
967*4882a593Smuzhiyun .vsel_reg = RK805_BUCK2_ON_VSEL_REG,
968*4882a593Smuzhiyun .vsel_mask = RK818_BUCK_VSEL_MASK,
969*4882a593Smuzhiyun .enable_reg = RK805_DCDC_EN_REG,
970*4882a593Smuzhiyun .enable_mask = ENABLE_MASK(RK805_ID_DCDC2),
971*4882a593Smuzhiyun .enable_val = ENABLE_MASK(RK805_ID_DCDC2),
972*4882a593Smuzhiyun .disable_val = DISABLE_VAL(RK805_ID_DCDC2),
973*4882a593Smuzhiyun .of_map_mode = rk8xx_regulator_of_map_mode,
974*4882a593Smuzhiyun .owner = THIS_MODULE,
975*4882a593Smuzhiyun }, {
976*4882a593Smuzhiyun .name = "DCDC_REG3",
977*4882a593Smuzhiyun .supply_name = "vcc3",
978*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG3"),
979*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
980*4882a593Smuzhiyun .id = RK805_ID_DCDC3,
981*4882a593Smuzhiyun .ops = &rk808_switch_ops,
982*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
983*4882a593Smuzhiyun .n_voltages = 1,
984*4882a593Smuzhiyun .enable_reg = RK805_DCDC_EN_REG,
985*4882a593Smuzhiyun .enable_mask = ENABLE_MASK(RK805_ID_DCDC3),
986*4882a593Smuzhiyun .enable_val = ENABLE_MASK(RK805_ID_DCDC3),
987*4882a593Smuzhiyun .disable_val = DISABLE_VAL(RK805_ID_DCDC3),
988*4882a593Smuzhiyun .of_map_mode = rk8xx_regulator_of_map_mode,
989*4882a593Smuzhiyun .owner = THIS_MODULE,
990*4882a593Smuzhiyun }, {
991*4882a593Smuzhiyun .name = "DCDC_REG4",
992*4882a593Smuzhiyun .supply_name = "vcc4",
993*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG4"),
994*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
995*4882a593Smuzhiyun .id = RK805_ID_DCDC4,
996*4882a593Smuzhiyun .ops = &rk808_reg_ops_ranges,
997*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
998*4882a593Smuzhiyun .n_voltages = 32,
999*4882a593Smuzhiyun .linear_ranges = rk805_buck4_voltage_ranges,
1000*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(rk805_buck4_voltage_ranges),
1001*4882a593Smuzhiyun .vsel_reg = RK805_BUCK4_ON_VSEL_REG,
1002*4882a593Smuzhiyun .vsel_mask = RK818_BUCK4_VSEL_MASK,
1003*4882a593Smuzhiyun .enable_reg = RK805_DCDC_EN_REG,
1004*4882a593Smuzhiyun .enable_mask = ENABLE_MASK(RK805_ID_DCDC4),
1005*4882a593Smuzhiyun .enable_val = ENABLE_MASK(RK805_ID_DCDC4),
1006*4882a593Smuzhiyun .disable_val = DISABLE_VAL(RK805_ID_DCDC4),
1007*4882a593Smuzhiyun .of_map_mode = rk8xx_regulator_of_map_mode,
1008*4882a593Smuzhiyun .owner = THIS_MODULE,
1009*4882a593Smuzhiyun },
1010*4882a593Smuzhiyun
1011*4882a593Smuzhiyun RK805_DESC(RK805_ID_LDO1, "LDO_REG1", "vcc5", 800, 3400, 100,
1012*4882a593Smuzhiyun RK805_LDO1_ON_VSEL_REG, RK818_LDO_VSEL_MASK, RK805_LDO_EN_REG,
1013*4882a593Smuzhiyun ENABLE_MASK(0), DISABLE_VAL(0), 400),
1014*4882a593Smuzhiyun RK805_DESC(RK805_ID_LDO2, "LDO_REG2", "vcc5", 800, 3400, 100,
1015*4882a593Smuzhiyun RK805_LDO2_ON_VSEL_REG, RK818_LDO_VSEL_MASK, RK805_LDO_EN_REG,
1016*4882a593Smuzhiyun ENABLE_MASK(1), DISABLE_VAL(1), 400),
1017*4882a593Smuzhiyun RK805_DESC(RK805_ID_LDO3, "LDO_REG3", "vcc6", 800, 3400, 100,
1018*4882a593Smuzhiyun RK805_LDO3_ON_VSEL_REG, RK818_LDO_VSEL_MASK, RK805_LDO_EN_REG,
1019*4882a593Smuzhiyun ENABLE_MASK(2), DISABLE_VAL(2), 400),
1020*4882a593Smuzhiyun };
1021*4882a593Smuzhiyun
1022*4882a593Smuzhiyun static const struct regulator_desc rk808_reg[] = {
1023*4882a593Smuzhiyun {
1024*4882a593Smuzhiyun .name = "DCDC_REG1",
1025*4882a593Smuzhiyun .supply_name = "vcc1",
1026*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG1"),
1027*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1028*4882a593Smuzhiyun .id = RK808_ID_DCDC1,
1029*4882a593Smuzhiyun .ops = &rk808_buck1_2_ops,
1030*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1031*4882a593Smuzhiyun .min_uV = 712500,
1032*4882a593Smuzhiyun .uV_step = 12500,
1033*4882a593Smuzhiyun .n_voltages = 64,
1034*4882a593Smuzhiyun .vsel_reg = RK808_BUCK1_ON_VSEL_REG,
1035*4882a593Smuzhiyun .vsel_mask = RK808_BUCK_VSEL_MASK,
1036*4882a593Smuzhiyun .enable_reg = RK808_DCDC_EN_REG,
1037*4882a593Smuzhiyun .enable_mask = BIT(0),
1038*4882a593Smuzhiyun .owner = THIS_MODULE,
1039*4882a593Smuzhiyun }, {
1040*4882a593Smuzhiyun .name = "DCDC_REG2",
1041*4882a593Smuzhiyun .supply_name = "vcc2",
1042*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG2"),
1043*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1044*4882a593Smuzhiyun .id = RK808_ID_DCDC2,
1045*4882a593Smuzhiyun .ops = &rk808_buck1_2_ops,
1046*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1047*4882a593Smuzhiyun .min_uV = 712500,
1048*4882a593Smuzhiyun .uV_step = 12500,
1049*4882a593Smuzhiyun .n_voltages = 64,
1050*4882a593Smuzhiyun .vsel_reg = RK808_BUCK2_ON_VSEL_REG,
1051*4882a593Smuzhiyun .vsel_mask = RK808_BUCK_VSEL_MASK,
1052*4882a593Smuzhiyun .enable_reg = RK808_DCDC_EN_REG,
1053*4882a593Smuzhiyun .enable_mask = BIT(1),
1054*4882a593Smuzhiyun .owner = THIS_MODULE,
1055*4882a593Smuzhiyun }, {
1056*4882a593Smuzhiyun .name = "DCDC_REG3",
1057*4882a593Smuzhiyun .supply_name = "vcc3",
1058*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG3"),
1059*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1060*4882a593Smuzhiyun .id = RK808_ID_DCDC3,
1061*4882a593Smuzhiyun .ops = &rk808_switch_ops,
1062*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1063*4882a593Smuzhiyun .n_voltages = 1,
1064*4882a593Smuzhiyun .enable_reg = RK808_DCDC_EN_REG,
1065*4882a593Smuzhiyun .enable_mask = BIT(2),
1066*4882a593Smuzhiyun .owner = THIS_MODULE,
1067*4882a593Smuzhiyun },
1068*4882a593Smuzhiyun RK8XX_DESC(RK808_ID_DCDC4, "DCDC_REG4", "vcc4", 1800, 3300, 100,
1069*4882a593Smuzhiyun RK808_BUCK4_ON_VSEL_REG, RK808_BUCK4_VSEL_MASK,
1070*4882a593Smuzhiyun RK808_DCDC_EN_REG, BIT(3), 0),
1071*4882a593Smuzhiyun RK8XX_DESC(RK808_ID_LDO1, "LDO_REG1", "vcc6", 1800, 3400, 100,
1072*4882a593Smuzhiyun RK808_LDO1_ON_VSEL_REG, RK808_LDO_VSEL_MASK, RK808_LDO_EN_REG,
1073*4882a593Smuzhiyun BIT(0), 400),
1074*4882a593Smuzhiyun RK8XX_DESC(RK808_ID_LDO2, "LDO_REG2", "vcc6", 1800, 3400, 100,
1075*4882a593Smuzhiyun RK808_LDO2_ON_VSEL_REG, RK808_LDO_VSEL_MASK, RK808_LDO_EN_REG,
1076*4882a593Smuzhiyun BIT(1), 400),
1077*4882a593Smuzhiyun {
1078*4882a593Smuzhiyun .name = "LDO_REG3",
1079*4882a593Smuzhiyun .supply_name = "vcc7",
1080*4882a593Smuzhiyun .of_match = of_match_ptr("LDO_REG3"),
1081*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1082*4882a593Smuzhiyun .id = RK808_ID_LDO3,
1083*4882a593Smuzhiyun .ops = &rk808_reg_ops_ranges,
1084*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1085*4882a593Smuzhiyun .n_voltages = 16,
1086*4882a593Smuzhiyun .linear_ranges = rk808_ldo3_voltage_ranges,
1087*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(rk808_ldo3_voltage_ranges),
1088*4882a593Smuzhiyun .vsel_reg = RK808_LDO3_ON_VSEL_REG,
1089*4882a593Smuzhiyun .vsel_mask = RK808_BUCK4_VSEL_MASK,
1090*4882a593Smuzhiyun .enable_reg = RK808_LDO_EN_REG,
1091*4882a593Smuzhiyun .enable_mask = BIT(2),
1092*4882a593Smuzhiyun .enable_time = 400,
1093*4882a593Smuzhiyun .owner = THIS_MODULE,
1094*4882a593Smuzhiyun },
1095*4882a593Smuzhiyun RK8XX_DESC(RK808_ID_LDO4, "LDO_REG4", "vcc9", 1800, 3400, 100,
1096*4882a593Smuzhiyun RK808_LDO4_ON_VSEL_REG, RK808_LDO_VSEL_MASK, RK808_LDO_EN_REG,
1097*4882a593Smuzhiyun BIT(3), 400),
1098*4882a593Smuzhiyun RK8XX_DESC(RK808_ID_LDO5, "LDO_REG5", "vcc9", 1800, 3400, 100,
1099*4882a593Smuzhiyun RK808_LDO5_ON_VSEL_REG, RK808_LDO_VSEL_MASK, RK808_LDO_EN_REG,
1100*4882a593Smuzhiyun BIT(4), 400),
1101*4882a593Smuzhiyun RK8XX_DESC(RK808_ID_LDO6, "LDO_REG6", "vcc10", 800, 2500, 100,
1102*4882a593Smuzhiyun RK808_LDO6_ON_VSEL_REG, RK808_LDO_VSEL_MASK, RK808_LDO_EN_REG,
1103*4882a593Smuzhiyun BIT(5), 400),
1104*4882a593Smuzhiyun RK8XX_DESC(RK808_ID_LDO7, "LDO_REG7", "vcc7", 800, 2500, 100,
1105*4882a593Smuzhiyun RK808_LDO7_ON_VSEL_REG, RK808_LDO_VSEL_MASK, RK808_LDO_EN_REG,
1106*4882a593Smuzhiyun BIT(6), 400),
1107*4882a593Smuzhiyun RK8XX_DESC(RK808_ID_LDO8, "LDO_REG8", "vcc11", 1800, 3400, 100,
1108*4882a593Smuzhiyun RK808_LDO8_ON_VSEL_REG, RK808_LDO_VSEL_MASK, RK808_LDO_EN_REG,
1109*4882a593Smuzhiyun BIT(7), 400),
1110*4882a593Smuzhiyun RK8XX_DESC_SWITCH(RK808_ID_SWITCH1, "SWITCH_REG1", "vcc8",
1111*4882a593Smuzhiyun RK808_DCDC_EN_REG, BIT(5)),
1112*4882a593Smuzhiyun RK8XX_DESC_SWITCH(RK808_ID_SWITCH2, "SWITCH_REG2", "vcc12",
1113*4882a593Smuzhiyun RK808_DCDC_EN_REG, BIT(6)),
1114*4882a593Smuzhiyun };
1115*4882a593Smuzhiyun
1116*4882a593Smuzhiyun static const struct regulator_desc rk816_reg[] = {
1117*4882a593Smuzhiyun {
1118*4882a593Smuzhiyun .name = "DCDC_REG1",
1119*4882a593Smuzhiyun .supply_name = "vcc1",
1120*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG1"),
1121*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1122*4882a593Smuzhiyun .id = RK816_ID_DCDC1,
1123*4882a593Smuzhiyun .ops = &rk816_buck1_2_ops_ranges,
1124*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1125*4882a593Smuzhiyun .n_voltages = 64,
1126*4882a593Smuzhiyun .linear_ranges = rk816_buck_voltage_ranges,
1127*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(rk816_buck_voltage_ranges),
1128*4882a593Smuzhiyun .vsel_reg = RK816_BUCK1_ON_VSEL_REG,
1129*4882a593Smuzhiyun .vsel_mask = RK818_BUCK_VSEL_MASK,
1130*4882a593Smuzhiyun .enable_reg = RK816_DCDC_EN_REG1,
1131*4882a593Smuzhiyun .enable_mask = BIT(4) | BIT(0),
1132*4882a593Smuzhiyun .enable_val = BIT(4) | BIT(0),
1133*4882a593Smuzhiyun .disable_val = BIT(4),
1134*4882a593Smuzhiyun .of_map_mode = rk8xx_regulator_of_map_mode,
1135*4882a593Smuzhiyun .owner = THIS_MODULE,
1136*4882a593Smuzhiyun }, {
1137*4882a593Smuzhiyun .name = "DCDC_REG2",
1138*4882a593Smuzhiyun .supply_name = "vcc2",
1139*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG2"),
1140*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1141*4882a593Smuzhiyun .id = RK816_ID_DCDC2,
1142*4882a593Smuzhiyun .ops = &rk816_buck1_2_ops_ranges,
1143*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1144*4882a593Smuzhiyun .n_voltages = 64,
1145*4882a593Smuzhiyun .linear_ranges = rk816_buck_voltage_ranges,
1146*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(rk816_buck_voltage_ranges),
1147*4882a593Smuzhiyun .vsel_reg = RK816_BUCK2_ON_VSEL_REG,
1148*4882a593Smuzhiyun .vsel_mask = RK818_BUCK_VSEL_MASK,
1149*4882a593Smuzhiyun .enable_reg = RK816_DCDC_EN_REG1,
1150*4882a593Smuzhiyun .enable_mask = BIT(5) | BIT(1),
1151*4882a593Smuzhiyun .enable_val = BIT(5) | BIT(1),
1152*4882a593Smuzhiyun .disable_val = BIT(5),
1153*4882a593Smuzhiyun .of_map_mode = rk8xx_regulator_of_map_mode,
1154*4882a593Smuzhiyun .owner = THIS_MODULE,
1155*4882a593Smuzhiyun }, {
1156*4882a593Smuzhiyun .name = "DCDC_REG3",
1157*4882a593Smuzhiyun .supply_name = "vcc3",
1158*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG3"),
1159*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1160*4882a593Smuzhiyun .id = RK818_ID_DCDC3,
1161*4882a593Smuzhiyun .ops = &rk808_switch_ops,
1162*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1163*4882a593Smuzhiyun .n_voltages = 1,
1164*4882a593Smuzhiyun .enable_reg = RK816_DCDC_EN_REG1,
1165*4882a593Smuzhiyun .enable_mask = BIT(6) | BIT(2),
1166*4882a593Smuzhiyun .enable_val = BIT(6) | BIT(2),
1167*4882a593Smuzhiyun .disable_val = BIT(6),
1168*4882a593Smuzhiyun .of_map_mode = rk8xx_regulator_of_map_mode,
1169*4882a593Smuzhiyun .owner = THIS_MODULE,
1170*4882a593Smuzhiyun }, {
1171*4882a593Smuzhiyun .name = "DCDC_REG4",
1172*4882a593Smuzhiyun .supply_name = "vcc4",
1173*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG4"),
1174*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1175*4882a593Smuzhiyun .id = RK816_ID_DCDC4,
1176*4882a593Smuzhiyun .ops = &rk808_reg_ops_ranges,
1177*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1178*4882a593Smuzhiyun .n_voltages = 32,
1179*4882a593Smuzhiyun .linear_ranges = rk816_buck4_voltage_ranges,
1180*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(rk816_buck4_voltage_ranges),
1181*4882a593Smuzhiyun .vsel_reg = RK816_BUCK4_ON_VSEL_REG,
1182*4882a593Smuzhiyun .vsel_mask = RK818_BUCK4_VSEL_MASK,
1183*4882a593Smuzhiyun .enable_reg = RK816_DCDC_EN_REG1,
1184*4882a593Smuzhiyun .enable_mask = BIT(7) | BIT(3),
1185*4882a593Smuzhiyun .enable_val = BIT(7) | BIT(3),
1186*4882a593Smuzhiyun .disable_val = BIT(7),
1187*4882a593Smuzhiyun .of_map_mode = rk8xx_regulator_of_map_mode,
1188*4882a593Smuzhiyun .owner = THIS_MODULE,
1189*4882a593Smuzhiyun },
1190*4882a593Smuzhiyun
1191*4882a593Smuzhiyun RK816_DESC(RK816_ID_LDO1, "LDO_REG1", "vcc5", 800, 3400, 100,
1192*4882a593Smuzhiyun RK816_LDO1_ON_VSEL_REG, RK818_LDO_VSEL_MASK,
1193*4882a593Smuzhiyun RK816_LDO_EN_REG1, ENABLE_MASK(0), DISABLE_VAL(0), 400),
1194*4882a593Smuzhiyun RK816_DESC(RK816_ID_LDO2, "LDO_REG2", "vcc5", 800, 3400, 100,
1195*4882a593Smuzhiyun RK816_LDO2_ON_VSEL_REG, RK818_LDO_VSEL_MASK,
1196*4882a593Smuzhiyun RK816_LDO_EN_REG1, ENABLE_MASK(1), DISABLE_VAL(1), 400),
1197*4882a593Smuzhiyun RK816_DESC(RK816_ID_LDO3, "LDO_REG3", "vcc5", 800, 3400, 100,
1198*4882a593Smuzhiyun RK816_LDO3_ON_VSEL_REG, RK818_LDO_VSEL_MASK,
1199*4882a593Smuzhiyun RK816_LDO_EN_REG1, ENABLE_MASK(2), DISABLE_VAL(2), 400),
1200*4882a593Smuzhiyun RK816_DESC(RK816_ID_LDO4, "LDO_REG4", "vcc6", 800, 3400, 100,
1201*4882a593Smuzhiyun RK816_LDO4_ON_VSEL_REG, RK818_LDO_VSEL_MASK,
1202*4882a593Smuzhiyun RK816_LDO_EN_REG1, ENABLE_MASK(3), DISABLE_VAL(3), 400),
1203*4882a593Smuzhiyun RK816_DESC(RK816_ID_LDO5, "LDO_REG5", "vcc6", 800, 3400, 100,
1204*4882a593Smuzhiyun RK816_LDO5_ON_VSEL_REG, RK818_LDO_VSEL_MASK,
1205*4882a593Smuzhiyun RK816_LDO_EN_REG2, ENABLE_MASK(0), DISABLE_VAL(0), 400),
1206*4882a593Smuzhiyun RK816_DESC(RK816_ID_LDO6, "LDO_REG6", "vcc6", 800, 3400, 100,
1207*4882a593Smuzhiyun RK816_LDO6_ON_VSEL_REG, RK818_LDO_VSEL_MASK,
1208*4882a593Smuzhiyun RK816_LDO_EN_REG2, ENABLE_MASK(1), DISABLE_VAL(1), 400),
1209*4882a593Smuzhiyun };
1210*4882a593Smuzhiyun
1211*4882a593Smuzhiyun static const struct regulator_desc rk809_reg[] = {
1212*4882a593Smuzhiyun {
1213*4882a593Smuzhiyun .name = "DCDC_REG1",
1214*4882a593Smuzhiyun .supply_name = "vcc1",
1215*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG1"),
1216*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1217*4882a593Smuzhiyun .id = RK817_ID_DCDC1,
1218*4882a593Smuzhiyun .ops = &rk817_buck_ops_range,
1219*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1220*4882a593Smuzhiyun .n_voltages = RK817_BUCK1_SEL_CNT + 1,
1221*4882a593Smuzhiyun .linear_ranges = rk817_buck1_voltage_ranges,
1222*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(rk817_buck1_voltage_ranges),
1223*4882a593Smuzhiyun .vsel_reg = RK817_BUCK1_ON_VSEL_REG,
1224*4882a593Smuzhiyun .vsel_mask = RK817_BUCK_VSEL_MASK,
1225*4882a593Smuzhiyun .enable_reg = RK817_POWER_EN_REG(0),
1226*4882a593Smuzhiyun .enable_mask = ENABLE_MASK(RK817_ID_DCDC1),
1227*4882a593Smuzhiyun .enable_val = BIT(RK817_ID_DCDC1),
1228*4882a593Smuzhiyun .disable_val = DISABLE_VAL(RK817_ID_DCDC1),
1229*4882a593Smuzhiyun .of_map_mode = rk8xx_regulator_of_map_mode,
1230*4882a593Smuzhiyun .owner = THIS_MODULE,
1231*4882a593Smuzhiyun }, {
1232*4882a593Smuzhiyun .name = "DCDC_REG2",
1233*4882a593Smuzhiyun .supply_name = "vcc2",
1234*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG2"),
1235*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1236*4882a593Smuzhiyun .id = RK817_ID_DCDC2,
1237*4882a593Smuzhiyun .ops = &rk817_buck_ops_range,
1238*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1239*4882a593Smuzhiyun .n_voltages = RK817_BUCK1_SEL_CNT + 1,
1240*4882a593Smuzhiyun .linear_ranges = rk817_buck1_voltage_ranges,
1241*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(rk817_buck1_voltage_ranges),
1242*4882a593Smuzhiyun .vsel_reg = RK817_BUCK2_ON_VSEL_REG,
1243*4882a593Smuzhiyun .vsel_mask = RK817_BUCK_VSEL_MASK,
1244*4882a593Smuzhiyun .enable_reg = RK817_POWER_EN_REG(0),
1245*4882a593Smuzhiyun .enable_mask = ENABLE_MASK(RK817_ID_DCDC2),
1246*4882a593Smuzhiyun .enable_val = BIT(RK817_ID_DCDC2),
1247*4882a593Smuzhiyun .disable_val = DISABLE_VAL(RK817_ID_DCDC2),
1248*4882a593Smuzhiyun .of_map_mode = rk8xx_regulator_of_map_mode,
1249*4882a593Smuzhiyun .owner = THIS_MODULE,
1250*4882a593Smuzhiyun }, {
1251*4882a593Smuzhiyun .name = "DCDC_REG3",
1252*4882a593Smuzhiyun .supply_name = "vcc3",
1253*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG3"),
1254*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1255*4882a593Smuzhiyun .id = RK817_ID_DCDC3,
1256*4882a593Smuzhiyun .ops = &rk817_buck_ops_range,
1257*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1258*4882a593Smuzhiyun .n_voltages = RK817_BUCK1_SEL_CNT + 1,
1259*4882a593Smuzhiyun .linear_ranges = rk817_buck1_voltage_ranges,
1260*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(rk817_buck1_voltage_ranges),
1261*4882a593Smuzhiyun .vsel_reg = RK817_BUCK3_ON_VSEL_REG,
1262*4882a593Smuzhiyun .vsel_mask = RK817_BUCK_VSEL_MASK,
1263*4882a593Smuzhiyun .enable_reg = RK817_POWER_EN_REG(0),
1264*4882a593Smuzhiyun .enable_mask = ENABLE_MASK(RK817_ID_DCDC3),
1265*4882a593Smuzhiyun .enable_val = BIT(RK817_ID_DCDC3),
1266*4882a593Smuzhiyun .disable_val = DISABLE_VAL(RK817_ID_DCDC3),
1267*4882a593Smuzhiyun .of_map_mode = rk8xx_regulator_of_map_mode,
1268*4882a593Smuzhiyun .owner = THIS_MODULE,
1269*4882a593Smuzhiyun }, {
1270*4882a593Smuzhiyun .name = "DCDC_REG4",
1271*4882a593Smuzhiyun .supply_name = "vcc4",
1272*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG4"),
1273*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1274*4882a593Smuzhiyun .id = RK817_ID_DCDC4,
1275*4882a593Smuzhiyun .ops = &rk817_buck_ops_range,
1276*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1277*4882a593Smuzhiyun .n_voltages = RK817_BUCK3_SEL_CNT + 1,
1278*4882a593Smuzhiyun .linear_ranges = rk817_buck3_voltage_ranges,
1279*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(rk817_buck3_voltage_ranges),
1280*4882a593Smuzhiyun .vsel_reg = RK817_BUCK4_ON_VSEL_REG,
1281*4882a593Smuzhiyun .vsel_mask = RK817_BUCK_VSEL_MASK,
1282*4882a593Smuzhiyun .enable_reg = RK817_POWER_EN_REG(0),
1283*4882a593Smuzhiyun .enable_mask = ENABLE_MASK(RK817_ID_DCDC4),
1284*4882a593Smuzhiyun .enable_val = BIT(RK817_ID_DCDC4),
1285*4882a593Smuzhiyun .disable_val = DISABLE_VAL(RK817_ID_DCDC4),
1286*4882a593Smuzhiyun .of_map_mode = rk8xx_regulator_of_map_mode,
1287*4882a593Smuzhiyun .owner = THIS_MODULE,
1288*4882a593Smuzhiyun },
1289*4882a593Smuzhiyun {
1290*4882a593Smuzhiyun .name = "DCDC_REG5",
1291*4882a593Smuzhiyun .supply_name = "vcc9",
1292*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG5"),
1293*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1294*4882a593Smuzhiyun .id = RK809_ID_DCDC5,
1295*4882a593Smuzhiyun .ops = &rk809_buck5_ops_range,
1296*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1297*4882a593Smuzhiyun .n_voltages = RK809_BUCK5_SEL_CNT,
1298*4882a593Smuzhiyun .linear_ranges = rk809_buck5_voltage_ranges,
1299*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(rk809_buck5_voltage_ranges),
1300*4882a593Smuzhiyun .vsel_reg = RK809_BUCK5_CONFIG(0),
1301*4882a593Smuzhiyun .vsel_mask = RK809_BUCK5_VSEL_MASK,
1302*4882a593Smuzhiyun .enable_reg = RK817_POWER_EN_REG(3),
1303*4882a593Smuzhiyun .enable_mask = ENABLE_MASK(1),
1304*4882a593Smuzhiyun .enable_val = BIT(1),
1305*4882a593Smuzhiyun .disable_val = DISABLE_VAL(1),
1306*4882a593Smuzhiyun .of_map_mode = rk8xx_regulator_of_map_mode,
1307*4882a593Smuzhiyun .owner = THIS_MODULE,
1308*4882a593Smuzhiyun },
1309*4882a593Smuzhiyun RK817_DESC(RK817_ID_LDO1, "LDO_REG1", "vcc5", 600, 3400, 25,
1310*4882a593Smuzhiyun RK817_LDO_ON_VSEL_REG(0), RK817_LDO_VSEL_MASK,
1311*4882a593Smuzhiyun RK817_POWER_EN_REG(1), ENABLE_MASK(0), BIT(0),
1312*4882a593Smuzhiyun DISABLE_VAL(0), 400),
1313*4882a593Smuzhiyun RK817_DESC(RK817_ID_LDO2, "LDO_REG2", "vcc5", 600, 3400, 25,
1314*4882a593Smuzhiyun RK817_LDO_ON_VSEL_REG(1), RK817_LDO_VSEL_MASK,
1315*4882a593Smuzhiyun RK817_POWER_EN_REG(1), ENABLE_MASK(1), BIT(1),
1316*4882a593Smuzhiyun DISABLE_VAL(1), 400),
1317*4882a593Smuzhiyun RK817_DESC(RK817_ID_LDO3, "LDO_REG3", "vcc5", 600, 3400, 25,
1318*4882a593Smuzhiyun RK817_LDO_ON_VSEL_REG(2), RK817_LDO_VSEL_MASK,
1319*4882a593Smuzhiyun RK817_POWER_EN_REG(1), ENABLE_MASK(2), BIT(2),
1320*4882a593Smuzhiyun DISABLE_VAL(2), 400),
1321*4882a593Smuzhiyun RK817_DESC(RK817_ID_LDO4, "LDO_REG4", "vcc6", 600, 3400, 25,
1322*4882a593Smuzhiyun RK817_LDO_ON_VSEL_REG(3), RK817_LDO_VSEL_MASK,
1323*4882a593Smuzhiyun RK817_POWER_EN_REG(1), ENABLE_MASK(3), BIT(3),
1324*4882a593Smuzhiyun DISABLE_VAL(3), 400),
1325*4882a593Smuzhiyun RK817_DESC(RK817_ID_LDO5, "LDO_REG5", "vcc6", 600, 3400, 25,
1326*4882a593Smuzhiyun RK817_LDO_ON_VSEL_REG(4), RK817_LDO_VSEL_MASK,
1327*4882a593Smuzhiyun RK817_POWER_EN_REG(2), ENABLE_MASK(0), BIT(0),
1328*4882a593Smuzhiyun DISABLE_VAL(0), 400),
1329*4882a593Smuzhiyun RK817_DESC(RK817_ID_LDO6, "LDO_REG6", "vcc6", 600, 3400, 25,
1330*4882a593Smuzhiyun RK817_LDO_ON_VSEL_REG(5), RK817_LDO_VSEL_MASK,
1331*4882a593Smuzhiyun RK817_POWER_EN_REG(2), ENABLE_MASK(1), BIT(1),
1332*4882a593Smuzhiyun DISABLE_VAL(1), 400),
1333*4882a593Smuzhiyun RK817_DESC(RK817_ID_LDO7, "LDO_REG7", "vcc7", 600, 3400, 25,
1334*4882a593Smuzhiyun RK817_LDO_ON_VSEL_REG(6), RK817_LDO_VSEL_MASK,
1335*4882a593Smuzhiyun RK817_POWER_EN_REG(2), ENABLE_MASK(2), BIT(2),
1336*4882a593Smuzhiyun DISABLE_VAL(2), 400),
1337*4882a593Smuzhiyun RK817_DESC(RK817_ID_LDO8, "LDO_REG8", "vcc7", 600, 3400, 25,
1338*4882a593Smuzhiyun RK817_LDO_ON_VSEL_REG(7), RK817_LDO_VSEL_MASK,
1339*4882a593Smuzhiyun RK817_POWER_EN_REG(2), ENABLE_MASK(3), BIT(3),
1340*4882a593Smuzhiyun DISABLE_VAL(3), 400),
1341*4882a593Smuzhiyun RK817_DESC(RK817_ID_LDO9, "LDO_REG9", "vcc7", 600, 3400, 25,
1342*4882a593Smuzhiyun RK817_LDO_ON_VSEL_REG(8), RK817_LDO_VSEL_MASK,
1343*4882a593Smuzhiyun RK817_POWER_EN_REG(3), ENABLE_MASK(0), BIT(0),
1344*4882a593Smuzhiyun DISABLE_VAL(0), 400),
1345*4882a593Smuzhiyun RK817_DESC_SWITCH(RK809_ID_SW1, "SWITCH_REG1", "vcc9",
1346*4882a593Smuzhiyun RK817_POWER_EN_REG(3), ENABLE_MASK(2), BIT(2),
1347*4882a593Smuzhiyun DISABLE_VAL(2)),
1348*4882a593Smuzhiyun RK817_DESC_SWITCH(RK809_ID_SW2, "SWITCH_REG2", "vcc8",
1349*4882a593Smuzhiyun RK817_POWER_EN_REG(3), ENABLE_MASK(3), BIT(3),
1350*4882a593Smuzhiyun DISABLE_VAL(3)),
1351*4882a593Smuzhiyun };
1352*4882a593Smuzhiyun
1353*4882a593Smuzhiyun static const struct regulator_desc rk817_reg[] = {
1354*4882a593Smuzhiyun {
1355*4882a593Smuzhiyun .name = "DCDC_REG1",
1356*4882a593Smuzhiyun .supply_name = "vcc1",
1357*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG1"),
1358*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1359*4882a593Smuzhiyun .id = RK817_ID_DCDC1,
1360*4882a593Smuzhiyun .ops = &rk817_buck_ops_range,
1361*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1362*4882a593Smuzhiyun .n_voltages = RK817_BUCK1_SEL_CNT + 1,
1363*4882a593Smuzhiyun .linear_ranges = rk817_buck1_voltage_ranges,
1364*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(rk817_buck1_voltage_ranges),
1365*4882a593Smuzhiyun .vsel_reg = RK817_BUCK1_ON_VSEL_REG,
1366*4882a593Smuzhiyun .vsel_mask = RK817_BUCK_VSEL_MASK,
1367*4882a593Smuzhiyun .enable_reg = RK817_POWER_EN_REG(0),
1368*4882a593Smuzhiyun .enable_mask = ENABLE_MASK(RK817_ID_DCDC1),
1369*4882a593Smuzhiyun .enable_val = ENABLE_MASK(RK817_ID_DCDC1),
1370*4882a593Smuzhiyun .disable_val = DISABLE_VAL(RK817_ID_DCDC1),
1371*4882a593Smuzhiyun .of_map_mode = rk8xx_regulator_of_map_mode,
1372*4882a593Smuzhiyun .owner = THIS_MODULE,
1373*4882a593Smuzhiyun }, {
1374*4882a593Smuzhiyun .name = "DCDC_REG2",
1375*4882a593Smuzhiyun .supply_name = "vcc2",
1376*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG2"),
1377*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1378*4882a593Smuzhiyun .id = RK817_ID_DCDC2,
1379*4882a593Smuzhiyun .ops = &rk817_buck_ops_range,
1380*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1381*4882a593Smuzhiyun .n_voltages = RK817_BUCK1_SEL_CNT + 1,
1382*4882a593Smuzhiyun .linear_ranges = rk817_buck1_voltage_ranges,
1383*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(rk817_buck1_voltage_ranges),
1384*4882a593Smuzhiyun .vsel_reg = RK817_BUCK2_ON_VSEL_REG,
1385*4882a593Smuzhiyun .vsel_mask = RK817_BUCK_VSEL_MASK,
1386*4882a593Smuzhiyun .enable_reg = RK817_POWER_EN_REG(0),
1387*4882a593Smuzhiyun .enable_mask = ENABLE_MASK(RK817_ID_DCDC2),
1388*4882a593Smuzhiyun .enable_val = ENABLE_MASK(RK817_ID_DCDC2),
1389*4882a593Smuzhiyun .disable_val = DISABLE_VAL(RK817_ID_DCDC2),
1390*4882a593Smuzhiyun .of_map_mode = rk8xx_regulator_of_map_mode,
1391*4882a593Smuzhiyun .owner = THIS_MODULE,
1392*4882a593Smuzhiyun }, {
1393*4882a593Smuzhiyun .name = "DCDC_REG3",
1394*4882a593Smuzhiyun .supply_name = "vcc3",
1395*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG3"),
1396*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1397*4882a593Smuzhiyun .id = RK817_ID_DCDC3,
1398*4882a593Smuzhiyun .ops = &rk817_buck_ops_range,
1399*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1400*4882a593Smuzhiyun .n_voltages = RK817_BUCK1_SEL_CNT + 1,
1401*4882a593Smuzhiyun .linear_ranges = rk817_buck1_voltage_ranges,
1402*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(rk817_buck1_voltage_ranges),
1403*4882a593Smuzhiyun .vsel_reg = RK817_BUCK3_ON_VSEL_REG,
1404*4882a593Smuzhiyun .vsel_mask = RK817_BUCK_VSEL_MASK,
1405*4882a593Smuzhiyun .enable_reg = RK817_POWER_EN_REG(0),
1406*4882a593Smuzhiyun .enable_mask = ENABLE_MASK(RK817_ID_DCDC3),
1407*4882a593Smuzhiyun .enable_val = ENABLE_MASK(RK817_ID_DCDC3),
1408*4882a593Smuzhiyun .disable_val = DISABLE_VAL(RK817_ID_DCDC3),
1409*4882a593Smuzhiyun .of_map_mode = rk8xx_regulator_of_map_mode,
1410*4882a593Smuzhiyun .owner = THIS_MODULE,
1411*4882a593Smuzhiyun }, {
1412*4882a593Smuzhiyun .name = "DCDC_REG4",
1413*4882a593Smuzhiyun .supply_name = "vcc4",
1414*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG4"),
1415*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1416*4882a593Smuzhiyun .id = RK817_ID_DCDC4,
1417*4882a593Smuzhiyun .ops = &rk817_buck_ops_range,
1418*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1419*4882a593Smuzhiyun .n_voltages = RK817_BUCK3_SEL_CNT + 1,
1420*4882a593Smuzhiyun .linear_ranges = rk817_buck3_voltage_ranges,
1421*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(rk817_buck3_voltage_ranges),
1422*4882a593Smuzhiyun .vsel_reg = RK817_BUCK4_ON_VSEL_REG,
1423*4882a593Smuzhiyun .vsel_mask = RK817_BUCK_VSEL_MASK,
1424*4882a593Smuzhiyun .enable_reg = RK817_POWER_EN_REG(0),
1425*4882a593Smuzhiyun .enable_mask = ENABLE_MASK(RK817_ID_DCDC4),
1426*4882a593Smuzhiyun .enable_val = ENABLE_MASK(RK817_ID_DCDC4),
1427*4882a593Smuzhiyun .disable_val = DISABLE_VAL(RK817_ID_DCDC4),
1428*4882a593Smuzhiyun .of_map_mode = rk8xx_regulator_of_map_mode,
1429*4882a593Smuzhiyun .owner = THIS_MODULE,
1430*4882a593Smuzhiyun },
1431*4882a593Smuzhiyun RK817_DESC(RK817_ID_LDO1, "LDO_REG1", "vcc5", 600, 3400, 25,
1432*4882a593Smuzhiyun RK817_LDO_ON_VSEL_REG(0), RK817_LDO_VSEL_MASK,
1433*4882a593Smuzhiyun RK817_POWER_EN_REG(1), ENABLE_MASK(0), BIT(0),
1434*4882a593Smuzhiyun DISABLE_VAL(0), 400),
1435*4882a593Smuzhiyun RK817_DESC(RK817_ID_LDO2, "LDO_REG2", "vcc5", 600, 3400, 25,
1436*4882a593Smuzhiyun RK817_LDO_ON_VSEL_REG(1), RK817_LDO_VSEL_MASK,
1437*4882a593Smuzhiyun RK817_POWER_EN_REG(1), ENABLE_MASK(1), BIT(1),
1438*4882a593Smuzhiyun DISABLE_VAL(1), 400),
1439*4882a593Smuzhiyun RK817_DESC(RK817_ID_LDO3, "LDO_REG3", "vcc5", 600, 3400, 25,
1440*4882a593Smuzhiyun RK817_LDO_ON_VSEL_REG(2), RK817_LDO_VSEL_MASK,
1441*4882a593Smuzhiyun RK817_POWER_EN_REG(1), ENABLE_MASK(2), BIT(2),
1442*4882a593Smuzhiyun DISABLE_VAL(2), 400),
1443*4882a593Smuzhiyun RK817_DESC(RK817_ID_LDO4, "LDO_REG4", "vcc6", 600, 3400, 25,
1444*4882a593Smuzhiyun RK817_LDO_ON_VSEL_REG(3), RK817_LDO_VSEL_MASK,
1445*4882a593Smuzhiyun RK817_POWER_EN_REG(1), ENABLE_MASK(3), BIT(3),
1446*4882a593Smuzhiyun DISABLE_VAL(3), 400),
1447*4882a593Smuzhiyun RK817_DESC(RK817_ID_LDO5, "LDO_REG5", "vcc6", 600, 3400, 25,
1448*4882a593Smuzhiyun RK817_LDO_ON_VSEL_REG(4), RK817_LDO_VSEL_MASK,
1449*4882a593Smuzhiyun RK817_POWER_EN_REG(2), ENABLE_MASK(0), BIT(0),
1450*4882a593Smuzhiyun DISABLE_VAL(0), 400),
1451*4882a593Smuzhiyun RK817_DESC(RK817_ID_LDO6, "LDO_REG6", "vcc6", 600, 3400, 25,
1452*4882a593Smuzhiyun RK817_LDO_ON_VSEL_REG(5), RK817_LDO_VSEL_MASK,
1453*4882a593Smuzhiyun RK817_POWER_EN_REG(2), ENABLE_MASK(1), BIT(1),
1454*4882a593Smuzhiyun DISABLE_VAL(1), 400),
1455*4882a593Smuzhiyun RK817_DESC(RK817_ID_LDO7, "LDO_REG7", "vcc7", 600, 3400, 25,
1456*4882a593Smuzhiyun RK817_LDO_ON_VSEL_REG(6), RK817_LDO_VSEL_MASK,
1457*4882a593Smuzhiyun RK817_POWER_EN_REG(2), ENABLE_MASK(2), BIT(2),
1458*4882a593Smuzhiyun DISABLE_VAL(2), 400),
1459*4882a593Smuzhiyun RK817_DESC(RK817_ID_LDO8, "LDO_REG8", "vcc7", 600, 3400, 25,
1460*4882a593Smuzhiyun RK817_LDO_ON_VSEL_REG(7), RK817_LDO_VSEL_MASK,
1461*4882a593Smuzhiyun RK817_POWER_EN_REG(2), ENABLE_MASK(3), BIT(3),
1462*4882a593Smuzhiyun DISABLE_VAL(3), 400),
1463*4882a593Smuzhiyun RK817_DESC(RK817_ID_LDO9, "LDO_REG9", "vcc7", 600, 3400, 25,
1464*4882a593Smuzhiyun RK817_LDO_ON_VSEL_REG(8), RK817_LDO_VSEL_MASK,
1465*4882a593Smuzhiyun RK817_POWER_EN_REG(3), ENABLE_MASK(0), BIT(0),
1466*4882a593Smuzhiyun DISABLE_VAL(0), 400),
1467*4882a593Smuzhiyun RK817_BOOST_DESC(RK817_ID_BOOST, "BOOST", "vcc8", 4700, 5400, 100,
1468*4882a593Smuzhiyun RK817_BOOST_OTG_CFG, RK817_BOOST_VSEL_MASK,
1469*4882a593Smuzhiyun RK817_POWER_EN_REG(3), ENABLE_MASK(1), BIT(1),
1470*4882a593Smuzhiyun DISABLE_VAL(1), 400, 3500 - 5400),
1471*4882a593Smuzhiyun RK817_DESC_SWITCH(RK817_ID_BOOST_OTG_SW, "OTG_SWITCH", "vcc9",
1472*4882a593Smuzhiyun RK817_POWER_EN_REG(3), ENABLE_MASK(2), BIT(2),
1473*4882a593Smuzhiyun DISABLE_VAL(2)),
1474*4882a593Smuzhiyun };
1475*4882a593Smuzhiyun
1476*4882a593Smuzhiyun static const struct regulator_desc rk818_reg[] = {
1477*4882a593Smuzhiyun {
1478*4882a593Smuzhiyun .name = "DCDC_REG1",
1479*4882a593Smuzhiyun .supply_name = "vcc1",
1480*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG1"),
1481*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1482*4882a593Smuzhiyun .id = RK818_ID_DCDC1,
1483*4882a593Smuzhiyun .ops = &rk808_reg_ops,
1484*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1485*4882a593Smuzhiyun .min_uV = 712500,
1486*4882a593Smuzhiyun .uV_step = 12500,
1487*4882a593Smuzhiyun .n_voltages = 64,
1488*4882a593Smuzhiyun .vsel_reg = RK818_BUCK1_ON_VSEL_REG,
1489*4882a593Smuzhiyun .vsel_mask = RK818_BUCK_VSEL_MASK,
1490*4882a593Smuzhiyun .enable_reg = RK818_DCDC_EN_REG,
1491*4882a593Smuzhiyun .enable_mask = BIT(0),
1492*4882a593Smuzhiyun .owner = THIS_MODULE,
1493*4882a593Smuzhiyun }, {
1494*4882a593Smuzhiyun .name = "DCDC_REG2",
1495*4882a593Smuzhiyun .supply_name = "vcc2",
1496*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG2"),
1497*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1498*4882a593Smuzhiyun .id = RK818_ID_DCDC2,
1499*4882a593Smuzhiyun .ops = &rk808_reg_ops,
1500*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1501*4882a593Smuzhiyun .min_uV = 712500,
1502*4882a593Smuzhiyun .uV_step = 12500,
1503*4882a593Smuzhiyun .n_voltages = 64,
1504*4882a593Smuzhiyun .vsel_reg = RK818_BUCK2_ON_VSEL_REG,
1505*4882a593Smuzhiyun .vsel_mask = RK818_BUCK_VSEL_MASK,
1506*4882a593Smuzhiyun .enable_reg = RK818_DCDC_EN_REG,
1507*4882a593Smuzhiyun .enable_mask = BIT(1),
1508*4882a593Smuzhiyun .owner = THIS_MODULE,
1509*4882a593Smuzhiyun }, {
1510*4882a593Smuzhiyun .name = "DCDC_REG3",
1511*4882a593Smuzhiyun .supply_name = "vcc3",
1512*4882a593Smuzhiyun .of_match = of_match_ptr("DCDC_REG3"),
1513*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1514*4882a593Smuzhiyun .id = RK818_ID_DCDC3,
1515*4882a593Smuzhiyun .ops = &rk808_switch_ops,
1516*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1517*4882a593Smuzhiyun .n_voltages = 1,
1518*4882a593Smuzhiyun .enable_reg = RK818_DCDC_EN_REG,
1519*4882a593Smuzhiyun .enable_mask = BIT(2),
1520*4882a593Smuzhiyun .owner = THIS_MODULE,
1521*4882a593Smuzhiyun },
1522*4882a593Smuzhiyun RK8XX_DESC(RK818_ID_DCDC4, "DCDC_REG4", "vcc4", 1800, 3600, 100,
1523*4882a593Smuzhiyun RK818_BUCK4_ON_VSEL_REG, RK818_BUCK4_VSEL_MASK,
1524*4882a593Smuzhiyun RK818_DCDC_EN_REG, BIT(3), 0),
1525*4882a593Smuzhiyun RK8XX_DESC(RK818_ID_BOOST, "DCDC_BOOST", "boost", 4700, 5400, 100,
1526*4882a593Smuzhiyun RK818_BOOST_LDO9_ON_VSEL_REG, RK818_BOOST_ON_VSEL_MASK,
1527*4882a593Smuzhiyun RK818_DCDC_EN_REG, BIT(4), 0),
1528*4882a593Smuzhiyun RK8XX_DESC(RK818_ID_LDO1, "LDO_REG1", "vcc6", 1800, 3400, 100,
1529*4882a593Smuzhiyun RK818_LDO1_ON_VSEL_REG, RK818_LDO_VSEL_MASK, RK818_LDO_EN_REG,
1530*4882a593Smuzhiyun BIT(0), 400),
1531*4882a593Smuzhiyun RK8XX_DESC(RK818_ID_LDO2, "LDO_REG2", "vcc6", 1800, 3400, 100,
1532*4882a593Smuzhiyun RK818_LDO2_ON_VSEL_REG, RK818_LDO_VSEL_MASK, RK818_LDO_EN_REG,
1533*4882a593Smuzhiyun BIT(1), 400),
1534*4882a593Smuzhiyun {
1535*4882a593Smuzhiyun .name = "LDO_REG3",
1536*4882a593Smuzhiyun .supply_name = "vcc7",
1537*4882a593Smuzhiyun .of_match = of_match_ptr("LDO_REG3"),
1538*4882a593Smuzhiyun .regulators_node = of_match_ptr("regulators"),
1539*4882a593Smuzhiyun .id = RK818_ID_LDO3,
1540*4882a593Smuzhiyun .ops = &rk808_reg_ops_ranges,
1541*4882a593Smuzhiyun .type = REGULATOR_VOLTAGE,
1542*4882a593Smuzhiyun .n_voltages = 16,
1543*4882a593Smuzhiyun .linear_ranges = rk808_ldo3_voltage_ranges,
1544*4882a593Smuzhiyun .n_linear_ranges = ARRAY_SIZE(rk808_ldo3_voltage_ranges),
1545*4882a593Smuzhiyun .vsel_reg = RK818_LDO3_ON_VSEL_REG,
1546*4882a593Smuzhiyun .vsel_mask = RK818_LDO3_ON_VSEL_MASK,
1547*4882a593Smuzhiyun .enable_reg = RK818_LDO_EN_REG,
1548*4882a593Smuzhiyun .enable_mask = BIT(2),
1549*4882a593Smuzhiyun .enable_time = 400,
1550*4882a593Smuzhiyun .owner = THIS_MODULE,
1551*4882a593Smuzhiyun },
1552*4882a593Smuzhiyun RK8XX_DESC(RK818_ID_LDO4, "LDO_REG4", "vcc8", 1800, 3400, 100,
1553*4882a593Smuzhiyun RK818_LDO4_ON_VSEL_REG, RK818_LDO_VSEL_MASK, RK818_LDO_EN_REG,
1554*4882a593Smuzhiyun BIT(3), 400),
1555*4882a593Smuzhiyun RK8XX_DESC(RK818_ID_LDO5, "LDO_REG5", "vcc7", 1800, 3400, 100,
1556*4882a593Smuzhiyun RK818_LDO5_ON_VSEL_REG, RK818_LDO_VSEL_MASK, RK818_LDO_EN_REG,
1557*4882a593Smuzhiyun BIT(4), 400),
1558*4882a593Smuzhiyun RK8XX_DESC(RK818_ID_LDO6, "LDO_REG6", "vcc8", 800, 2500, 100,
1559*4882a593Smuzhiyun RK818_LDO6_ON_VSEL_REG, RK818_LDO_VSEL_MASK, RK818_LDO_EN_REG,
1560*4882a593Smuzhiyun BIT(5), 400),
1561*4882a593Smuzhiyun RK8XX_DESC(RK818_ID_LDO7, "LDO_REG7", "vcc7", 800, 2500, 100,
1562*4882a593Smuzhiyun RK818_LDO7_ON_VSEL_REG, RK818_LDO_VSEL_MASK, RK818_LDO_EN_REG,
1563*4882a593Smuzhiyun BIT(6), 400),
1564*4882a593Smuzhiyun RK8XX_DESC(RK818_ID_LDO8, "LDO_REG8", "vcc8", 1800, 3400, 100,
1565*4882a593Smuzhiyun RK818_LDO8_ON_VSEL_REG, RK818_LDO_VSEL_MASK, RK818_LDO_EN_REG,
1566*4882a593Smuzhiyun BIT(7), 400),
1567*4882a593Smuzhiyun RK8XX_DESC(RK818_ID_LDO9, "LDO_REG9", "vcc9", 1800, 3400, 100,
1568*4882a593Smuzhiyun RK818_BOOST_LDO9_ON_VSEL_REG, RK818_LDO_VSEL_MASK,
1569*4882a593Smuzhiyun RK818_DCDC_EN_REG, BIT(5), 400),
1570*4882a593Smuzhiyun RK8XX_DESC_SWITCH(RK818_ID_SWITCH, "SWITCH_REG", "vcc9",
1571*4882a593Smuzhiyun RK818_DCDC_EN_REG, BIT(6)),
1572*4882a593Smuzhiyun RK8XX_DESC_SWITCH(RK818_ID_HDMI_SWITCH, "HDMI_SWITCH", "h_5v",
1573*4882a593Smuzhiyun RK818_H5V_EN_REG, BIT(0)),
1574*4882a593Smuzhiyun RK8XX_DESC_SWITCH(RK818_ID_OTG_SWITCH, "OTG_SWITCH", "usb",
1575*4882a593Smuzhiyun RK818_DCDC_EN_REG, BIT(7)),
1576*4882a593Smuzhiyun };
1577*4882a593Smuzhiyun
rk808_regulator_dt_parse_pdata(struct device * dev,struct device * client_dev,struct regmap * map,struct rk808_regulator_data * pdata)1578*4882a593Smuzhiyun static int rk808_regulator_dt_parse_pdata(struct device *dev,
1579*4882a593Smuzhiyun struct device *client_dev,
1580*4882a593Smuzhiyun struct regmap *map,
1581*4882a593Smuzhiyun struct rk808_regulator_data *pdata)
1582*4882a593Smuzhiyun {
1583*4882a593Smuzhiyun struct device_node *np;
1584*4882a593Smuzhiyun int tmp, ret = 0, i;
1585*4882a593Smuzhiyun
1586*4882a593Smuzhiyun np = of_get_child_by_name(client_dev->of_node, "regulators");
1587*4882a593Smuzhiyun if (!np)
1588*4882a593Smuzhiyun return -ENXIO;
1589*4882a593Smuzhiyun
1590*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(pdata->dvs_gpio); i++) {
1591*4882a593Smuzhiyun pdata->dvs_gpio[i] =
1592*4882a593Smuzhiyun devm_gpiod_get_index_optional(client_dev, "dvs", i,
1593*4882a593Smuzhiyun GPIOD_OUT_LOW);
1594*4882a593Smuzhiyun if (IS_ERR(pdata->dvs_gpio[i])) {
1595*4882a593Smuzhiyun ret = PTR_ERR(pdata->dvs_gpio[i]);
1596*4882a593Smuzhiyun dev_err(dev, "failed to get dvs%d gpio (%d)\n", i, ret);
1597*4882a593Smuzhiyun goto dt_parse_end;
1598*4882a593Smuzhiyun }
1599*4882a593Smuzhiyun
1600*4882a593Smuzhiyun if (!pdata->dvs_gpio[i]) {
1601*4882a593Smuzhiyun dev_info(dev, "there is no dvs%d gpio\n", i);
1602*4882a593Smuzhiyun continue;
1603*4882a593Smuzhiyun }
1604*4882a593Smuzhiyun
1605*4882a593Smuzhiyun tmp = i ? RK808_DVS2_POL : RK808_DVS1_POL;
1606*4882a593Smuzhiyun ret = regmap_update_bits(map, RK808_IO_POL_REG, tmp,
1607*4882a593Smuzhiyun gpiod_is_active_low(pdata->dvs_gpio[i]) ?
1608*4882a593Smuzhiyun 0 : tmp);
1609*4882a593Smuzhiyun }
1610*4882a593Smuzhiyun
1611*4882a593Smuzhiyun dt_parse_end:
1612*4882a593Smuzhiyun of_node_put(np);
1613*4882a593Smuzhiyun return ret;
1614*4882a593Smuzhiyun }
1615*4882a593Smuzhiyun
rk808_regulator_probe(struct platform_device * pdev)1616*4882a593Smuzhiyun static int rk808_regulator_probe(struct platform_device *pdev)
1617*4882a593Smuzhiyun {
1618*4882a593Smuzhiyun struct rk808 *rk808 = dev_get_drvdata(pdev->dev.parent);
1619*4882a593Smuzhiyun struct i2c_client *client = rk808->i2c;
1620*4882a593Smuzhiyun struct regulator_config config = {};
1621*4882a593Smuzhiyun struct regulator_dev *rk808_rdev;
1622*4882a593Smuzhiyun struct rk808_regulator_data *pdata;
1623*4882a593Smuzhiyun const struct regulator_desc *regulators;
1624*4882a593Smuzhiyun int ret, i, nregulators;
1625*4882a593Smuzhiyun
1626*4882a593Smuzhiyun pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1627*4882a593Smuzhiyun if (!pdata)
1628*4882a593Smuzhiyun return -ENOMEM;
1629*4882a593Smuzhiyun
1630*4882a593Smuzhiyun ret = rk808_regulator_dt_parse_pdata(&pdev->dev, &client->dev,
1631*4882a593Smuzhiyun rk808->regmap, pdata);
1632*4882a593Smuzhiyun if (ret < 0)
1633*4882a593Smuzhiyun return ret;
1634*4882a593Smuzhiyun
1635*4882a593Smuzhiyun platform_set_drvdata(pdev, pdata);
1636*4882a593Smuzhiyun
1637*4882a593Smuzhiyun switch (rk808->variant) {
1638*4882a593Smuzhiyun case RK805_ID:
1639*4882a593Smuzhiyun regulators = rk805_reg;
1640*4882a593Smuzhiyun nregulators = RK805_NUM_REGULATORS;
1641*4882a593Smuzhiyun break;
1642*4882a593Smuzhiyun case RK808_ID:
1643*4882a593Smuzhiyun regulators = rk808_reg;
1644*4882a593Smuzhiyun nregulators = RK808_NUM_REGULATORS;
1645*4882a593Smuzhiyun break;
1646*4882a593Smuzhiyun case RK809_ID:
1647*4882a593Smuzhiyun regulators = rk809_reg;
1648*4882a593Smuzhiyun nregulators = RK809_NUM_REGULATORS;
1649*4882a593Smuzhiyun break;
1650*4882a593Smuzhiyun case RK816_ID:
1651*4882a593Smuzhiyun regulators = rk816_reg;
1652*4882a593Smuzhiyun nregulators = RK816_NUM_REGULATORS;
1653*4882a593Smuzhiyun break;
1654*4882a593Smuzhiyun case RK817_ID:
1655*4882a593Smuzhiyun regulators = rk817_reg;
1656*4882a593Smuzhiyun nregulators = RK817_NUM_REGULATORS;
1657*4882a593Smuzhiyun break;
1658*4882a593Smuzhiyun case RK818_ID:
1659*4882a593Smuzhiyun regulators = rk818_reg;
1660*4882a593Smuzhiyun nregulators = RK818_NUM_REGULATORS;
1661*4882a593Smuzhiyun break;
1662*4882a593Smuzhiyun default:
1663*4882a593Smuzhiyun dev_err(&client->dev, "unsupported RK8XX ID %lu\n",
1664*4882a593Smuzhiyun rk808->variant);
1665*4882a593Smuzhiyun return -EINVAL;
1666*4882a593Smuzhiyun }
1667*4882a593Smuzhiyun
1668*4882a593Smuzhiyun config.dev = &client->dev;
1669*4882a593Smuzhiyun config.driver_data = pdata;
1670*4882a593Smuzhiyun config.regmap = rk808->regmap;
1671*4882a593Smuzhiyun
1672*4882a593Smuzhiyun /* Instantiate the regulators */
1673*4882a593Smuzhiyun for (i = 0; i < nregulators; i++) {
1674*4882a593Smuzhiyun rk808_rdev = devm_regulator_register(&pdev->dev,
1675*4882a593Smuzhiyun ®ulators[i], &config);
1676*4882a593Smuzhiyun if (IS_ERR(rk808_rdev)) {
1677*4882a593Smuzhiyun dev_err(&client->dev,
1678*4882a593Smuzhiyun "failed to register %d regulator\n", i);
1679*4882a593Smuzhiyun return PTR_ERR(rk808_rdev);
1680*4882a593Smuzhiyun }
1681*4882a593Smuzhiyun }
1682*4882a593Smuzhiyun
1683*4882a593Smuzhiyun return 0;
1684*4882a593Smuzhiyun }
1685*4882a593Smuzhiyun
1686*4882a593Smuzhiyun static struct platform_driver rk808_regulator_driver = {
1687*4882a593Smuzhiyun .probe = rk808_regulator_probe,
1688*4882a593Smuzhiyun .driver = {
1689*4882a593Smuzhiyun .name = "rk808-regulator"
1690*4882a593Smuzhiyun },
1691*4882a593Smuzhiyun };
1692*4882a593Smuzhiyun
1693*4882a593Smuzhiyun #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
rk808_regulator_driver_init(void)1694*4882a593Smuzhiyun static int __init rk808_regulator_driver_init(void)
1695*4882a593Smuzhiyun {
1696*4882a593Smuzhiyun return platform_driver_register(&rk808_regulator_driver);
1697*4882a593Smuzhiyun }
1698*4882a593Smuzhiyun subsys_initcall(rk808_regulator_driver_init);
1699*4882a593Smuzhiyun
rk808_regulator_driver_exit(void)1700*4882a593Smuzhiyun static void __exit rk808_regulator_driver_exit(void)
1701*4882a593Smuzhiyun {
1702*4882a593Smuzhiyun platform_driver_unregister(&rk808_regulator_driver);
1703*4882a593Smuzhiyun }
1704*4882a593Smuzhiyun module_exit(rk808_regulator_driver_exit);
1705*4882a593Smuzhiyun #else
1706*4882a593Smuzhiyun module_platform_driver(rk808_regulator_driver);
1707*4882a593Smuzhiyun #endif
1708*4882a593Smuzhiyun
1709*4882a593Smuzhiyun MODULE_DESCRIPTION("regulator driver for the RK805/RK808/RK816/RK818 series PMICs");
1710*4882a593Smuzhiyun MODULE_AUTHOR("Tony xie <tony.xie@rock-chips.com>");
1711*4882a593Smuzhiyun MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1712*4882a593Smuzhiyun MODULE_AUTHOR("Zhang Qing <zhangqing@rock-chips.com>");
1713*4882a593Smuzhiyun MODULE_AUTHOR("Wadim Egorov <w.egorov@phytec.de>");
1714*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1715*4882a593Smuzhiyun MODULE_ALIAS("platform:rk808-regulator");
1716