xref: /OK3568_Linux_fs/kernel/drivers/regulator/rc5t583-regulator.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Regulator driver for RICOH RC5T583 power management chip.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
6*4882a593Smuzhiyun  * Author: Laxman dewangan <ldewangan@nvidia.com>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * based on code
9*4882a593Smuzhiyun  *      Copyright (C) 2011 RICOH COMPANY,LTD
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun #include <linux/err.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/regulator/driver.h>
18*4882a593Smuzhiyun #include <linux/regulator/machine.h>
19*4882a593Smuzhiyun #include <linux/gpio.h>
20*4882a593Smuzhiyun #include <linux/mfd/rc5t583.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun struct rc5t583_regulator_info {
23*4882a593Smuzhiyun 	int			deepsleep_id;
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun 	/* Regulator register address.*/
26*4882a593Smuzhiyun 	uint8_t			reg_disc_reg;
27*4882a593Smuzhiyun 	uint8_t			disc_bit;
28*4882a593Smuzhiyun 	uint8_t			deepsleep_reg;
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun 	/* Regulator specific turn-on delay  and voltage settling time*/
31*4882a593Smuzhiyun 	int			enable_uv_per_us;
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun 	/* Used by regulator core */
34*4882a593Smuzhiyun 	struct regulator_desc	desc;
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun 
rc5t583_regulator_enable_time(struct regulator_dev * rdev)37*4882a593Smuzhiyun static int rc5t583_regulator_enable_time(struct regulator_dev *rdev)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun 	struct rc5t583_regulator_info *reg_info = rdev_get_drvdata(rdev);
40*4882a593Smuzhiyun 	int vsel = regulator_get_voltage_sel_regmap(rdev);
41*4882a593Smuzhiyun 	int curr_uV = regulator_list_voltage_linear(rdev, vsel);
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun 	return DIV_ROUND_UP(curr_uV, reg_info->enable_uv_per_us);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun static const struct regulator_ops rc5t583_ops = {
47*4882a593Smuzhiyun 	.is_enabled		= regulator_is_enabled_regmap,
48*4882a593Smuzhiyun 	.enable			= regulator_enable_regmap,
49*4882a593Smuzhiyun 	.disable		= regulator_disable_regmap,
50*4882a593Smuzhiyun 	.enable_time		= rc5t583_regulator_enable_time,
51*4882a593Smuzhiyun 	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
52*4882a593Smuzhiyun 	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
53*4882a593Smuzhiyun 	.list_voltage		= regulator_list_voltage_linear,
54*4882a593Smuzhiyun 	.map_voltage		= regulator_map_voltage_linear,
55*4882a593Smuzhiyun 	.set_voltage_time_sel	= regulator_set_voltage_time_sel,
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun #define RC5T583_REG(_id, _en_reg, _en_bit, _disc_reg, _disc_bit, \
59*4882a593Smuzhiyun 		_vout_mask, _min_mv, _max_mv, _step_uV, _enable_mv) \
60*4882a593Smuzhiyun {								\
61*4882a593Smuzhiyun 	.reg_disc_reg	= RC5T583_REG_##_disc_reg,		\
62*4882a593Smuzhiyun 	.disc_bit	= _disc_bit,				\
63*4882a593Smuzhiyun 	.deepsleep_reg	= RC5T583_REG_##_id##DAC_DS,		\
64*4882a593Smuzhiyun 	.enable_uv_per_us = _enable_mv * 1000,			\
65*4882a593Smuzhiyun 	.deepsleep_id	= RC5T583_DS_##_id,			\
66*4882a593Smuzhiyun 	.desc = {						\
67*4882a593Smuzhiyun 		.name = "rc5t583-regulator-"#_id,		\
68*4882a593Smuzhiyun 		.id = RC5T583_REGULATOR_##_id,			\
69*4882a593Smuzhiyun 		.n_voltages = (_max_mv - _min_mv) * 1000 / _step_uV + 1, \
70*4882a593Smuzhiyun 		.ops = &rc5t583_ops,				\
71*4882a593Smuzhiyun 		.type = REGULATOR_VOLTAGE,			\
72*4882a593Smuzhiyun 		.owner = THIS_MODULE,				\
73*4882a593Smuzhiyun 		.vsel_reg = RC5T583_REG_##_id##DAC,		\
74*4882a593Smuzhiyun 		.vsel_mask = _vout_mask,			\
75*4882a593Smuzhiyun 		.enable_reg = RC5T583_REG_##_en_reg,		\
76*4882a593Smuzhiyun 		.enable_mask = BIT(_en_bit),			\
77*4882a593Smuzhiyun 		.min_uV	= _min_mv * 1000,			\
78*4882a593Smuzhiyun 		.uV_step = _step_uV,				\
79*4882a593Smuzhiyun 		.ramp_delay = 40 * 1000,			\
80*4882a593Smuzhiyun 	},							\
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun static struct rc5t583_regulator_info rc5t583_reg_info[RC5T583_REGULATOR_MAX] = {
84*4882a593Smuzhiyun 	RC5T583_REG(DC0, DC0CTL, 0, DC0CTL, 1, 0x7F, 700, 1500, 12500, 4),
85*4882a593Smuzhiyun 	RC5T583_REG(DC1, DC1CTL, 0, DC1CTL, 1, 0x7F, 700, 1500, 12500, 14),
86*4882a593Smuzhiyun 	RC5T583_REG(DC2, DC2CTL, 0, DC2CTL, 1, 0x7F, 900, 2400, 12500, 14),
87*4882a593Smuzhiyun 	RC5T583_REG(DC3, DC3CTL, 0, DC3CTL, 1, 0x7F, 900, 2400, 12500, 14),
88*4882a593Smuzhiyun 	RC5T583_REG(LDO0, LDOEN2, 0, LDODIS2, 0, 0x7F, 900, 3400, 25000, 160),
89*4882a593Smuzhiyun 	RC5T583_REG(LDO1, LDOEN2, 1, LDODIS2, 1, 0x7F, 900, 3400, 25000, 160),
90*4882a593Smuzhiyun 	RC5T583_REG(LDO2, LDOEN2, 2, LDODIS2, 2, 0x7F, 900, 3400, 25000, 160),
91*4882a593Smuzhiyun 	RC5T583_REG(LDO3, LDOEN2, 3, LDODIS2, 3, 0x7F, 900, 3400, 25000, 160),
92*4882a593Smuzhiyun 	RC5T583_REG(LDO4, LDOEN2, 4, LDODIS2, 4, 0x3F, 750, 1500, 12500, 133),
93*4882a593Smuzhiyun 	RC5T583_REG(LDO5, LDOEN2, 5, LDODIS2, 5, 0x7F, 900, 3400, 25000, 267),
94*4882a593Smuzhiyun 	RC5T583_REG(LDO6, LDOEN2, 6, LDODIS2, 6, 0x7F, 900, 3400, 25000, 133),
95*4882a593Smuzhiyun 	RC5T583_REG(LDO7, LDOEN2, 7, LDODIS2, 7, 0x7F, 900, 3400, 25000, 233),
96*4882a593Smuzhiyun 	RC5T583_REG(LDO8, LDOEN1, 0, LDODIS1, 0, 0x7F, 900, 3400, 25000, 233),
97*4882a593Smuzhiyun 	RC5T583_REG(LDO9, LDOEN1, 1, LDODIS1, 1, 0x7F, 900, 3400, 25000, 133),
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun 
rc5t583_regulator_probe(struct platform_device * pdev)100*4882a593Smuzhiyun static int rc5t583_regulator_probe(struct platform_device *pdev)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun 	struct rc5t583 *rc5t583 = dev_get_drvdata(pdev->dev.parent);
103*4882a593Smuzhiyun 	struct rc5t583_platform_data *pdata = dev_get_platdata(rc5t583->dev);
104*4882a593Smuzhiyun 	struct regulator_config config = { };
105*4882a593Smuzhiyun 	struct regulator_dev *rdev;
106*4882a593Smuzhiyun 	struct rc5t583_regulator_info *ri;
107*4882a593Smuzhiyun 	int ret;
108*4882a593Smuzhiyun 	int id;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	if (!pdata) {
111*4882a593Smuzhiyun 		dev_err(&pdev->dev, "No platform data, exiting...\n");
112*4882a593Smuzhiyun 		return -ENODEV;
113*4882a593Smuzhiyun 	}
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	for (id = 0; id < RC5T583_REGULATOR_MAX; ++id) {
116*4882a593Smuzhiyun 		ri = &rc5t583_reg_info[id];
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 		if (ri->deepsleep_id == RC5T583_DS_NONE)
119*4882a593Smuzhiyun 			goto skip_ext_pwr_config;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 		ret = rc5t583_ext_power_req_config(rc5t583->dev,
122*4882a593Smuzhiyun 				ri->deepsleep_id,
123*4882a593Smuzhiyun 				pdata->regulator_ext_pwr_control[id],
124*4882a593Smuzhiyun 				pdata->regulator_deepsleep_slot[id]);
125*4882a593Smuzhiyun 		/*
126*4882a593Smuzhiyun 		 * Configuring external control is not a major issue,
127*4882a593Smuzhiyun 		 * just give warning.
128*4882a593Smuzhiyun 		 */
129*4882a593Smuzhiyun 		if (ret < 0)
130*4882a593Smuzhiyun 			dev_warn(&pdev->dev,
131*4882a593Smuzhiyun 				"Failed to configure ext control %d\n", id);
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun skip_ext_pwr_config:
134*4882a593Smuzhiyun 		config.dev = &pdev->dev;
135*4882a593Smuzhiyun 		config.init_data = pdata->reg_init_data[id];
136*4882a593Smuzhiyun 		config.driver_data = ri;
137*4882a593Smuzhiyun 		config.regmap = rc5t583->regmap;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 		rdev = devm_regulator_register(&pdev->dev, &ri->desc, &config);
140*4882a593Smuzhiyun 		if (IS_ERR(rdev)) {
141*4882a593Smuzhiyun 			dev_err(&pdev->dev, "Failed to register regulator %s\n",
142*4882a593Smuzhiyun 						ri->desc.name);
143*4882a593Smuzhiyun 			return PTR_ERR(rdev);
144*4882a593Smuzhiyun 		}
145*4882a593Smuzhiyun 	}
146*4882a593Smuzhiyun 	return 0;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun static struct platform_driver rc5t583_regulator_driver = {
150*4882a593Smuzhiyun 	.driver	= {
151*4882a593Smuzhiyun 		.name	= "rc5t583-regulator",
152*4882a593Smuzhiyun 	},
153*4882a593Smuzhiyun 	.probe		= rc5t583_regulator_probe,
154*4882a593Smuzhiyun };
155*4882a593Smuzhiyun 
rc5t583_regulator_init(void)156*4882a593Smuzhiyun static int __init rc5t583_regulator_init(void)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun 	return platform_driver_register(&rc5t583_regulator_driver);
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun subsys_initcall(rc5t583_regulator_init);
161*4882a593Smuzhiyun 
rc5t583_regulator_exit(void)162*4882a593Smuzhiyun static void __exit rc5t583_regulator_exit(void)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun 	platform_driver_unregister(&rc5t583_regulator_driver);
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun module_exit(rc5t583_regulator_exit);
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
169*4882a593Smuzhiyun MODULE_DESCRIPTION("RC5T583 regulator driver");
170*4882a593Smuzhiyun MODULE_ALIAS("platform:rc5t583-regulator");
171*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
172